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e373aad32a
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond. Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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.. | ||
clock.h | ||
clock_sun4i.h | ||
clock_sun6i.h | ||
cpu.h | ||
dram.h | ||
gpio.h | ||
i2c.h | ||
mmc.h | ||
prcm.h | ||
spl.h | ||
sys_proto.h | ||
timer.h | ||
watchdog.h |