Commit graph

363 commits

Author SHA1 Message Date
Guillaume La Roque
f699cb1dd5 phy: meson-g12a-usb2: fix ret check on power_domain_get
Patch which add A1 SoC support create a regression on khadas vim3/vim3l
boards when we try to use fastboot command:

  => fastboot usb 0
  failed to get power domain
  failed to get power domain
  No USB device found
  USB init failed: -19

Add ENOENT check on ret in probe function.

Fixes: 5533c883ce ("phy: support Amlogic A1 family")

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231017185725.809524-1-glaroque@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-18 09:45:48 +02:00
Tom Rini
2e1577e836 - add Amlogic A1 clock driver
- add Amlogic A1 reset support
 - add USB Device support for Amlogic A1
 - enable RNG on Amlogic A1 & Amlogic S4
 - move Amlogic Secure Monitor to standalone driver
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Merge tag 'u-boot-amlogic-20231015' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- add Amlogic A1 clock driver
- add Amlogic A1 reset support
- add USB Device support for Amlogic A1
- enable RNG on Amlogic A1 & Amlogic S4
- move Amlogic Secure Monitor to standalone driver
2023-10-16 09:09:54 -04:00
Matthias Schiffer
5fecea171d treewide: use dev_read_addr_*_ptr() where appropriate
A follow-up to commit 842fb5de42
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").

In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.

This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-13 14:01:42 -06:00
Alexey Romanov
5533c883ce phy: support Amlogic A1 family
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Alexey Romanov
80f45c3b36 phy: move clk enable/disable in init/exit
It is better to place clk_enable() in phy_meson_g12a_usb2_init()
and clk_disable() in phy_meson_g12a_usb2_exit().

For more detailed information, please see comments in the review of
a similar driver in the Linux Kernel:

https://lore.kernel.org/all/CAFBinCCEhobbyKHuKDWzTYCQWgNT1-e8=7hMhq1mvT6CuEOjGw@mail.gmail.com/

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-5-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Alexey Romanov
881714983e phy: get rid of raw hex values
It is better to use defines instead of write raw
hex values in regmap.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-4-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Jonas Karlman
b37260bca1 phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588
Route signal from comb PHY instead of PCIe3 PHY to PCIe1l0 and PCIe1l1.

Fixes use of pcie2x1l0 on ROCK 5B.

Code imported from mainline linux driver.

Fixes: c5b4a012bc ("phy: rockchip: naneng-combphy: Support rk3588")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07 10:23:12 +08:00
Jonas Karlman
50e54e8067 phy: rockchip: snps-pcie3: Add support for RK3588
Add support for the RK3588 variant to the driver.

Code imported almost 1:1 from mainline linux driver.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07 10:23:12 +08:00
Jonas Karlman
1ebebfcc25 phy: rockchip: snps-pcie3: Add bifurcation support for RK3568
Configure aggregation or bifurcation mode on RK3568 based on the value
of data-lanes property.

Code imported almost 1:1 from mainline linux driver.

Fixes: 6ec62b6ca6 ("phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07 10:23:12 +08:00
Jonas Karlman
6cacdf842d phy: rockchip: snps-pcie3: Refactor to use a phy_init ops
Add a phy_init ops in preparation for upcoming support of a RK3588
variant in the driver.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07 10:23:12 +08:00
Jonas Karlman
3b39592e8e phy: rockchip: snps-pcie3: Refactor to use clk_bulk API
Change to use clk_bulk API and syscon_regmap_lookup_by_phandle to
simplify in preparation for upcoming support of a RK3588 variant.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07 10:23:12 +08:00
Simon Glass
1e94b46f73 common: Drop linux/printk.h from common header
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h

Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-24 09:54:57 -04:00
Jonas Karlman
565f556d0b phy: Refactor generic_{setup, shutdown}_phy() to reduce complexity
Refactor generic_{setup,shutdown}_phy() to reduce complexity and
indentation. This have no intended functional change.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-09-13 15:52:21 -04:00
Jonas Karlman
1a4293e001 phy: Return success from generic_setup_phy() when phy is not found
Restore the old behavior of ehci_setup_phy() and ohci_setup_phy() to
return success when generic_phy_get_by_index() return -ENOENT.

Fixes: 84e561407a ("phy: Add generic_{setup,shutdown}_phy() helpers")
Fixes: 10005004db ("usb: ohci: Make usage of generic_{setup,shutdown}_phy() helpers")
Fixes: 083f8aa978 ("usb: ehci: Make usage of generic_{setup,shutdown}_phy() helpers")
Fixes: 75341e9c16 ("usb: ehci: Remove unused ehci_{setup,shutdown}_phy() helpers")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-09-13 15:52:21 -04:00
Jonas Karlman
bd78f2c2c2 phy: Fix generic_setup_phy() return value on power on failure
generic_phy_exit() typically return 0 for a struct phy that has been
initialized with a generic_phy_init() call.

generic_setup_phy() returns the value from a generic_phy_exit() call
when generic_phy_power_on() fails. This hides the failed state of the
power_on ops from the caller of generic_setup_phy().

Fix this by ignoring the return value of the generic_phy_exit() call and
return the value from the generic_phy_power_on() call.

Fixes: 84e561407a ("phy: Add generic_{setup,shutdown}_phy() helpers")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-09-13 15:52:21 -04:00
Jonas Karlman
14639bf14d phy: Set phy->dev to NULL when generic_phy_get_by_index_nodev() fails
Generic phy helpers typically use generic_phy_valid() to determine if
the helper should perform its function on a passed struct phy.
generic_phy_valid() treat any struct phy having phy->dev set as valid.

With generic_phy_get_by_index_nodev() setting phy->dev to a valid struct
udevice early, there can be situations where the struct phy is returned
as valid when initialization in fact failed and returned an error.

Fix this by setting phy->dev back to NULL when any of the calls to
of_xlate ops, device_get_supply_regulator or phy_alloc_counts fail. Also
extend the dm_test_phy_base test with a test where of_xlate ops fail.

Fixes: 72e5016f87 ("drivers: phy: add generic PHY framework")
Fixes: b9688df3cb ("drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-09-13 15:52:20 -04:00
Jonas Karlman
feb4b919ab phy: Set phy->dev to NULL when generic_phy_get_by_name() fails
generic_phy_get_by_name() does not initialize phy->dev to NULL before
returning when dev_read_stringlist_search() fails. This can lead to an
uninitialized or reused struct phy erroneously be report as valid by
generic_phy_valid().

Fix this issue by initializing phy->dev to NULL, also extend the
dm_test_phy_base test with calls to generic_phy_valid().

Fixes: b9688df3cb ("drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails")
Fixes: 868d58f69c ("usb: dwc3: Fix non-usb3 configurations")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-09-13 15:52:20 -04:00
Tom Rini
ddec4cae62 Prepare v2023.10-rc4
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Merge tag 'v2023.10-rc4' into next

Prepare v2023.10-rc4
2023-09-04 10:51:58 -04:00
Tim Harvey
e3380e1c1a phy: phy-imx8mq-usb: clean up clock code
use CONFIG_IS_ENABLED for clock enable/disable and change printf's
to dev_err. Additionlly remove the comment that does not make sense.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-08-25 02:36:19 +02:00
Tim Harvey
c90729c463 phy: phy-imx8mq-usb: add vbus regulator support
Add support for enabling and disabling vbus-supply regulator found
on several imx8mp boards in the usb3_phy0 and usb3_phy1 nodes.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-08-25 02:36:19 +02:00
Siddharth Vadapalli
cb6f4bbe3f phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E
Enable full rate divider configuration support for J721E_WIZ_16G for SGMII.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15 17:46:39 -04:00
Siddharth Vadapalli
0914616156 phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200
Select the same mac divider for SGMII too as the one being used for
QSGMII.

Enable full rate divider configuration support for J721E_WIZ_10G for
SGMII.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15 17:46:39 -04:00
Mark Kettenis
b99c635787 phy: Add support for the Apple Type-C PHY
This is merely a dummy driver that makes sure the DWC3 XHCI driver
finds its reset and PHY controllers.  We rely on iBoot to set up
the PHY for us.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-08-14 17:51:51 -04:00
Jagan Teki
9aa93d8403 phy: rockchip-inno-usb2: Add USB2 PHY for RK3328
USB2.0 Host and OTG controllers in RK3328 are using USB2PHY.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31 20:33:18 +08:00
Frank Wang
7b57ca18f8 phy: rockchip: add usbdp combo phy driver
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28 18:45:02 +08:00
Andre Przywara
830b3a8e40 phy: sun4i: Add H616 USB PHY support
Now that the Allwinner USB PHY driver supports the H616 quirk, let's
enable support for USB ports on that SoC.

We connect the compatible string to a new struct describing the SoCs USB
PHY properties, and unblock the PHY driver selection in Kconfig.

A later patch will enable USB support in the H616 boards' defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:28:13 +01:00
Andre Przywara
730b452caa phy: sun4i-usb: Add H616 USB PHY quirk support
The H616 USB PHY is some kind of special snowflake: Only port2 works out
of the box, but all other ports need some help from this port2 to work
correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be
enabled, and the SIDDQ bit in the PMU PHY control register needs to be
cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be
ungated. Don't ask ....

Follow the respective Linux patch (b45c6d80325b) and add a quirk bit,
triggering the special sequence as outlined above, for PHYs other than
PHY2: ungate this one special clock, and clear the SIDDQ bit. We also
pick the clock and reset from PHY2 and enable them as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:28:13 +01:00
Andre Przywara
d7a7fed55d phy: sun4i-usb: Replace types with explicit quirk flags
So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.

Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.

Port of Linux patch 8dd256bae653.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:28:13 +01:00
Andre Przywara
fcd9220d66 sunxi: Kconfig: rework PHY_USB_SUN4I selection
At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.

Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.

Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-07-21 00:26:36 +01:00
Andre Przywara
003fbb2f8e phy: sun4i-usb: add Allwinner F1C100s support
The Allwinner F1C100s implements a single USB PHY, connected to its MUSB
OTG controller. The USB PHY is of the simpler, older type (like the A10),
the only real difference is that it's indeed only one PHY.

Add a struct describing those F1C100s USB PHY properties, and connect it
to the new compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:21:42 +01:00
Andre Przywara
999bc5e660 phy: sun4i-usb: Fix of_xlate() argument check
In its of_xlate() function, the Allwinner USB PHY driver compares the
args_count variable against the number of implemented USB PHYs, although
this is the *number of arguments* to the DT phandle property. Per the DT
binding for this PHY device, this number is always one, so this check
will always fail if the particular SoC implements exactly one USB PHY.
So far this affected only the V3s (which has USB support disabled), but
the F1C100s also sports one PHY only.

Fix that check to compare args_count against exactly 1, and the args[0]
content (requested PHY number) against the number of implemented PHYs.

This fixes USB operation on the Allwinner V3s and allows to enable USB
on the Allwinner F1C100s SoC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:21:42 +01:00
Tom Rini
e80f4079b3 Prepare v2023.07-rc6
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Merge tag 'v2023.07-rc6' into next

Prepare v2023.07-rc6
2023-07-05 11:28:55 -04:00
Eugen Hristev
3cc537842f phy: rockchip: inno-usb2: fix phy reg=0 case
The support for #address-cells=2 has a loophole: if the reg is actually 0,
but the #address-cells is actually 1, like in such case below:

syscon {
	#address-cells = <1>;

	phy {
		reg = <0 0x10>;
	};
};

then the second u32 of the 'reg' is the size, not the address.

The code should check for the parent's #address-cells value, and not
assume that if the first u32 is 0, then the #address-cells is 2, and the
reg property is something like
	reg = <0 0xff00 0x10>;

Fixed this by looking for the #address-cells value and retrieving the
reg address only if this is ==2.
To avoid breaking anything I also kept the check `if reg==0` as some DT's
may have a wrong #address-cells as parent and even if this commit is
correct, it might break the existing wrong device-trees.

Fixes: d538efb9ad ("phy: rockchip: inno-usb2: Add support #address_cells = 2")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-06-29 18:31:48 +08:00
Tom Rini
7da82de916 Xilinx changes for v2023.10-rc1
global:
 - Use proper U-Boot project name
 
 Fix sparse warnings in zynqmp-clk, zynqmp handoff, board
 
 cmd:
 - Cover incorrect 0 length entries
 
 Versal NET:
 - Add bootmode logic
 - Support SPP production version
 - Add loadpdi command
 
 ZynqMP:
 - Clear pmufw node command ID handling
 - Change power domain behavior around zynqmp_pmufw_node()
 - Fix zynqmp cmd return values and pmufw command
 - Fix R5 tcm init and modes
 
 mmc:
 - Sync Versal NET emmc DT binding
 
 pcie:
 - Add support for ZynqMP PCIe root port
 
 video:
 - Add support for ZynqMP DP
 
 tools:
 - Fix debug message in relocate-rela
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Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.10-rc1

global:
- Use proper U-Boot project name

Fix sparse warnings in zynqmp-clk, zynqmp handoff, board

cmd:
- Cover incorrect 0 length entries

Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command

ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes

mmc:
- Sync Versal NET emmc DT binding

pcie:
- Add support for ZynqMP PCIe root port

video:
- Add support for ZynqMP DP

tools:
- Fix debug message in relocate-rela
2023-06-12 16:42:37 -04:00
Tom Rini
260d4962e0 Merge tag v2023.07-rc4 into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12 14:55:33 -04:00
Michal Simek
1be82afa80 global: Use proper project name U-Boot
Use proper project name in comments, Kconfig, readmes.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Qu Wenruo <wqu@suse.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-12 13:24:31 +02:00
Xavier Drudis Ferran
40359c9440 phy: rockchip-inno-usb2: Implement clock operations for usb2phy clock
This clock doesn't seem needed but appears in a phandle list used by
ehci-generic.c to bulk enable it. The phandle list comes from linux,
where it is needed for suspend/resume to work [1].

My tests give the same results with or without this patch, but Marek
Vasut found it weird to declare an empty clk_ops [2].

So I adapted the code from linux 6.1-rc8 so that it hopefully works
if it ever has some user. For now, without real use, it seems to
at least not give any errors when called.

Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
      [2] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/

Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Christoph Fritz <chf.fritz@googlemail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>

Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
2023-06-07 23:41:47 +02:00
Xavier Drudis Ferran
e81512ac30 phy: rockchip-inno-usb2: Add usb2phy clock provider of 480MHz clock
arch/arm/dts/rk3399.dtsi has a node

  usb_host0_ehci: usb@fe380000 {
       compatible = "generic-ehci";

with clocks:

       clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
                <&u2phy0>;

The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0
has class UCLASS_PHY.

  u2phy0: usb2phy@e450 {
       compatible = "rockchip,rk3399-usb2phy";

Since clk_get_bulk() only looks for devices with UCLASS_CLK,
it fails with -ENODEV and then ehci_usb_probe() aborts.

The consequence is peripherals connected to a USB 2 port (e.g. in a
Rock Pi 4 the white port, nearer the edge) not being detected.
They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig,
because ohci_usb_probe() does not abort when one clk_get_by_index()
fails, but then they work in USB 1 mode.

rk3399.dtsi comes from linux and the  u2phy0 was added[1] to the clock
list in:

    commit b5d1c57299734f5b54035ef2e61706b83041f20c
    Author: William wu <wulf@rock-chips.com>
    Date:   Wed Dec 21 18:41:05 2016 +0800

    arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

    We found that the suspend process was blocked when it run into
    ehci/ohci module due to clk-480m of usb2-phy was disabled.
    [...]

Suspend concerns don't apply to U-Boot, and the problem with U-Boot
failing to probe EHCI doesn't apply to linux, because in linux
rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider
when called by rockchip_usb2phy_probe().

So I can think of a few alternative solutions:

1- Change ehci_usb_probe() to make it more similar to
   ohci_usb_probe(), and survive failure to get one clock. Looks a
   little harder, and I don't know whether it could break something if
   it ignored a clock that was important for something else than
   suspend.

2- Change rk3399.dtsi effectively reverting the linux commit
   b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi
   from linux and seems fragile at the next synchronisation.

3- Change the clock list in rk3399-u-boot.dtsi or somewhere else.
   This survives .dts* sync but may survive "too much" and miss some
   change from linux that we might want.

4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode.
   This would need to be made for all boards using rk3399.  In a
   simple test reading one file from USB storage it gave 769.5 KiB/s
   instead of 20.5 MiB/s with solution 2.

5- Trying to replicate linux and have usb2phy somehow provide a clk,
   or have a separate clock device for usb2phy in addition to the phy
   device.

This patch tries to implement option 5 as Marek Vasut requested in
December 5th.  Options 1 and 3 didn't get through [2][3].

It just registers usb2phy as a clock driver (device_bind_driver()
didn't work but device_bind_driver_to_node() did), without any
specific operations, so that ehci-generic.c finds it and is happy. It
worked in my tests on a Rock Pi 4 B+ (rk3399).

Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
      [2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/
      [3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/

Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Christoph Fritz <chf.fritz@googlemail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>

Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
2023-06-07 23:41:47 +02:00
Ravi Gunasekaran
eab13ca620 phy: ti: phy-j721e-wiz: Add j721s2-wiz-10g module support
Add support for j721s2-wiz-10g device to use clock-names interface
instead of explicitly defining clock nodes within device tree node.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2023-06-01 12:40:16 -04:00
Jon Lin
c5b4a012bc phy: rockchip: naneng-combphy: Support rk3588
Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[kever.yang@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[eugen.hristev@collabora.com: squashed, tidy up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
d49dc884cb phy: rockchip: naneng-combphy: Add support for multiple resets
Some variants of the PHY have more than just one reset.
To cover all cases, request the rests in bulk rather than just
the reset at index 0.

Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Jonas Karlman
e74ac44f79 phy: Keep balance of counts when ops is missing
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 226fce6108 ("phy: Track power-on and init counts in uclass")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-05-17 17:36:18 +08:00
Eugen Hristev
cdf9010f6e phy: rockchip-inno-usb2: add initial support for rk3588 PHY
Add initial support for the rk3588 PHY variant.
The lookup for the host-port reg inside the struct now does a do {} while()
instead of a while() {} in order to allow a first check for reg == 0.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
b59e031a7d phy: remove phy-supply related code
phy-supply is now handled at uclass level. Remove it from the drivers that
implement it at the driver level.

Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
c57e0dcd93 phy: add support for phy-supply
Some phys require a phy-supply property that is a phandle to a regulator
that needs to be enabled for phy operations.
Implement basic supply lookup, enable and disabling, if DM_REGULATOR is
available.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se:
use regulator_set_enable_if_allowed and disable if power_on ops fails]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Johan Jonker
84404d8165 drivers: fix debug string with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
320a1938b6 drivers: use devfdt_get_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
a12a73b664 drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Samuel Holland
df202d996d phy: sun4i-usb: Do not drive VBUS with external VBUS present
It is possible to use host-side USB with externally-provided VBUS. For
example, some USB OTG cables have an extra power input which powers
both the board and the USB peripheral.

To support this setup, skip enabling the VBUS switch/regulator if VBUS
voltage is already present. This behavior matches the Linux PHY driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28 01:30:40 +01:00
Andrew Davis
f392860c2e arm: mach-k3: Remove empty sys_proto.h include
This header file is now empty, remove it.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00