Commit graph

347 commits

Author SHA1 Message Date
Nikita Kiryanov
fcd0524574 mtd: nand: omap: fix ecc ops assignment when changing ecc
If we change to software ecc and then back to hardware ecc, the nand ecc ops
pointers are populated with incorrect function pointers. This is related to the
way nand_scan_tail() handles assigning functions to ecc ops:

If we are switching to software ecc/no ecc, it assigns default functions to the
ecc ops pointers unconditionally, but if we are switching to hardware ecc,
the default hardware ecc functions are assigned to ops pointers only if these
pointers are NULL (so that drivers could set their own functions). In the case
of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are
assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc,
the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite
them with hw ecc functions.
The result: sw ecc functions used to write hw ecc data.

Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that
ops which were not assigned by the driver will get the correct default values
from nand_scan_tail().

Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2013-12-17 17:47:47 -06:00
Nikita Kiryanov
eb237a15bd mtd: nand: omap: fix sw->hw->sw ecc switch
When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values
into the current nand chip's ecc.layout struct. This is done under the
assumption that the struct exists only to store values, so it is OK to overwrite
it, but there is at least one situation where this assumption is incorrect:

When switching to 1 bit hamming code sw ecc, the job of assigning layout data
is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a
pointer to an existing struct prefilled with the appropriate values. This struct
doubles as both data and layout definition, and therefore shouldn't be
overwritten, but on the next switch to hardware ecc, this is exactly what's
going to happen. The next time the user switches to software ecc, they're
going to get a messed up ecc layout.

Prevent this and possible similar bugs by explicitly using the
private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2013-12-17 17:46:53 -06:00
Tom Rini
3ef1eadb44 nand_util.c: Use '%zd' for length in nand_unlock debug print
length is size_t so needs to be '%zd' not '%d' to avoid warnings.

Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-17 17:44:36 -06:00
Nikita Kiryanov
2528460c38 mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.size
Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic
platform" (d016dc42ce) changed the way
software ECC is configured, both during boot, and during ecc switch, in a way
that is not backwards compatible with older systems:

Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring
for software ecc, relying on nand_scan_tail() to select a default for ecc.size
(256), while the new version of omap_gpmc.c assigns ecc.size = pagesize,
which is likely to not be 256.

Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert
to the original behavior.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Pekon Gupta <pekon@ti.com>
2013-12-17 17:41:25 -06:00
Stefan Roese
5d7a49b930 mtd: nand: omap_gpmc: cosmetic: Fix indentation
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: wrap some long lines]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-12-17 17:31:14 -06:00
pekon gupta
69cc97f8db mtd: nand: omap: fix ecc-layout for HAM1 ecc-scheme
As per OMAP3530 TRM referenced below [1]

For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
 - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
 - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device

Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
 *for x8 NAND Device*
 +--------+---------+---------+---------+---------+---------+---------+
 | xxxx   | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
 +--------+---------+---------+---------+---------+---------+---------+

 *for x16 NAND Device*
 +--------+--------+---------+---------+---------+---------+---------+---------+
 | xxxxx  | xxxxx  | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
 +--------+--------+---------+---------+---------+---------+---------+---------+

This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.

[1] OMAP3530: http://www.ti.com/product/omap3530
    TRM: http://www.ti.com/litv/pdf/spruf98x
		Chapter-25: Initialization Sub-topic: Memory Booting
		Section: 25.4.7.4 NAND
		Figure 25-19. ECC Locations in NAND Spare Areas

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Stefan Roese <sr@denx.de>
2013-12-17 17:28:41 -06:00
Masahiro Yamada
392ba5256a drivers/mtd: descend into sub directories only when it is necessary
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:18:44 -05:00
Albert ARIBAUD
f15ea6e1d6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds
2013-12-10 22:23:59 +01:00
Andreas Bießmann
ac45bb1646 at91: nand: switch atmel_nand to generic GPIO API
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-12-09 13:21:45 +01:00
Tom Rini
77fdd6d1eb Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-12-02 08:38:28 -05:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
pekon gupta
3f719069c8 mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme
This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed
CONFIG_xx used for selecting NAND ecc-schemes.
This patch aims at solving following issues.

1) Currently ecc-scheme is tied to SoC platform, which prevents user to select
   other ecc-schemes also supported in hardware. like;
 - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite
   the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with
   software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW).
 - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware
   supports BCH16 ecc-scheme also.

2) Different platforms use different CONFIG_xx to select ecc-schemes, which
   adds confusion for user while migrating platforms.
 - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only
    8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW)
    whereas ELM hardware engine supports other ecc-schemes also like; BCH4,
    and BCH16 (in future).
 - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error
    correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW).
 - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library

Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency
on SoC platform and NAND driver. And user can select ecc-scheme independently
foreach board.
However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still
depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand)

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
pekon gupta
d016dc42ce mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+-----------------------------------+-----------------+-----------------+
|ECC Scheme                         | ECC Calculation | Error Detection |
+-----------------------------------+-----------------+-----------------+
|OMAP_ECC_BCH8_CODE_HW              |GPMC             |ELM H/W engine   |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC             |S/W BCH library  |
+-----------------------------------+-----------------+-----------------+

Current implementation limits the BCH8_CODE_HW only for AM33xx device family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.

This patch
- removes CONFIG_AM33xx
	Thus this driver can be reused by all devices having ELM h/w engine.
- adds omap_select_ecc_scheme()
	A common function to handle ecc-scheme related configurations. This
	can be used both during device-probe and via user-space u-boot commads
	to change ecc-scheme. During device probe ecc-scheme is selected based
	on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8
- enables CONFIG_BCH
	S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW
  	is enabled by CONFIG_BCH.
- enables CONFIG_SYS_NAND_ONFI_DETECTION
	for auto-detection of ONFI compliant NAND devices
- updates following README doc
	doc/README.nand
	board/ti/am335x/README
	doc/README.omap3

Signed-off-by: Pekon Gupta <pekon@ti.com>
[scottwood@freescale.com: fixed unused variable warning]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-11-21 13:33:41 -06:00
pekon gupta
beba5f04f2 mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms
ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include <asm/elm.h>
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
	and include in all board configs using AM33xx SoC platform.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c0dc3dec69 mtd: atmel_nand: use dev_xxx instead of printk
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c55cc573ea mtd: atmel_nand: don't print bit correction message in driver
Since for some MLC nand, bit errors happened too often. Just disable it
to avoid noise

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
16dddef605 mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flash
increase the delay to 75us to support the 8k bytes page nand flash

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Prabhakar Kushwaha
71220f80e7 mtd/ifc: Add support of 8K page size NAND flash
Current IFC driver supports till 4K page size NAND flash.
Add support of 8K NAND flash
  - Program Spare region size in csor_ext
  - Add nand_ecclayout for 4 bit & 8 bit ecc
  - Defines constants
  - Add support of 8K NAND boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Liu Po <po.liu@freescale.com>
2013-11-21 13:33:40 -06:00
Prabhakar Kushwaha
ed5ac34a33 driver/mtd/ifc: Read Status while programming NAND flash
as per controller description,
  "While programming a NAND flash, status read should never skipped.
   Because it may happen that a new command is issued to the NAND Flash,
   even when the device has not yet finished processing the previous request.
   This may result in unpredictable behaviour."

IFC controller never polls for R/B signal after command send. It just return
control to software. This behaviour may not occur with NAND flash access.
because new commands are sent after polling R/B signal. But it may happen
in scenario where GPCM-ASIC and NAND flash device are working simultaneously.

Update the controller driver to take care of this requirement

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-11-13 18:43:39 -06:00
Bo Shen
7604a3f920 MTD: atmel_nand: support for software BCH ECC
Add possible to use software BCH ECC for atmel nand driver

Signed-off-by: Bo Shen <voice.shen@gmail.com>
2013-11-13 17:20:26 -06:00
Albert ARIBAUD
85b8c5c4bf Merge branch 'iu-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	board/compulab/cm_t35/Makefile
	board/corscience/tricorder/Makefile
	board/ppcag/bg0900/Makefile
	drivers/bootcount/Makefile
	include/configs/omap4_common.h
	include/configs/pdnb3.h

Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:

	board/compulab/common/Makefile
	board/udoo/Makefile

include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.

include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.

Note: 'git show' will also list two files just because
they are new:

	include/configs/am335x_igep0033.h
	include/configs/omap3_igep00x0.h
2013-11-09 22:59:47 +01:00
Heiko Schocher
2fff63c2a5 nand, davinci: add special UBL ecc position
enable the RBL/UBL ECC layout through
CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC define

see for more info:
http://processors.wiki.ti.com/index.php/DM365_Nand_ECC_layout

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
2013-11-01 15:30:51 -04:00
Masahiro Yamada
2fc7ef6196 drivers: mtd: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:22:13 -04:00
Tom Rini
9d33fb4a5c nand_util.c: Correct licensing
Prior to SPDX licensing this file was GPL-2.0 with Freescale granting
rights for "or later" for their contributed code.  We incorrectly moved
this file to GPL-2.0+, so correct it to GPL-2.0.  In addition we cannot
easily denote in the file where or what code is "or later", so just set
that aside for now and the file as a whole is GPL-2.0 regardless.

Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-31 09:24:00 -04:00
Valentin Longchamp
2f9e559a6c mtd/fsl_elbc: take NAND_ECC_SOFT_BCH config option into account
NAND_ECC_SOFT was the only option available while the SOFT_BCH option
may also be used.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-10-24 09:36:05 -07:00
Wolfgang Denk
d4c8aa9cb4 Coding Style cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
93e1459641 Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14 16:06:54 -04:00
Paul Burton
40462e541d mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEAN
Linux modified the MTD driver interface in commit edbc4540 (with the
same name as this commit). The effect is that calls to mtd_read will
not return -EUCLEAN if the number of ECC-corrected bit errors is below
a certain threshold, which defaults to the strength of the ECC. This
allows -EUCLEAN to stop indicating "some bits were corrected" and begin
indicating "a large number of bits were corrected, the data held in
this region of flash may be lost soon". UBI makes use of this and when
-EUCLEAN is returned from mtd_read it will move data to another block
of flash. Without adopting this interface change UBI on U-boot attempts
to move data between blocks every time a single bit is corrected using
the ECC, which is a very common occurance on some devices.

For some devices where bit errors are common enough, UBI can get stuck
constantly moving data around because each block it attempts to use has
a single bit error. This condition is hit when wear_leveling_worker
attempts to move data from one PEB to another in response to an
-EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
called to perform the data copy, and after the data is written it is
read back to check its validity. If that read returns UBI_IO_BITFLIPS
(in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
wear_leveling worker, which then proceeds to schedule the destination
PEB for erasure. This leads to erase_worker running on the PEB, and
following a successful erase wear_leveling_worker is called which
begins this whole cycle all over again. The end result is that (without
UBI debug output enabled) the boot appears to simply hang whilst in
reality U-boot busily works away at destroying a block of the NAND
flash. Debug output from this situation:

  UBI DBG: ensure_wear_leveling: schedule scrubbing
  UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
  UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
  UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
  UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
  UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
  UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
  UBI: fixable bit-flip detected at PEB 1027
  UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
  UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
  UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
  UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
  UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
  UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
  UBI: fixable bit-flip detected at PEB 4083
  UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
  UBI DBG: erase_worker: erase PEB 4083 EC 55
  UBI DBG: sync_erase: erase PEB 4083, old EC 55
  UBI DBG: do_sync_erase: erase PEB 4083
  UBI DBG: sync_erase: erased PEB 4083, new EC 56
  UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
  UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
  UBI DBG: ensure_wear_leveling: schedule scrubbing
  UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
  ...

This patch adopts the interface change as in Linux commit edbc4540 in
order to avoid such situations. Given that none of the drivers under
drivers/mtd return -EUCLEAN, this should only affect those using
software ECC. I have tested that it works on a board which is
currently out of tree, but which I hope to be able to begin
upstreaming soon.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
2013-10-09 12:52:04 -05:00
Elie De Brauwer
a8f2d0e675 mxs_nand: Fix ECC strength for NAND flash with OOB size of 224
On a board with an i.mx28 and a Micron MT29F4G08ABAEAH4, Linux says:

NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron MT29F4G08ABAEAH4),
512MiB, page size: 4096, OOB size: 224) the ECC strength is 16.

root@(none):/sys/devices/virtual/mtd/mtd0# for i in ecc_strength oobsize subpagesize; do echo $i = `cat $i`; done
ecc_strength = 16
oobsize = 224
subpagesize = 4096

The ECC strength was not properly discovered by U-Boot causing the data
written by Linux to return an -74 (EBADMSG) when read from U-Boot. This
patch fixes mxs_nand_get_ecc_strength() to function in case of a NAND
flash with page_data_size = 4096 and page_oob_size= 224.

Signed-off-by: Elie De Brauwer <eliedebrauwer@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-09-11 09:33:36 +02:00
Wu, Josh
1bd3e2a823 mtd: atmel_nand: pmecc: fix bug fail to correct bit error in 1024-bytes sector
The PMECC use BCH algorithm to correct error. In BCH algorithm, the
primitive polynomial value is GF(2^13) for 512-bytes sector size. And it is
GF(2^14) for 1024-bytes sector size.

This patch will choose correct degree of the remainders (13 or 14) for
different sector size.
Tested in AT91SAM9X5-EK with MLC nand flash.

More detail can be refered to section 5.4.1 of:
  AT91SAM ARM-based Embedded MPU Application Note
  <http://www.atmel.com/Images/doc11127.pdf>

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-09-04 17:07:21 +02:00
Albert ARIBAUD
4eef93da26 Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-09-04 11:50:25 +02:00
Masahiro Yamada
47b6dad319 nand_util: delete a useless variable
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-08-22 17:25:03 -05:00
Wu, Josh
a07d229497 ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirement
1. if CONFIG_SYS_NAND_ONFI_DETECTION is defined, driver will check NAND flash's
   ecc minimum requirement in ONFI parameter.

  a) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are defined. then use it.
     Driver will display a WARNING if the values are different from ONFI
     parameters.

  b) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are not defined, then use
      the value from ONFI parameters.
      * If ONFI ECC parameters are in ONFI extended parameter page, since we
        are not support it, so assume the minimum ecc requirement is 2 bits
        in 512 bytes.
      * For non-ONFI support nand flash, also assume the minimum ecc
        requirement is 2 bits in 512 bytes.

2. if CONFIG_SYS_NAND_ONFI_DETECTION is not defined, just use CONFIG_PMECC_CAP
   and CONFIG_PMECC_SECTOR_SIZE.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:52 +02:00
Wu, Josh
ddd85974b1 mtd: atmel_nand: alloc memory instead of use static array for pmecc data
In this way, the pmecc corraction capbility can change in run time.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:44 +02:00
Wu, Josh
b2d96dc28f ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size
Define the galois index table offset in chip head file. So user do not need
to set by himself. Driver will set it correctly according to sector_size.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
[rebased on master]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:16 +02:00
Ying Zhang
5d97fe2a04 powerpc: p1022ds: add TPL for p1022ds nand boot
TPL is introduced in the patch "NAND: TPL : introduce the TPL
based on the SPL", here enable TPL for p1022ds nand boot.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Marek Vasut
1c90369437 mtd: mxc_nand: Fix crash after MTD resync
The driver triggered a BUG() in nand_base.c:3214/nand_scan_tail()
because the ecc.strength was not set in NAND_ECC_HW_SYNDROME ECC
mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-07-12 16:12:33 -05:00
Tom Rini
5a34d9bf31 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2013-07-01 10:11:56 -04:00
Mike Dunn
8b6b51a617 mtd/nand: docg4: fix compiler warnings
Newer gcc versions warn about unused variables.  This patch corrects a few of
those warnings that popped up in a build for the palmtreo680 board.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-26 16:19:58 -05:00
Heiko Schocher
a67cc37e69 dfu, nand: before write a buffer to nand, erase the nand sectors
before writing the received buffer to nand, erase the nand
sectors. If not doing this, nand write fails. See for
more info here:

http://lists.denx.de/pipermail/u-boot/2013-June/156361.html

Using the nand erase option "spread", maybe overwrite
blocks on, for example another mtd partition, if the
erasing range contains bad blocks.
So a limit option is added to nand_erase_opts()

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-06-24 18:17:23 -05:00
Prabhakar Kushwaha
3a88179d03 powerpc/mpc85xx: new SPL support for IFC NAND
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds

common/Makefile: Avoid compiling unnecssary files

fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:08:58 -05:00
Daniel Schwierzeck
eab2276458 mtd: nand: fix initialization of BBT options
commit dfe64e2c89
Author: Sergey Lapin <slapin@ossfans.org>
Date:   Mon Jan 14 03:46:50 2013 +0000

    mtd: resync with Linux-3.7.1

changed the initialization of BBT options. Fix drivers
jz4740 and s3c2410 which have not been updated yet and
cause compile errors.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-06-18 15:35:16 -05:00
Mike Dunn
211bf20c35 mtd: nand/docg4: fix driver after Linux resync
Commit dfe64e2c89:

    mtd: resync with Linux-3.7.1

broke the docg4 driver.  Specifically:
 - some of the prototypes of the ecc methods changed
 - the NAND_NO_AUTOINCR flag was removed
 - the ecc.strength element was added.

This patch fixes these.  Tested on the docg4 on my palmtre680 board.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-17 17:26:12 -05:00
Sergey Lapin
4bfd0002b6 bug, nand, am33xx: nand->ecc.strength not set in board_nand_init()
commit dfe64e2c89
Author: Sergey Lapin <slapin@ossfans.org>
Date:   Mon Jan 14 03:46:50 2013 +0000

    mtd: resync with Linux-3.7.1

Introduced runtime bug:

U-Boot 2013.04-00499-g46567df-dirty (Jun 04 2013 - 08:17:08)

I2C:   ready
DRAM:  512 MiB
WARNING: Caches not enabled
NAND:  BUG: failure at nand_base.c:3214/nand_scan_tail()!
BUG!
resetting ...

on boards using drivers/mtd/nand/omap_gpmc.c as in board_nand_init()
nand->ecc.strength is not set. Fix this!

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2013-06-04 11:50:04 -05:00
Tom Rini
d6639d10db Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2013-05-31 18:28:47 -04:00
Sergey Lapin
dfe64e2c89 mtd: resync with Linux-3.7.1
This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:

- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.

- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).

To produce this update I used tag v3.7.1 of linux-stable repository.

The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.

Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-05-31 17:12:03 -05:00
Prabhakar Kushwaha
a1b81ab26f nand/fsl_ifc: Convert to self-init
Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-05-22 16:53:42 -05:00
htbegin
453db36863 mtd: nand: use ssize_t instead of size_t to prevent infinite loop
When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop
will loop forever.
After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l
will still be 0 as expected.

Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Scott Wood <scottwood@freescale.com>
2013-05-22 16:50:59 -05:00
htbegin
070fd8e529 mtd: nand: fix the partial page write condition
When writelen is mtd->writesize - 1, it is still a partial page write

Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
2013-05-22 16:43:47 -05:00