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As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de> |
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.. | ||
am335x_spl_bch.c | ||
atmel_nand.c | ||
atmel_nand_ecc.h | ||
bfin_nand.c | ||
davinci_nand.c | ||
diskonchip.c | ||
docg4.c | ||
docg4_spl.c | ||
fsl_elbc_nand.c | ||
fsl_elbc_spl.c | ||
fsl_ifc_nand.c | ||
fsl_ifc_spl.c | ||
fsl_upm.c | ||
fsmc_nand.c | ||
jz4740_nand.c | ||
kb9202_nand.c | ||
kirkwood_nand.c | ||
kmeter1_nand.c | ||
Makefile | ||
mpc5121_nfc.c | ||
mxc_nand.c | ||
mxc_nand.h | ||
mxc_nand_spl.c | ||
mxs_nand.c | ||
nand.c | ||
nand_base.c | ||
nand_bbt.c | ||
nand_bch.c | ||
nand_ecc.c | ||
nand_ids.c | ||
nand_plat.c | ||
nand_spl_load.c | ||
nand_spl_simple.c | ||
nand_util.c | ||
ndfc.c | ||
nomadik.c | ||
omap_elm.c | ||
omap_gpmc.c | ||
s3c2410_nand.c | ||
tegra_nand.c | ||
tegra_nand.h |