The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.
SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.
U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).
It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.
There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.
With this patch, link boots to a prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.
Signed-off-by: Simon Glass <sjg@chromium.org>
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some functions are missing prototypes. Fix those that are specific to x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add code to jump to a 64-bit Linux kernel. We need to set up a flat page
table structure, a new GDT and then go through a few hoops in the right
order.
Signed-off-by: Simon Glass <sjg@chromium.org>
To permit information to be passed from the early U-Boot code to
board_init_f() we cannot zero the global_data in board_init_f(). Instead
zero it in the start-up code.
Signed-off-by: Simon Glass <sjg@chromium.org>
When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to
pull them into the final linking process.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Until now building the x86 arch boards required 32-bit toolchain. As
many x86_64 toolchains come with 32-bit support (multilib) that's a
good idea to enable build with such toolchains.
The change required was to specify the usage of 32-bit explicitly to
the compiler and the linker (-m32 and -m elf_i386 flags) and locate
the right libgcc path.
Signed-off-by: Vasili Galka <vvv444@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
U-Boot has supported two kinds of asm-offsets.h.
One is generic for all architectures and its source is located at
./lib/asm-offsets.c.
The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.
Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.
It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.
This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.
By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
panic_puts() can be called in early boot to display a message. It might
help with early debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we don't have real-mode code now, we can remove this chunk of the link
script.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
The intention of the memory init code is that it should work the same with
CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init()
is called prior to relocation with generic board (matching other archs)
and after relocation without generic board.
Adjust the init sequence so that dram_init() is not called in the generic
board case, which seems like the easiest fix for now. Also ensure that
relocation addresses are still calculated.
Signed-off-by: Simon Glass <sjg@chromium.org>
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end. We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.
Conflicts:
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/u-boot.lds
arch/arm/lib/Makefile
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/dvlhost/u-boot.lds
board/freescale/mx31ads/u-boot.lds
doc/README.scrapyard
include/configs/tegra-common.h
Build tested for all of ARM and run-time tested on am335x_evm.
Signed-off-by: Tom Rini <trini@ti.com>
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.
Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.
Conflicts:
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/vpac270/u-boot-spl.lds
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
At present BSS data is including in the image, which wastes binary space.
Remove it by rearranging the sections so that BSS is last.
Signed-off-by: Simon Glass <sjg@chromium.org>
With this symbol we can easy append something (e.g. an FDT) to the U-Boot
binary and access it from within U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to be able to access the timer before U-Boot has relocated
so that we can fully support bootstage.
Add new global_data members to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
The memory layout calculations are done in calculate_relocation_address(),
and coreboot has its own version of this function. But in fact all we
really need is to set the top of usable RAM, and then the base version
will work as is.
So instead of allowing the whole calculate_relocation_address() function
to be replaced, create board_get_usable_ram_top() which can be used by
a board to specify the top of the area where U-Boot relocations to.
Signed-off-by: Simon Glass <sjg@chromium.org>
Invert the polarity of this option to simplify the Makefile logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gabe Black <gabeblack@chromium.org>
This x86 CPU variant is no longer required as the boards that use it have
been removed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add arch/x86/cpu/cpu.c changes after Graeme's comments]
Signed-off-by: Tom Rini <trini@ti.com>
We currently assume that the global data pointer is at the start of
struct global_data. We want to remove this restriction, and it is
easiest to do this in C.
Remove the asm code and add equivalent code in C.
This idea was proposed by Graeme Russ here:
http://patchwork.ozlabs.org/patch/199741/
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Apply Graeme Russ' comments
http://patchwork.ozlabs.org/patch/206305/ here, re-order]
Signed-off-by: Tom Rini <trini@ti.com>
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.
monitor_flash_len is unused, drop it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
... because that information is already "encoded" in the directory name.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.
This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.
Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.
Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move. Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
These were removed, but actually are useful.
Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.
We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.
Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
U-boot is unable to actually use that memory and it can
cause problems with relocation if it tries to.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.
This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.
Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.
The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.
Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The microsecond timer is not currently implemented, but add a dummy
implementation for now.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.
On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.
This was tested as follows:
Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.
It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
When running from coreboot we don't want this code.
This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
So it can be used as a type in struct global_data and remove an ugly typecast
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Building the eNET_SRAM board fails for me:
sc520_timer.c: In function 'sc520_udelay':
sc520_timer.c:81:7: error: variable 'temp' set but not used
[-Werror=unused-but-set-variable]
cc1: all warnings being treated as errors
make[1]: *** [sc520_timer.o] Error 1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Use the base address of the 'F' segment as a pointer to the global data
structure. By adding the linear address (i.e. the 'D' segment address) as
the first word of the global data structure, the address of the global data
relative to the 'D' segment can be found simply, for example, by:
fs movl 0, %eax
This makes the gd 'pointer' writable prior to relocation (by reloading the
Global Desctriptor Table) which brings x86 into line with all other arches
NOTE: Writing to the gd 'pointer' is expensive (but we only do it
twice) but using it to access global data members (read and write) is
still fairly cheap
--
Changes for v2:
- Rebased against changes made to patch #3
- Removed extra indent
- Tweaked commit message
Move the relocation offset calculation out of assembler and into C. This
also paves the way for the upcoming init sequence simplification by adding
the board_init_f_r flash to RAM transitional function
--
Changes for v2:
- Added commit message
- Minor adjustment to new stack address comment
The inline assembler is ugly and uses hard coded magic numbers. Make it more
elegant to allow cleaner implementation of future GDT related patches. The
compiler seems smart enough to generate the same code anyway
--
Changes for v2:
- Rebased against revised patch #3
- Use GDT size define instead of magic number
- Added commit message
Also approximate the size of RAM using the largest RAM address available
in the tables. There may be areas which are marked as reserved which are
actually at the end of RAM.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
This change also forces the lib_sysinfo structure to be in the .data
section. Otherwise it ends up in the .bss section. U-boot assumes that it
doesn't need to copy it over during relocation, and instead fills that
whole section with zeroes. If we really were booting from ROM that would be
appropriate, but we need some information from the coreboot tables (memory
size) before then and have to fill that structure before relocation. We
skirt u-boot's assumption by putting this in .data where it assumes there
is still read only but non-zero data.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
By adding a multiboot header, U-Boot can be loaded by GRUB2. Using GRUB2 to
bootstrap U-Boot is useful for using an existing BIOS to get an initial
U-Boot port up and running before implementing the low-level reset vector
code, SDRAM init, etc. and overwriting the BIOS
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 files to UTF-8.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address
Signed-off-by: Mike Williams <mike@mikebwilliams.com>
Partial linking allows weak functions to be overridden in files containing
only one function. Moving the sc520 override of reset_cpu gets rid of an
ugly #ifdef
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
