Simon Glass 2b6051541b x86: ivybridge: Add early LPC init so that serial works ... The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>		2014-11-21 07:34:12 +01:00
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coreboot	x86: Refactor PCI to permit alternate init	2014-11-21 07:34:11 +01:00
ivybridge	x86: ivybridge: Add early LPC init so that serial works	2014-11-21 07:34:12 +01:00
call64.S	x86: Add support for starting 64-bit kernel	2014-10-28 20:43:47 -06:00
config.mk	kconfig: delete redundant CONFIG_${ARCH} definition	2014-07-30 14:42:02 -04:00
cpu.c	x86: Replace fill_processor_name() with cpu_get_name()	2014-11-21 07:24:12 +01:00
interrupts.c	x86: Fix up some missing prototypes	2014-11-21 07:24:09 +01:00
Makefile	x86: Refactor PCI to permit alternate init	2014-11-21 07:34:11 +01:00
pci.c	x86: pci: Allow configuration before relocation	2014-11-21 07:34:12 +01:00
resetvec.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
start.S	x86: Emit post codes in startup code for Chromebooks	2014-11-21 07:34:11 +01:00
start16.S	x86: Save the BIST value on reset	2014-11-21 07:24:10 +01:00
u-boot.lds	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00