According to EHCI spec, software needs to do handshake with HC for
safely removing QH from async list. This handshake is implemented by
setting IAAD (Interrupt on Async Advance Doorbell) bit in USB_USBCMD
register and poll the IAA (Interrupt on Async Advance bit) in the
USB_USBSTS to ensure the HC has released all on-chip state that may
potentially reference one of the data structures just removed.
Current codes only check active status of the last QTD, but this can't
ensure the QH is released from HC. We can meet unrecoverable
"EHCI timed out on TD" errors when running UEFI SCT tests on USB disk.
The USB_ASYNCLISTADDR register is changed to a invalid address when the
issue happens. It is fixed after adding the IAA handshake.
Steps to reproduce the issue:
1. Build the UEFI SCT from https://github.com/tianocore/edk2-test
2. Build the EDK2 UEFI Shell from https://github.com/tianocore/edk2
3. Copy SCT files and Shell.efi to USB disk FAT partition
4. Load the Shell.efi from USB FAT, and run bootefi to execute it
5. After booting into Shell, enter the SCT directory and run "sct -a"
to execute all tests.
6. Tests run about 1 hour and stop with many EHCI timeout errors like
EHCI timed out on TD - token=0x801f8c80
Signed-off-by: Ye Li <ye.li@nxp.com>
Until now, the Octeontx MMC driver did only support the ARM Octeon
TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform
to this driver. Here a short summary of the changes:
- Enable driver compilation for MIPS Octeon, including the MMC related
header file
- Reorder header inclusion
- Switch to using the clk framework to get the input clock
- Remove some functions for MIPS Octeon, as some registers don't
exist here
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Sometimes no traffic was getting out on the ports, the root cause was
a wrong configuration of the Serdes6G, which is used on jr2 pcb111.
This patch fixes this issue by applying the correct configuration.
Fixes: 5e1d417bec ("net: Add MSCC Jaguar2 network driver.")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Make sure to reset the switch core at probe time.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use psci driver exported functions for reset/poweroff, instead of
invoking directly invoke_psci_fn.
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Adds support for:
* PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API
that allows discovering whether a specific PSCI function is implemented
and its features.
* SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing
SYSTEM_RESET. It provides support for vendor-specific resets, providing
reset_type as an additional param.
For additional details visit [1].
Implementations of some functions were borrowed from Linux PSCI driver
code [2].
[1] https://developer.arm.com/documentation/den0022/latest/
[2] drivers/firmware/psci/psci.c
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
To squash that nasty warning message and make better use of the newly
gained OF_CONTROL feature, let's convert the calxedagmac driver to the
"new" driver model.
The conversion is pretty straight forward, mostly just adjusting the
use of the involved data structures.
The only actual change is the required split of the receive routine into
a receive and free_pkt part.
Also this allows us to get rid of the hardcoded platform information and
explicit init calls.
This also uses the opportunity to wrap the code decoding the MMIO
register base address, to make it safe for using PHYS_64BIT later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The fdt node offset is apparently not set properly when probed
causing no MDIO busses to be found. Fix this by obtaining the
offset.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
After check for maximum between max id and available ports, also check
if available port count is less than max id and update.
In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to
the number of ports found otherwise the following occurs on a scan:
GW6404-B> scsi scan
scanning bus for devices...
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc
apst
Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233
Type: Hard Disk
Capacity: 61057.3 MB = 59.6 GB (125045424 x 512)
"Synchronous Abort" handler, esr 0x96000006
elr: 000000000052f824 lr : 000000000052fa10 (reloc)
elr: 000000007fee9824 lr : 000000007fee9a10
x0 : 0000000000000001 x1 : 0000000000000001
x2 : 000000007bea3528 x3 : 000000007bea3580
x4 : 0000000000000200 x5 : 0000000000000000
x6 : 0000000000000002 x7 : 000000007bea3540
x8 : 00000000fffffff8 x9 : 0000000000000008
x10: 00000000000186a0 x11: 000000000000000d
x12: 0000000000000006 x13: 000000000001869f
x14: 0000000000000007 x15: 00000000ffffffff
x16: 000000007ff439a5 x17: 000000007ff5730c
x18: 000000007bea9de0 x19: 000000007ff7a580
x20: 000000007bec79f8 x21: 0000000000000000
x22: 000000007bea3580 x23: 0000000000000000
x24: 0000000000000000 x25: 000000007bec7a00
x26: 00000000ffffffc0 x27: 000000007bec79d0
x28: 000000007beb51c0 x29: 000000007bea3480
Code: 91246800 940130c2 12800000 1400004f (b9402ae0)
Resetting CPU ...
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Revert a change that occured between the Marvell SDK-10.1.1.0
and SDK-10.3.1.1 which broke QSMII phy support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Fixes IDE issues found on the Malta board under Qemu:
1) DMA implied commands were sent to the controller in stead of the PIO
variants. The rest of the code is DMA free and written for PIO operation.
2) direct pointer access was used to read and write the registers instead
of the inb/inw/outb/outw functions/macros. Registers don't have to be
memory mapped and ATA_CURR_BASE() does not have to return an offset from
address zero.
3) Endian isues in ide_ident() and reading/writing data in general. Names
were corrupted and sizes misreported.
Tested malta_defconfig and maltael_defconfig to work again in Qemu.
Signed-off-by: Reinoud Zandijk <reinoud@NetBSD.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ
selectable for all platforms.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for sama7g5 pinctrl variant, with 5 banks with a degraded
8 line only 5th bank.
Based on Linux Kernel implementation.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This is a patchset which makes away with the .bind() controller indexing
workaround which was broken since before v2021.04, and then adds PHY
support and MX8M support on top of that. Better add it into the release
early to get as much testing as possible done, because this really does
a lot of changes to the ehci-mx6 driver.
The iMX8M uses nop PHY, select PHY and NOP_PHY automatically.
Otherwise, the DM capable driver is now perfectly compatible.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Fix cast from pointer to integer of different size by casting the
pointer to uintptr_t instead of uint32_t, the former has correct
size on both 32bit and 64bit architectures.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Add new compatible string, used by some more up-to-date DTs.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
There is now multiple copies of CONFIG_MXC_USB_PORTSC in configs set to
PORT_PTS_UTMI | PORT_PTS_PTW, which is in fact the default register value
for MX6, MX7 and MX7ULP. Define the default value of CONFIG_MXC_USB_PORTSC
in the driver and use it in case CONFIG_MXC_USB_PORTSC is not defined in
config, to reduce the duplication.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
In case PHY support is enabled, use the generic EHCI PHY support
to start and stop the PHY.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
In case the platform uses DM, determine port number, which is
used as offset in USBMISC registers, from PHY node DT aliases,
just like Linux does.
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Instead of passing ad-hoc sequence number to usb_oc_config(), pass in
the USB MISC address itself. The USB MISC address comes from DT in DM
case, and from the old method using controller index in non-DM case.
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP
addresses instead of ad-hoc sequence numbers. This is only applicable
on legacy systems which do not implement proper PHY support. Once PHY
support is available, parts of this can be removed altogether and moved
to the PHY driver, similar to Linux phy-mxs-usb.c .
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Instead of passing ad-hoc index to USB PHY handling functions and then
try and figure out the PHY address, pass in the PHY address itself. For
DM case, this address comes easily from DT. For non-DM case, the previous
method is still present, however the non-DM case will soon be removed.
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
In order to pass component addresses around easily instead of passing
ad-hoc sequence numbers, it is necessary to split ehci_mx6_common_init().
Make it so and call the separate functions instead.
Since board_ehci_hcd_init() makes no sense in DM case, do not call it
in DM case.
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
In case DM and OF controler is enabled, but PHY support is disabled,
parse USB PHY and MISC component addresses from DT manually. Those
component addresses will be used in subsequent patches to access the
ANATOP, PHY and MISC registers matching the controller and thus get
rid of the ad-hoc controller sequence number mapping.
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Merge USBNC register layout structure into a single one, instead of
having three separate structures and a lot of ifdeffery. No functional
change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Add support for using DM clock framework to enable and disable all the
necessary clock for the USB controller.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
The driver turns on Vbus regulator in probe, but fails to turn it back
off in case of probe failure. Add the missing code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
The driver is compatible with iMX8MN, add missing compatible string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
The driver is compatible with iMX8MM, add missing compatible string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver is
compatible with USB no-op PHY, so add the compatible string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Currently sunxi Makefile manually specifies full path to dw-hdmi common
code. However, that is not needed because it can be selected in Kconfig
instead.
Select proper symbol in Kconfig and drop path from Makefile.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The XHCI controller has its own clock and reset. Add them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is
used, among other things, by the XHCI controller in the H6. To be able
to call clk_get_bulk() on the XHCI controller, some device needs to
provide all referenced clocks.
Since LOSC is a fixed-rate always-on clock, implementation is trivial.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
update ls1028aqds networking protocol, config in ls1021atwr, env in ls1012a
Add seli3 board support, booke watchdog, update eTSEC support in ppc-qemu
Add DM_SERIAL and lpuart in sl28, add DM_ETH support for some of powerpc platforms
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This adds a test case to verify reading <ranges> of a simple-bus is
working as expected.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
At present we decode simple bus <ranges> using the following assumption:
- parent #address-cells 1
- child #address-cells 1
- child #size-cells 1
However this might not always be the case.
Update to use fdt_addr_t and fdt_size_t in 'struct simple_bus_plat', and
use fdt_read_ranges() to correctly decode it according to the actual
parent and child #address-cells / #size-cells under a Kconfig option
CONFIG_SIMPLE_BUS_CORRECT_RANGE which can be turned on for any board
that needs it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
At present the tsec driver uses a non-standard DT bindings to get
its <reg> base / size. The upstream Linux kernel seems to require
the <reg> base / size to be put under a subnode of the eTSEC node
with a name prefix "queue-group". This is not documented in the
kernel DT bindings, but it looks every dtsi file that contains the
eTSEC node was written like this.
This commit updates the tsec driver to handle this case.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
dev_remap_addr() eventually calls dev_read_addr_index(), while
pdata->iobase holds the return value of dev_read_addr() that calls
dev_read_addr_index() too. Such duplication can be avoided by using
map_physmem() directly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The DSA sandbox driver is used for unit testing the DSA class code.
It implements a simple 2 port switch plus 1 CPU port, and uses a
very simple tag to identify the ports.
The DSA sandbox device is connected via CPU port to a regular Ethernet
sandbox device, called 'dsa-test-eth, managed by the existing eth
sandbox driver. The 'dsa-test-eth' is not intended for testing the
eth class code however, but it is used to emulate traffic through the
'lan0' and 'lan1' front pannel switch ports. To achieve this the dsa
sandbox driver registers a tx handler for the 'dsa-test-eth' device.
The switch ports, labeled as 'lan0' and 'lan1', are also registered
as eth devices by the dsa class code this time. So pinging through
these switch ports is as easy as:
=> setenv ethact lan0
=> ping 1.2.3.5
Unit tests for the dsa class code were also added. The 'dsa_probe'
test exercises most API functions from dsa.h. The 'dsa' unit test
simply exercises ARP/ICMP traffic through the two switch ports,
including tag injection and extraction, with the help of the dsa
sandbox driver.
I took care to minimize the impact on the existing eth unit tests,
though some adjustments needed to be made with the addition of
extra eth interfaces used by the dsa unit tests. The additional eth
interfaces also require MAC addresses, these have been added to the
sandbox default environment.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Message-Id: <20210216224804.3355044-5-olteanv@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Now that the fixed phy driver has been fully adapted to OF APIs,
and dm_eth_phy_connect() already can handle the fixed phy, call
dm_eth_phy_connect() directly in the DM tsec driver.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210216224804.3355044-4-olteanv@gmail.com>
[bmeng: split from "net: mdio: teach dm_eth_phy_connect to connect to fixed PHY"]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Update fixedphy_probe() to support the old DT binding.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The printf statement doesn't end with a newline. Add it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The PHY driver ops should be made static.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Simplify the logic of phy_connect_fixed() by using the new API
ofnode_phy_is_fixed_link(), which brings additional bonus of
supporting the old DT bindings.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
At present phy_connect_gmii2rgmii() is implemented using a DM API
dev_of_offset() hence it cannot support a non-DM configuration.
Remove the non-DM version prototype of phy_connect_gmii2rgmii()
and make the driver depend on CONFIG_DM_ETH.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Following the same updates that were done to the fixed phy driver,
use ofnode_ APIs instead of fdt_ APIs so that the Xilinx PHY driver
can support live DT.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
In drivers/net/phy/Kconfig, CONFIG_PHY_FIXED already depends on
CONFIG_DM_ETH, so the function prototype definition when
CONFIG_DM_ETH=n does nothing, so it can be dropped. It is also
never reachable, since the whole function is already under #ifdef
CONFIG_PHY_FIXED (which again, as I said, depends on CONFIG_DM_ETH=y).
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210216224804.3355044-3-olteanv@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
On systems that use CONFIG_OF_LIVE, the "ofnode" type is defined
as const struct device_node *np, while on the flat DT systems it
is defined as a long of_offset into gd->fdt_blob.
It is desirable that the fixed PHY driver uses the higher-level
ofnode abstraction instead of parsing gd->fdt_blob directly,
because that enables it to work on live OF systems.
The fixed PHY driver has used a nasty hack since its introduction in
commit db40c1aa1c ("drivers/net/phy: add fixed-phy /
fixed-link support"),
which is to pass the long gd->fdt_blob offset inside int phydev->addr
(a value that normally holds the MDIO bus address at which the PHY
responds). Even ignoring the fact that the types were already
mismatched leading to a potential truncation (flat OF offset was
supposed to be a long and not an int), we really cannot extend this
hack any longer, because there's no way an int will hold the other
representation of ofnode, the struct device_node *np.
So we unfortunately need to do the right thing, which is to use the
framework introduced by Grygorii Strashko in
commit eef0b8a930 ("net: phy: add ofnode node to struct phy_device").
This will populate phydev->node for the fixed PHY.
Note that phydev->node will not be valid in the probe function, since
that is called synchronously from phy_device_create and we really have
no way of passing the ofnode directly through the phy_device_create API.
So we do what other drivers do too: we move the OF parsing logic from
the .probe to the .config method of the PHY driver. The new function
will be called at phy_config() time.
I do believe I've converted all the possible call paths for creating
a PHY with PHY_FIXED_ID, so there is really no reason to maintain
compatibility with the old logic of retrieving a flat OF tree offset
from phydev->addr. We just pass 0 to phydev->addr now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210216224804.3355044-2-olteanv@gmail.com>
[bmeng: keep fixedphy_probe(); update mdio-uclass.c to handle fixed phy]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Introduce a helper API ofnode_phy_is_fixed_link() to detect whether
the ethernet controller connects to a fixed-link pseudo-PHY device.
Note there are two ways to describe a fixed PHY attached to an
Ethernet device:
- the new DT binding, where 'fixed-link' is a sub-node of the
Ethernet device
- the old DT binding, where 'fixed-link' is a property with 5
cells encoding various information about the fixed PHY
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add a driver for the PowerPC Book E watchdog driver that is present on a
number of Freescale/NXP SoCs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add support for the DW PCIe controller found in the Amlogic Meson AXG and
G12 (G12A, G12B, SM1) SoCs.
This uses the common DW PCIe helpers introducted previously.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in the
Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated.
This introduce a "common" DW PCIe helpers file with common code merged from the
dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson.
The following changes will switch the dw_ti and dw_rockchip to use these helpers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Green Wan <green.wan@sifive.com>
[bmeng: remove the blank line at EOF of drivers/pci/pcie_dw_common.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Call the translation function on the ofnode_read_resource result only
when the livetree is not activated.
Today of_address_to_resource() calls ofnode_read_resource() for livetree
support and fdt_get_resource() when livetree is not supported.
The fdt_get_resource() doesn't do the address translation
so when it is required when livetree is activated but this address
translation is already done by ofnode_read_resource().
Fixes: 240720e905 ("firmware: scmi: mailbox/smt agent device")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This is the only driver that uses this function. Update it to use the
alternative which is dm_gpio_clrset_flags().
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Harm Berntsen <harm.berntsen@nedap.com>
Add MMIO driver for QFW.
Note that there is no consumer as of this patch.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A sandbox driver and test are added for the qfw uclass, and a test in
QEMU added for qfw functionality to confirm it doesn't break in real
world use.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We move qfw into its own uclass and split the PIO functions into a
specific driver for that uclass. The PIO driver is selected in the
qemu-x86 board config (this covers x86 and x86_64).
include/qfw.h is cleaned up and documentation added.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Align the MMU area for SCMI shared buffer on section size;
use the ALIGN macro in mmu_set_region_dcache_behaviour call.
Since commit d877f8fd0f ("arm: provide a function for boards init
code to modify MMU virtual-physical map") the parameter of
mmu_set_region_dcache_behaviour need to be MMU_SECTION_SIZE
aligned.
Fixes: 240720e905 ("firmware: scmi: mailbox/smt agent device")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
This fixes several uses of strn(cpy|cat) which did not terminate their
destinations properly.
Fixes de1728ce4c ("fastboot: Allow u-boot-style partitions")
Reported-by: Coverity Scan
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This introduces strlcat, which provides a safer interface than strncat. It
never copies more than its size bytes, including the terminating nul. In
addition, it never reads past dest[size - 1], even if dest is not
nul-terminated.
This also removes the stub for dwc3 now that we have a proper
implementation.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Right now the error messages when optee has a version mismatch or shared
memory is not configured are done with a debug().
That's not very convenient since you have to enable debugging to figure
out what's going on, although this is an actual error.
So let's switch the debug() -> dev_err() and report those explicitly.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support for rtc3028 rtc from microcrystal.
based on linux dirver:
commit a38fd8748464: ("Linux 5.12-rc2")
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Fix inline comments and empty line in scmi driver and test files.
Remove test on IS_ENABLED(CONFIG_*_SCMI) in test/dm/scmi.c since these
configuration are expected enabled when CONFIG_FIRMWARE_SCMI is enabled
in sandbox configuration.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Implement sandbox regulator devices for SCMI voltage domains
and test them in DM scmi tests.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Implement voltage regulators interfaced by the SCMI voltage domain
protocol. The DT bindings are defined in the Linux kernel since
SCMI voltage domain and regulators patches [1] and [2] integration
in v5.11-rc7.
Link: [1] 0f80fcec08
Link: [2] 2add5cacff
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
For all other erase failures, the fail_addr is updated with the
failing address. Only in the case of erase failure due to bad block
detection, the fail_addr is not updated. This change simply updates
the fail_addr for this specific scenario so that it is consistent with
the rest of the code.
Signed-off-by: Farhan Ali <farhan.ali@broadcom.com>
The test adds two pinmux nodes to the device tree, one to test when a
register changes only one pin's mux (pinctrl-single,pins), and the other
to test when more than one pin's mux is changed (pinctrl-single,bits).
This required replacing the controller's register access functions when
the driver is used on sandbox.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
It allows to display the muxing of a given pin. Inspired by more recent
versions of the Linux driver, in addition to the address and the value
of the configuration register I added the pin function retrieved from
the DT. In doing so, the information displayed does not depend on the
platform, being a generic type driver, and it can be useful for debug
purposes.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
The configuration of pinmux registers was implemented with duplicate
code which can be removed by adding two functions for read/write access.
Access to 8-bit registers has also been added.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch is inspired by more recent versions of the Linux driver.
Replacing the default value 0xffffffff of the function mask with 0 is
certainly more conservative in case the "pinctrl-single,function-mask"
DT property is missing.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
In more recent versions of the Linux kernel the driver's probe function
returns an error if the "pinctrl-single,register-width" DT property is
missing. The lack of this information, in fact, does not allow to know
whether to access the registers of the controller at 8, 16, ... bits.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use dev_read_addr_size to get size of the controller's register area.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
The dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); prints the 'reg'
address preceded by the prefix 0x0x instead of 0x. This because the
printf '%pa' format specifier already prepends the prefix '0x' to the
address displayed.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
The pinmux configuration DT node of a peripheral does not define a
physical address but an offset. Only by adding it to the base address of
the controller it is possible to calculate the physical address of the
register to be configured. Printing an offset also requires a different
formatting option than a physical address.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
The 'n' variable is used as a loop counter, not as a physical address,
and is used in a comparison with an int. So it makes sense to change
its type from phys_addr_t to int.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Each row in the pixel array in the bitmap file is padded
if necessary so the row size is always a multiple of 4 bytes.
In current code the complement of row size to a multiple of
4 bytes is further unnecessarily multiplied by the pixel size.
This results in incorrect displaying of bitmaps having row size
that is not a multiple of 4 bytes. Fix this by removing
the unnecessary multiplication.
Tested with 24BPP bitmap and XRGB32 display.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Bitwise OR has a higher operator precedence than the ternary conditional.
Add the missing parentheses.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
drivers/video/mb862xx.c was removed in commit
9c1e098fb9 from December 2020, however, this
last little remnant in drivers/video/cfb_console.c remained.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
SIMPLE_PANEL currently only depends on PANEL && BACKLIGHT, but the code
makes references to dm_gpio_set_value and gpio_request_by_name. These
are defined in drivers/gpio/gpio-uclass.c, so a dependency on DM_GPIO
corrects these link errors:
aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_set_backlight':
/home/kameliya/u-boot/drivers/video/simple_panel.c:42: undefined reference to `dm_gpio_set_value'
aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_enable_backlight':
/home/kameliya/u-boot/drivers/video/simple_panel.c:27: undefined reference to `dm_gpio_set_value'
aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_of_to_plat':
/home/kameliya/u-boot/drivers/video/simple_panel.c:72: undefined reference to `gpio_request_by_name'
This issue is only exposed if you have a board which enables
CONFIG_DM_VIDEO without CONFIG_DM_GPIO; so far, none do, but soon a QEMU
board may.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
This PWM is used in rk3399-gru-bob and rk3399-gru-kevin to control
the display brightness. We can only change the duty cycle, so on
set_config() we just try to match the duty cycle that dividing duty_ns
by period_ns gives us. To disable, we set the duty cycle to zero while
keeping the old value for when we want to re-enable it.
The cros_ec_set_pwm_duty() function is taken from Depthcharge's
cros_ec_set_bl_pwm_duty() but modified to use the generic pwm type.
The driver itself is very loosely based on rk_pwm.c for the general pwm
driver structure.
The devicetree binding file is from Linux, before it was converted to
YAML at 5df5a577a6b4 ("dt-bindings: pwm: Convert google,cros-ec-pwm.txt
to YAML format") in their repo.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The PWM device provided by Chrome OS EC doesn't really support anything
other than setting a relative duty cycle. To support it as a backlight,
this patch makes the PWM period optional in the device tree and pretends
the valid brightness range is its period_ns.
Also adds a sandbox test for a PWM channel that has a fixed period,
checking that the resulting duty_cycle matches on a set_config() even if
the requested period_ns can't be set.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These boards have not been converted to CONFIG_DM_MMC by the deadline.
Remove them. As the P5020 is the last ARCH_P5020 platform, remove that
support as well.
Cc: Andy Fleming <afleming@gmail.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. It is also the only ARCH_T2081 board so remove that support
as well.
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Eddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The mvsata_ide driver was due for DM conversion by v2019.07. As that
has long passed, remove the driver and disable it in the boards which
had enabled it.
Signed-off-by: Tom Rini <trini@konsulko.com>
The dwc ahsata driver is written such that CONFIG_BLK must be enabled,
add this as a dependency in Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
In order to ensure that the VOP registers are in correct state,
add missing support for the VOP reset lines found in the device-tree
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
In order to ensure that the eDP registers are in correct state,
add missing support for the eDP reset lines found in the device-tree.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
The debug string printing the device name, framebuffer address and of node
is using %lu as format for the framebuffer address, which is not so nice.
Change it to %lx.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
In the code, the default polarity is set to positive/positive,
which is neither normal polarity or inverted polarity. It's
only the hardware default. This leads to booting linux with
wrong polarity setting.
Update the code to use PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE
by default instead.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
When booting with EFI and graphics, the memory used for framebuffer
has to be reserved, otherwise it may leads to kernel memory
overwrite.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
According to linux commit "drm/rockchip: analogix_dp: add rk3399 eDP
support" (82872e42bb1501dd9e60ca430f4bae45a469aa64), rk3288 and rk3399
eDP IPs are nearly the same, the difference is in the grf register
(SOC_CON6 versus SOC_CON20). So, change the code to use the right
register on each IP.
The clocks don't seem to be the same, the eDP clock is not at index 1
on rk3399, so don't try changing the clock at index 1 to rate 0 on
rk3399.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
The current code is using an hard coded enum and the of node reg value of
endpoint to find out if the endpoint is mipi/hdmi/lvds/edp/dp. The order
is different between rk3288, rk3399 vop little, rk3399 vop big.
A possible solution would be to make sure that the rk3288.dtsi and
rk3399.dtsi files have "expected" reg value or an other solution is
to find the kind of endpoint by comparing the endpoint compatible value.
This patch is implementing the more flexible second solution.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
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Merge tag 'u-boot-stm32-20210409' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
strsep will change data from original memory address,
in case the memory is in non-sdram/sram place, will
run into a bug(hang at SDRAM: )
just add a temporary array to store bank_name[] to fix this
bug.
Signed-off-by: dillon min <dillon.minfei@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need
around 18ms, common code only delay 10ms, so need to delay extra 8ms.
Otherwise voltage switch will timeout when wait for data0 line.
This IO voltage switch time depends on board design, depend on the
PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF
capacitance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Common code already handle the voltage switch sequence based on spec,
so remove the redundant voltage switch code.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552f ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.
Fixes: b5874b552f ("mmc: fsl_esdhc_imx: add wait_dat0() support")
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Add a weak nand_get_mtd function for nand drivers to provide mtd info
and use this to set pagesize such that reading of non page-aligned
elements can succeed.
The spl_load_simple_fit already handles block block access so all we
need to do is provide the nand writesize as the block length.
Further cleanup of the drivers which use nand_spl_loaders.c such as
am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done
using info from mtd_info instead of statically defined details.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit
for i.MX8M" breaks the 64 bits CAAM.
Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64),
to adapt and not break 64 bits CAAM support, add a new config
CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t".
This config is default enabled when CONFIG_PHYS_64BIT is set except
for iMX8M.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The signature is generated using manufacturing protection private key.
Fix typo in fsl_mfgprot.c.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add DEK blob encapsulation support for IMX8M through "dek_blob" command.
On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob
for encrypted boot.
The DEK blob is encapsulated by OP-TEE through a trusted application call.
U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE
dynamic shared memory.
To enable the DEK blob encapsulation, add to the defconfig:
CONFIG_SECURE_BOOT=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_DEKBLOB=y
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This driver is needed in the pre-relocation phase as the serial
driver depends on it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
In preparation to add SiFive Unmatched board support, let's rename
the existing fu540 board to unleashed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The clock subsystem requires that clk_free be called on clocks obtained via
clk_get_*.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The watchdog won't work if the clock isn't enabled.
Fixes: cf89ef8d10
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is preferred over #if because the compiler can check syntax even if
the feature is disabled. This cannot be used for CONFIG_CLK because
CONFIG_DW_WDT_CLOCK_KHZ is not defined on all platforms.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
log_2_n_round_up is only found in arm. fls performs the same job and is
generic.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The CAAM block used in i.MX8M is 32 bits address size but when the flag
PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a
wrong pointer size.
This patch fixes this issue.
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Enabling CAAM driver for i.MX8M platforms, a 64 bits architecture,
lead to casting warnings: from/to pointer to/from integer with
different size. This patch fix these warnings
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM
devices.
Due to different cache management it's necessary to flush dcache
range for destination address so data can be available in memory.
Add necessary operations in blob_encap() and blob_decap() functions.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This code was originally developed by Raul Cardenas <raul.casas@nxp.com>
and modified to be applied in U-Boot imx_v2017.03.
More information about the initial submission can be seen
in the link below:
https://lists.denx.de/pipermail/u-boot/2016-February/245273.html
i.MX7D has an a protection feature for Manufacturing process.
This feature uses asymmetric encryption to sign and verify
authenticated software handled between parties. This command
enables the use of such feature.
The private key is unique and generated once per device.
And it is stored in secure memory and only accessible by CAAM.
Therefore, the public key generation and signature functions
are the only functions available for the user.
The manufacturing-protection authentication process can be used to
authenticate the chip to the OEM's server.
Command usage:
Print the public key for the device.
- mfgprot pubk
Generates Signature over given data.
- mfgprot sign <data_address> <data_size>
Signed-off-by: Raul Ulises Cardenas <raul.casas@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register,
so it does not support "fuse sense" command like B1.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Currently PCA9450 might have address 0x25 or 0x35, so let user
choose the address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTS
Signed-off-by: haidong.zheng <haidong.zheng@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This is a straightforward conversion of the old, non-dm driver. It was
done in-place as the deadline for non-dm MMC has passed. Previous
commits ensured that no board depends on the old, non-dm variant. Tested
on a Kirkwood based board with eMMC.
Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
Tested-by: Harm Berntsen <harm.berntsen@nedap.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
CC: Pantelis Antoniou <panto@antoniou-consulting.com>
CC: Stefan Roese <sr@denx.de>
CC: Gerald Kerma <drEagle@doukki.net>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add RTC driver for Armada 38x, based on Linux' driver.
For now implement only `marvell,armada-380-rtc` compatible.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Pali Rohár <pali@kernel.org>
Update hwpartition usage
Check bootbus's arguments
workaround for erratum A-011334 for fsl_esdhc driver
add pulse width detection workaround for fsl_esdhc driver
Use alias num before checking mmc index when creating device
This change makes debugging a bit easier as the output is better
readable with the added space. The explicit le16_to_cpu() is not
needed in the output. Also this patch moves the strings into one line
to make the patch checkpatch clean.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Accessing the xHCI controller registers should be done via the
xhci_readl/writel functions. This patch adds this to a few missing
places.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
