Commit graph

72886 commits

Author SHA1 Message Date
Dave Gerlach
cc40e4d947 ram: k3-j721e: lpddr4_pi_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
cde1fcee3e ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
0ef6349326 ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
6a0677d0a0 ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
f1ce7dd92d ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
c1cf7a3d3a ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
5bf74a4884 ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
6da67b081f ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
760b7488f5 dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible
Update the k3-ddrss DT binding document to include compatible
for k3,am64-ddrss.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
55afd2d8f5 configs: am64x_evm_a53: Add Initial support
Add initial A53 defconfig support for AM64x SoCs.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:28 +05:30
Dave Gerlach
d480bd5edc configs: am64x_evm_r5: Add Initial support
Add initial R5 defconfig support for AM64x SoCs.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:28 +05:30
Dave Gerlach
b6059ddc45 arm: dts: k3-am642: Add r5 specific dt support
Add initial support for dt that runs on r5.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:28 +05:30
Dave Gerlach
5db2915a72 arm: dts: k3-am642: Add initial support for EVM
The AM642 EValuation Module (EVM) is a board that provides access to
various peripherals available on the AM642 SoC, such as PCIe, USB 2.0,
CPSW Ethernet, ADC, and more.

Add basic support.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
58211db0a8 arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
dd41886498 dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
Add pinctrl macros for AM64 SoC. These macro definitions are similar to
that of previous platforms, but adding new definitions to avoid any
naming confusions in the soc dts files.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
33b7258947 board: ti: am64x: Add board support for am64x evm
Add board specific initialization for am64x based boards.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
f721502e3f mailbox: k3-sec-proxy: Extend valid thread IDs
AM64x uses a different thread mapping that existing K3 SoCs, so update
the valid thread ID list to include those used for AM64x.

Also remove the comment identifying the purpose of each thread ID. The
purpose of the thread ID is specified when describing the threads in the
device tree and the same ID can mean different things on different SoCs,
so the comment is not useful.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
7288beaa47 mmc: sdhci_am654: Add Support for TI's AM642 SoC
Add support for the controller present on the AM642 SoC.

There are instances:
sdhci0: 8bit bus width, max 400 MBps
sdhci1: 4bit bus width, max 100 MBps

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Keerthy
7fe7713c2e armv8: mach-k3: am642: Add custom MMU support
Change the memory attributes for the DDR regions used by the remote
processors on AM65x so that the cores can see and execute the proper code.

A separate table based on the previous K3 SoCs is introduced since the
number of remote processors and their DDR usage is different between the
SoC families.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Suman Anna
078332cee3 arm: mach-k3: am642: Shut down R5 core after ATF startup on A53
The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs
the R5 SPL that performs the initialization of the System Controller
processor and starting the Arm Trusted Firmware (ATF) on the Arm
Cortex A53 cluster. The Core0 serves as this boot processor and is
parked in WFE after all the initialization. Core1 does not directly
participate in the boot flow, and is simply parked in a WFI.

Power down these R5 cores (and the associated RTI timer resources
that were indirectly powered up) after starting up ATF on A53 by
using the appropriate SYSFW API in release_resources_for_core_shutdown().
This allows these Main R5F cores to be further controlled from the
A53 to run regular applications.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
f4686c3d5b arm: mach-k3: am642: Use mmc start and stop callbacks
To avoid any glitches on MMC clock line, make use of pm per and post
callbacks when loading sysfw.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
d2edabfa8d arm: mach-k3: am642: Load SYSFW binary and config from boot media
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the AM642 early initialization sequence. Also
make use of existing logic to detect if ROM has already loaded sysfw
and avoided attempting to reload and instead just prepare to use already
running firmware.

While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW
to print diagnostic messages.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
6d52c9dd90 arm: mach-k3: am642: Store boot info from ROM
For AM642, ROM supports loading system firmware directly
from boot image. ROM passes information about the number of
images that are loaded to bootloader at a specific address
that is temporary.  Add support for storing this information
somewhere permanent before it gets corrupted.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
b4a8c3b242 arm: mach-k3: am642: Unlock all applicable control MMR registers
To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MAIN domain.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Keerthy
57dba04afb arm: mach-k3: am642: Add support for boot device detection
AM642 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
eb54168bb0 arm: mach-k3: Add basic support for AM642 SoC definition
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dario Binacchi
a47abd7bf4 Revert "fdt: translate address if #size-cells = <0>"
This reverts commit d64b9cdcd4.

As pointed by [1] and [2], the reverted patch made every DT 'reg'
property translatable. What the patch was trying to fix was fixed in a
different way from previously submitted patches which instead of
correcting the generic address translation function fixed the issue with
appropriate platform code.

[1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/
[2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-12 16:27:57 +05:30
Dario Binacchi
5a6caf916c clk: ti: am3-dpll: use custom API for memory access
Using the custom TI functions required not only replacing common memory
access functions but also rewriting the routines used to set bypass and
lock states. As for readl() and writel(), they also required the address
of the register to be accessed, a parameter that is hidden by the TI clk
module.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12 16:27:57 +05:30
Dario Binacchi
b178e1f77b clk: ti: gate: use custom API for memory access
Replaces the common memory access functions used by the driver with the
ones exported from the TI clk module.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12 16:27:57 +05:30
Dario Binacchi
2dd2f3ea6d clk: ti: change clk_ti_latch() signature
The clock access functions exported by the clk header use the
struct clk_ti_reg parameter to get the address of the register. This
must also apply to clk_ti_latch(). Changes to TI's clk-mux and
clk-divider drivers prevented the patch from generating compile errors.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12 16:27:57 +05:30
Dario Binacchi
b1aef0384f clk: ti: add custom API for memory access
As pointed by [1] and [2], commit
d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong:
- It makes every 'reg' DT property translatable. It changes the address
  translation so that for an I2C 'reg' address you'll get back as reg
  the I2C controller address + reg value.
- The quirk must be fixed with platform code.

The clk_ti_get_reg_addr() is the platform code able to make the correct
address translation for the AM33xx clocks registers. Its implementation
was inspired by the Linux Kernel code.

[1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/
[2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12 16:27:57 +05:30
Tom Rini
b107761b81 Prepare v2021.07-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-10 17:03:22 -04:00
Tom Rini
3ee71c5729 Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- x86: correct regwidth prompt in cbsysinfo
- virtio: convert README.virtio to reST
2021-05-10 08:02:00 -04:00
Bin Meng
200fdd3bff MAINTAINERS: Add an entry for VirtIO
This was missed when VirtIO support was initially brought to U-Boot
back in 2018. Add an entry for it and list myself as the maintainer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-10 13:56:12 +08:00
Bin Meng
9cea9abbe4 doc: develop: Convert README.virtio to reST
This converts the existing README.virtio to reST, and puts it under
the develop/driver-model/ directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-10 13:56:12 +08:00
Simon Glass
b8db1c1388 x86: Correct regwidth prompt in cbsysinfo
This should be 'regwidth', not 'baud'. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-10 13:56:12 +08:00
Tom Rini
07b53103b7 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-05-07 08:57:32 -04:00
Tom Rini
1b8ad819ce Merge branch '2021-05-06-misc-updates'
- Allow for boards to update bootargs before booting the OS (helpful in
  some forms of secure boot).
- Enhance GPT write support.
- gpio-sysinfo updates
- Allow env to be appended from dtb
2021-05-06 11:00:07 -04:00
Heinrich Schuchardt
91e4b7516d cmd/exception: support ebreak exception on RISC-V
The ebreak instruction should generate a breakpoint exception.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-05 16:13:12 +08:00
Dylan Jhong
1412b8d48a atcspi200: Add timeout mechanism in spi_xfer()
Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-05 16:12:14 +08:00
Green Wan
bc8bbb77f7 riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-05 16:11:27 +08:00
Green Wan
edd9ad8194 riscv: cpu: Add callback to init each core
Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-05 16:11:22 +08:00
Niko Mauno
f0b21ebd41 fdt_support.c: Allow late kernel cmdline modification
By declaring board-specific board_fdt_chosen_bootargs() the kernel
command line arguments can be adjusted before injecting to flat dt
chosen node.

Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2021-05-04 12:52:46 -04:00
Farhan Ali
653cd92d66 cmd: gpt: Add option to write GPT partitions to environment variable
This change would enhance the existing 'gpt read' command to allow
(optionally) writing of the read GPT partitions to an environment
variable in the UBOOT partitions layout format. This would allow users
to easily change the overall partition settings by editing said variable
and then using the variable in the 'gpt write' and 'gpt verify' commands.

Signed-off-by: Farhan Ali <farhan.ali@broadcom.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Corneliu Doban <cdoban@broadcom.com>
Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04 12:52:46 -04:00
Rasmus Villemoes
8c72842af5 sandbox: add test of CONFIG_ENV_IMPORT_FDT
Check that a variable defined in /config/environment is found in the
run-time environment, and that clearing fdt_env_path from within that
node works.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: Conditionalize the test being linked in]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-04 12:52:30 -04:00
Rasmus Villemoes
95fd977201 env: allow environment to be amended from control dtb
It can be useful to use the same U-Boot binary for multiple purposes,
say the normal one, one for developers that allow breaking into the
U-Boot shell, and one for use during bootstrapping which runs a
special-purpose bootcmd. Or one can have several board variants that
can share almost all boot logic, but just needs a few tweaks in the
variables used by the boot script.

To that end, allow the control dtb to contain a /config/enviroment
node (or whatever one puts in fdt_env_path variable), whose
property/value pairs are used to update the run-time environment after
it has been loaded from its persistent location.

The indirection via fdt_env_path is for maximum flexibility - for
example, should the user wish (or board logic dictate) that the values
in the DTB should no longer be applied, one simply needs to delete the
fdt_env_path variable; that can even be done automatically by
including a

  fdt_env_path = "";

property in the DTB node.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2021-05-04 11:50:50 -04:00
Sean Anderson
1cbfed8d3e test: Add gpio-sysinfo test
This adds a test for the gpio-sysinfo driver.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04 07:57:18 -04:00
Sean Anderson
54aa07fdfc sysinfo: Add gpio-sysinfo driver
This uses the newly-added dm_gpio_get_values_as_int_base3 function to
implement a sysinfo device. The revision map is stored in the device tree.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04 07:57:18 -04:00
Sean Anderson
4d65c6bcd7 sysinfo: Require that sysinfo_detect be called before other methods
This has the uclass enforce calling detect() before other methods.  This
allows drivers to cache information in detect() and perform (cheaper)
retrieval in the other accessors. This also modifies the only instance
where this sequencing was not followed.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04 07:57:18 -04:00
Sean Anderson
eed0a7a3e6 sysinfo: Use global sysinfo IDs for existing sysinfo drivers
Since 07c9e683a4 ("smbios: Allow a few values to come from sysinfo")
there are common global sysinfo IDs. This patch moved existing IDs above
SYSINFO_ID_USER.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04 07:57:18 -04:00