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Merge branch '2021-04-11-remove-non-migrated-boards'

Browse source 
- Remove a large number of boards that have not migrated to DM_MMC, for
  which the migration deadline with 2 years ago at v2019.04.
This commit is contained in:
Tom Rini 2021-04-11 14:11:05 -04:00
commit 3b676a1662
428 changed files with 21 additions and 39732 deletions
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6
.azure-pipelines.yml
View file

@ -195,12 +195,6 @@ jobs:
evb_ast2500:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
vexpress_ca15_tc2:
TEST_PY_BD: "vexpress_ca15_tc2"
TEST_PY_ID: "--id qemu"
vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"

12
.gitlab-ci.yml
View file

@ -206,18 +206,6 @@ sandbox_flattree test.py:
TEST_PY_BD: "sandbox_flattree"
<<: *buildman_and_testpy_dfn
vexpress_ca15_tc2 test.py:
variables:
TEST_PY_BD: "vexpress_ca15_tc2"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
vexpress_ca9x4 test.py:
variables:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
integratorcp_cm926ejs test.py:
variables:
TEST_PY_BD: "integratorcp_cm926ejs"

2
Makefile
View file

@ -1084,8 +1084,6 @@ endif
$(call deprecated,CONFIG_DM_MMC CONFIG_BLK,MMC,v2019.04,$(CONFIG_MMC))
$(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
USB,v2019.07,$(CONFIG_USB))
$(call deprecated,CONFIG_AHCI,AHCI instead of CONFIG_MVSATA_IDE,v2019.07, \
$(CONFIG_MVSATA_IDE))
$(call deprecated,CONFIG_AHCI,AHCI,v2019.07, $(CONFIG_LIBATA))
$(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
$(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\

53
arch/arm/Kconfig
View file

@ -346,7 +346,7 @@ config SYS_CACHELINE_SIZE
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
TARGET_BCMNSP || CPU_PXA || RZA1
CPU_PXA || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK
@ -561,11 +561,6 @@ config ARCH_MVEBU
select SPI
imply CMD_DM
config TARGET_APF27
bool "Support apf27"
select CPU_ARM926EJS
select SUPPORT_SPL
config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
@ -650,13 +645,6 @@ config ARCH_BCM6858
select OF_CONTROL
imply CMD_DM
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select PL011_SERIAL
config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
select CPU_V7A
@ -668,28 +656,6 @@ config ARCH_BCMSTB
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
select CPU_V7A
select PL011_SERIAL
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
select PL011_SERIAL
config TARGET_BCM23550_W1D
bool "Support bcm23550_w1d"
select CPU_V7A
imply CRC32_VERIFY
imply FAT_WRITE
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
select CPU_V7A
imply CRC32_VERIFY
imply FAT_WRITE
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
@ -701,10 +667,6 @@ config TARGET_BCMCYGNUS
imply HASH_VERIFY
imply NETDEVICES
config TARGET_BCMNSP
bool "Support bcmnsp"
select CPU_V7A
config TARGET_BCMNS2
bool "Support Broadcom Northstar2"
select ARM64
@ -954,11 +916,6 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
config TARGET_S32V234EVB
bool "Support s32v234evb"
select ARM64
select SYS_FSL_ERRATUM_ESDHC111
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
select ARM64
@ -1969,18 +1926,11 @@ source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
source "board/broadcom/bcm23550_w1d/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcm963158/Kconfig"
source "board/broadcom/bcm968360bg/Kconfig"
source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/broadcom/bcmns2/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
@ -2003,7 +1953,6 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"

2
arch/arm/cpu/armv8/Kconfig
View file

@ -116,7 +116,7 @@ config PSCI_RESET
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
!ARCH_UNIPHIER
help
Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.

6
arch/arm/cpu/armv8/s32v234/Makefile
View file

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
obj-y += generic.o
obj-y += cpu.o

102
arch/arm/cpu/armv8/s32v234/cpu.c
View file

@ -1,102 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/mc_me_regs.h>
#include <linux/bitops.h>
#include "cpu.h"
u32 cpu_mask(void)
{
return readl(MC_ME_CS);
}
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
#define S32V234_DRAM_BASE1 0x80000000UL
#define S32V234_DRAM_SIZE1 0x40000000UL
#define S32V234_DRAM_BASE2 0xC0000000UL
#define S32V234_DRAM_SIZE2 0x20000000UL
#define S32V234_PERIPH_BASE 0x40000000UL
#define S32V234_PERIPH_SIZE 0x40000000UL
static struct mm_region s32v234_mem_map[] = {
{
.virt = S32V234_IRAM_BASE,
.phys = S32V234_IRAM_BASE,
.size = S32V234_IRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
.virt = S32V234_DRAM_BASE1,
.phys = S32V234_DRAM_BASE1,
.size = S32V234_DRAM_SIZE1,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
.virt = S32V234_PERIPH_BASE,
.phys = S32V234_PERIPH_BASE,
.size = S32V234_PERIPH_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
/* TODO: Do we need these? */
/* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
}, {
.virt = S32V234_DRAM_BASE2,
.phys = S32V234_DRAM_BASE2,
.size = S32V234_DRAM_SIZE2,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_OUTER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = s32v234_mem_map;
#endif
/*
* Return the number of cores on this SOC.
*/
int cpu_numcores(void)
{
int numcores;
u32 mask;
mask = cpu_mask();
numcores = hweight32(cpu_mask());
/* Verify if M4 is deactivated */
if (mask & 0x1)
numcores--;
return numcores;
}
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
int rv;
asm volatile ("dsb sy");
rv = fsl_s32v234_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
asm volatile ("sev");
return 0;
}
#endif /* CONFIG_ARCH_EARLY_INIT_R */

7
arch/arm/cpu/armv8/s32v234/cpu.h
View file

@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
*/
u32 cpu_mask(void);
int cpu_numcores(void);

354
arch/arm/cpu/armv8/s32v234/generic.c
View file

@ -1,354 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/mc_cgm_regs.h>
#include <asm/arch/mc_me_regs.h>
#include <asm/arch/mc_rgm_regs.h>
#include <netdev.h>
#include <div64.h>
#include <errno.h>
u32 get_cpu_rev(void)
{
struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
u32 cpu = readl(&mscmir->cpxtype);
return cpu;
}
DECLARE_GLOBAL_DATA_PTR;
static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
u32 pllfd, u32 selected_output)
{
u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
u32 plldv_rfdphi_div = 0, fout = 0;
u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
if (selected_output > DFS_MAXNUMBER) {
return -1;
}
plldv_prediv =
(plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
/* The formula for VCO is from TR manual, rev. D */
vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
if (selected_output != 0) {
/* Determine the RFDPHI for PHI1 */
plldv_rfdphi_div =
(plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
PLLDIG_PLLDV_RFDPHI1_OFFSET;
plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
dfs_portn =
readl(DFS_DVPORTn(pll, selected_output - 1));
dfs_mfi =
(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
DFS_DVPORTn_MFI_OFFSET;
dfs_mfn =
(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
DFS_DVPORTn_MFI_OFFSET;
fout = vco / (dfs_mfi + (dfs_mfn / 256));
} else {
fout = vco / plldv_rfdphi_div;
}
} else {
/* Determine the RFDPHI for PHI0 */
plldv_rfdphi_div =
(plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
PLLDIG_PLLDV_RFDPHI_OFFSET;
fout = vco / plldv_rfdphi_div;
}
return fout;
}
/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
u32 selected_output)
{
u32 plldv, pllfd;
plldv = readl(PLLDIG_PLLDV(pll));
pllfd = readl(PLLDIG_PLLFD(pll));
return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
}
static u32 get_mcu_main_clk(void)
{
u32 coreclk_div;
u32 sysclk_sel;
u32 freq = 0;
sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
coreclk_div =
readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
coreclk_div += 1;
switch (sysclk_sel) {
case MC_CGM_SC_SEL_FIRC:
freq = FIRC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_XOSC:
freq = XOSC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_ARMPLL:
/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
break;
case MC_CGM_SC_SEL_CLKDISABLE:
printf("Sysclk is disabled\n");
break;
default:
printf("unsupported system clock select\n");
}
return freq / coreclk_div;
}
static u32 get_sys_clk(u32 number)
{
u32 sysclk_div, sysclk_div_number;
u32 sysclk_sel;
u32 freq = 0;
switch (number) {
case 3:
sysclk_div_number = 0;
break;
case 6:
sysclk_div_number = 1;
break;
default:
printf("unsupported system clock \n");
return -1;
}
sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
sysclk_div =
readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
MC_CGM_SC_DCn_PREDIV_MASK;
sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
sysclk_div += 1;
switch (sysclk_sel) {
case MC_CGM_SC_SEL_FIRC:
freq = FIRC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_XOSC:
freq = XOSC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_ARMPLL:
/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
break;
case MC_CGM_SC_SEL_CLKDISABLE:
printf("Sysclk is disabled\n");
break;
default:
printf("unsupported system clock select\n");
}
return freq / sysclk_div;
}
static u32 get_peripherals_clk(void)
{
u32 aux5clk_div;
u32 freq = 0;
aux5clk_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
aux5clk_div += 1;
freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
return freq / aux5clk_div;
}
static u32 get_uart_clk(void)
{
u32 auxclk3_div, auxclk3_sel, freq = 0;
auxclk3_sel =
readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
auxclk3_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
auxclk3_div += 1;
switch (auxclk3_sel) {
case MC_CGM_ACn_SEL_FIRC:
freq = FIRC_CLK_FREQ;
break;
case MC_CGM_ACn_SEL_XOSC:
freq = XOSC_CLK_FREQ;
break;
case MC_CGM_ACn_SEL_PERPLLDIVX:
freq = get_peripherals_clk() / 3;
break;
case MC_CGM_ACn_SEL_SYSCLK:
freq = get_sys_clk(6);
break;
default:
printf("unsupported system clock select\n");
}
return freq / auxclk3_div;
}
static u32 get_fec_clk(void)
{
u32 aux2clk_div;
u32 freq = 0;
aux2clk_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
aux2clk_div += 1;
freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
return freq / aux2clk_div;
}
static u32 get_usdhc_clk(void)
{
u32 aux15clk_div;
u32 freq = 0;
aux15clk_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
aux15clk_div += 1;
freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
return freq / aux15clk_div;
}
static u32 get_i2c_clk(void)
{
return get_peripherals_clk();
}
/* return clocks in Hz */
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_PERIPHERALS_CLK:
return get_peripherals_clk();
case MXC_UART_CLK:
return get_uart_clk();
case MXC_FEC_CLK:
return get_fec_clk();
case MXC_I2C_CLK:
return get_i2c_clk();
case MXC_USDHC_CLK:
return get_usdhc_clk();
default:
break;
}
printf("Error: Unsupported function to read the frequency! \
Please define it correctly!");
return -1;
}
/* Not yet implemented - int soc_clk_dump(); */
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
switch (cause) {
case F_SWT4:
return "WDOG";
case F_JTAG:
return "JTAG";
case F_FCCU_SOFT:
return "FCCU soft reaction";
case F_FCCU_HARD:
return "FCCU hard reaction";
case F_SOFT_FUNC:
return "Software Functional reset";
case F_ST_DONE:
return "Self Test done reset";
case F_EXT_RST:
return "External reset";
default:
return "unknown reset";
}
}
#define SRC_SCR_SW_RST (1<<12)
void reset_cpu(void)
{
printf("Feature not supported.\n");
};
int print_cpuinfo(void)
{
printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
int cpu_eth_init(struct bd_info * bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
#endif
return 0;
}

4
arch/arm/dts/Makefile
View file

@ -1071,10 +1071,6 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb

437
arch/arm/dts/vexpress-v2m-rs1.dtsi
View file

@ -1,437 +0,0 @@
/*
* ARM Ltd. Versatile Express
*
* Motherboard Express uATX
* V2M-P1
*
* HBI-0190D
*
* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
* Technical Reference Manual)
*
* WARNING! The hardware described in this file is independent from the
* original variant (vexpress-v2m.dtsi), but there is a strong
* correspondence between the two configurations.
*
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
* CHANGES TO vexpress-v2m.dtsi!
*/
/ {
smb@8000000 {
motherboard {
model = "V2M-P1";
arm,hbi = <0x190>;
arm,vexpress,site = <0>;
arm,v2m-memory-map = "rs1";
compatible = "arm,vexpress,v2m-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
ranges;
flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<4 0x00000000 0x04000000>;
bank-width = <4>;
};
psram@1,00000000 {
compatible = "arm,vexpress-psram", "mtd-ram";
reg = <1 0x00000000 0x02000000>;
bank-width = <4>;
};
ethernet@2,02000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&v2m_fixed_3v3>;
vddvario-supply = <&v2m_fixed_3v3>;
};
usb@2,03000000 {
compatible = "nxp,usb-isp1761";
reg = <2 0x03000000 0x20000>;
interrupts = <16>;
port1-otg;
};
iofpga@3,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@10000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10000 0x1000>;
v2m_led_gpios: gpio@8 {
compatible = "arm,vexpress-sysreg,sys_led";
reg = <0x008 4>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: gpio@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
reg = <0x048 4>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: gpio@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
reg = <0x04c 4>;
gpio-controller;
#gpio-cells = <2>;
};
};
v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
/* PCI-E I2C bus */
v2m_i2c_pcie: i2c@30000 {
compatible = "arm,versatile-i2c";
reg = <0x030000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
pcie-switch@60 {
compatible = "idt,89hpes32h8";
reg = <0x60>;
};
};
aaci@40000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
clocks = <&smbclk>;
clock-names = "apb_pclk";
};
mmci@50000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9>, <10>;
cd-gpios = <&v2m_mmc_gpios 0 0>;
wp-gpios = <&v2m_mmc_gpios 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "mclk", "apb_pclk";
};
kmi@60000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <12>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@70000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <13>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
v2m_serial0: uart@90000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
wdt@f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
clock-names = "wdogclk", "apb_pclk";
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x1000>;
interrupts = <2>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <3>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
/* DVI I2C bus */
v2m_i2c_dvi: i2c@160000 {
compatible = "arm,versatile-i2c";
reg = <0x160000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
dvi-transmitter@39 {
compatible = "sil,sii9022-tpi", "sil,sii9022";
reg = <0x39>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dvi_bridge_in: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
};
};
dvi-transmitter@60 {
compatible = "sil,sii9022-cpi", "sil,sii9022";
reg = <0x60>;
};
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
interrupts = <4>;
clocks = <&smbclk>;
clock-names = "apb_pclk";
};
compact-flash@1a0000 {
compatible = "arm,vexpress-cf", "ata-generic";
reg = <0x1a0000 0x100
0x1a0100 0xf00>;
reg-shift = <2>;
};
clcd@1f0000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f0000 0x1000>;
interrupt-names = "combined";
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&smbclk>;
clock-names = "clcdclk", "apb_pclk";
/* 800x600 16bpp @36MHz works fine */
max-memory-bandwidth = <54000000>;
memory-region = <&vram>;
port {
clcd_pads: endpoint {
remote-endpoint = <&dvi_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
};
};
v2m_fixed_3v3: fixed-regulator-0 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
leds {
compatible = "gpio-leds";
user1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
user2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
user3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
user4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
user5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
user6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
user7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
user8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";
};
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <25000000 60000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk0";
};
v2m_oscclk1: oscclk1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <23750000 65000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk1";
};
v2m_oscclk2: oscclk2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <24000000 24000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk2";
};
volt-vio {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "VIO";
regulator-always-on;
label = "VIO";
};
temp-mcc {
/* MCC internal operating temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "MCC";
};
reset {
compatible = "arm,vexpress-reset";
arm,vexpress-sysreg,func = <5 0>;
};
muxfpga {
compatible = "arm,vexpress-muxfpga";
arm,vexpress-sysreg,func = <7 0>;
};
shutdown {
compatible = "arm,vexpress-shutdown";
arm,vexpress-sysreg,func = <8 0>;
};
reboot {
compatible = "arm,vexpress-reboot";
arm,vexpress-sysreg,func = <9 0>;
};
dvimode {
compatible = "arm,vexpress-dvimode";
arm,vexpress-sysreg,func = <11 0>;
};
};
};
};
};

451
arch/arm/dts/vexpress-v2m.dtsi
View file

@ -1,451 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ARM Ltd. Versatile Express
*
* Motherboard Express uATX
* V2M-P1
*
* HBI-0190D
*
* Original memory map ("Legacy memory map" in the board's
* Technical Reference Manual)
*
* WARNING! The hardware described in this file is independent from the
* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
* correspondence between the two configurations.
*
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
* CHANGES TO vexpress-v2m-rs1.dtsi!
*/
/ {
smb@4000000 {
motherboard {
model = "V2M-P1";
arm,hbi = <0x190>;
arm,vexpress,site = <0>;
compatible = "arm,vexpress,v2m-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
ranges;
flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<1 0x00000000 0x04000000>;
bank-width = <4>;
};
psram@2,00000000 {
compatible = "arm,vexpress-psram", "mtd-ram";
reg = <2 0x00000000 0x02000000>;
bank-width = <4>;
};
ethernet@3,02000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <3 0x02000000 0x10000>;
interrupts = <15>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&v2m_fixed_3v3>;
vddvario-supply = <&v2m_fixed_3v3>;
};
usb@3,03000000 {
compatible = "nxp,usb-isp1761";
reg = <3 0x03000000 0x20000>;
interrupts = <16>;
port1-otg;
};
iofpga@7,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 7 0 0x20000>;
v2m_sysreg: sysreg@0 {
compatible = "arm,vexpress-sysreg";
reg = <0x00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000>;
v2m_led_gpios: gpio@8 {
compatible = "arm,vexpress-sysreg,sys_led";
reg = <0x008 4>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: gpio@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
reg = <0x048 4>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: gpio@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
reg = <0x04c 4>;
gpio-controller;
#gpio-cells = <2>;
};
};
v2m_sysctl: sysctl@1000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x01000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
/* PCI-E I2C bus */
v2m_i2c_pcie: i2c@2000 {
compatible = "arm,versatile-i2c";
reg = <0x02000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
pcie-switch@60 {
compatible = "idt,89hpes32h8";
reg = <0x60>;
};
};
aaci@4000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x04000 0x1000>;
interrupts = <11>;
clocks = <&smbclk>;
clock-names = "apb_pclk";
};
mmci@5000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x05000 0x1000>;
interrupts = <9>, <10>;
cd-gpios = <&v2m_mmc_gpios 0 0>;
wp-gpios = <&v2m_mmc_gpios 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "mclk", "apb_pclk";
};
kmi@6000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x06000 0x1000>;
interrupts = <12>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@7000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x07000 0x1000>;
interrupts = <13>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
v2m_serial0: uart@9000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x09000 0x1000>;
interrupts = <5>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@a000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a000 0x1000>;
interrupts = <6>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@b000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b000 0x1000>;
interrupts = <7>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@c000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c000 0x1000>;
interrupts = <8>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
wdt@f000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
clock-names = "wdogclk", "apb_pclk";
};
v2m_timer01: timer@11000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x11000 0x1000>;
interrupts = <2>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@12000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <3>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
/* DVI I2C bus */
v2m_i2c_dvi: i2c@16000 {
compatible = "arm,versatile-i2c";
reg = <0x16000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
dvi-transmitter@39 {
compatible = "sil,sii9022-tpi", "sil,sii9022";
reg = <0x39>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* Both the core tile and the motherboard routes their output
* pads to this transmitter. The motherboard system controller
* can select one of them as input using a mux register in
* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
* the only platform with this specific set-up.
*/
port@0 {
reg = <0>;
dvi_bridge_in_ct: endpoint {
remote-endpoint = <&clcd_pads_ct>;
};
};
port@1 {
reg = <1>;
dvi_bridge_in_mb: endpoint {
remote-endpoint = <&clcd_pads_mb>;
};
};
};
};
dvi-transmitter@60 {
compatible = "sil,sii9022-cpi", "sil,sii9022";
reg = <0x60>;
};
};
rtc@17000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x17000 0x1000>;
interrupts = <4>;
clocks = <&smbclk>;
clock-names = "apb_pclk";
};
compact-flash@1a000 {
compatible = "arm,vexpress-cf", "ata-generic";
reg = <0x1a000 0x100
0x1a100 0xf00>;
reg-shift = <2>;
};
clcd@1f000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f000 0x1000>;
interrupt-names = "combined";
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&smbclk>;
clock-names = "clcdclk", "apb_pclk";
/* 800x600 16bpp @36MHz works fine */
max-memory-bandwidth = <54000000>;
memory-region = <&vram>;
port {
clcd_pads_mb: endpoint {
remote-endpoint = <&dvi_bridge_in_mb>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
};
};
v2m_fixed_3v3: fixed-regulator-0 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
leds {
compatible = "gpio-leds";
user1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
user2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
user3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
user4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
user5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
user6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
user7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
user8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";
};
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <25000000 60000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk0";
};
v2m_oscclk1: oscclk1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <23750000 65000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk1";
};
v2m_oscclk2: oscclk2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <24000000 24000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk2";
};
volt-vio {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "VIO";
regulator-always-on;
label = "VIO";
};
temp-mcc {
/* MCC internal operating temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "MCC";
};
reset {
compatible = "arm,vexpress-reset";
arm,vexpress-sysreg,func = <5 0>;
};
muxfpga {
compatible = "arm,vexpress-muxfpga";
arm,vexpress-sysreg,func = <7 0>;
};
shutdown {
compatible = "arm,vexpress-shutdown";
arm,vexpress-sysreg,func = <8 0>;
};
reboot {
compatible = "arm,vexpress-reboot";
arm,vexpress-sysreg,func = <9 0>;
};
dvimode {
compatible = "arm,vexpress-dvimode";
arm,vexpress-sysreg,func = <11 0>;
};
};
};
};
};

682
arch/arm/dts/vexpress-v2p-ca15_a7.dts
View file

@ -1,682 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ARM Ltd. Versatile Express
*
* CoreTile Express A15x2 A7x3
* Cortex-A15_A7 MPCore (V2P-CA15_A7)
*
* HBI-0249A
*/
/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"
/ {
model = "V2P-CA15_CA7";
arm,hbi = <0x249>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
cci-control-port = <&cci_control1>;
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <990>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
cci-control-port = <&cci_control1>;
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <990>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control2>;
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
capacity-dmips-mhz = <516>;
dynamic-power-coefficient = <133>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control2>;
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
capacity-dmips-mhz = <516>;
dynamic-power-coefficient = <133>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control2>;
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
capacity-dmips-mhz = <516>;
dynamic-power-coefficient = <133>;
};
idle-states {
CLUSTER_SLEEP_BIG: cluster-sleep-big {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <500>;
min-residency-us = <2500>;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Chipselect 2 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0 0x18000000 0 0x00800000>;
no-map;
};
};
wdt@2a490000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0 0x2a490000 0 0x1000>;
interrupts = <0 98 4>;
clocks = <&oscclk6a>, <&oscclk6a>;
clock-names = "wdogclk", "apb_pclk";
};
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <0 85 4>;
clocks = <&hdlcd_clk>;
clock-names = "pxlclk";
};
memory-controller@2b0a0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0 0x2b0a0000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x2000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu,r0";
reg = <0x9000 0x5000>;
interrupts = <0 105 4>,
<0 101 4>,
<0 102 4>,
<0 103 4>,
<0 104 4>;
};
};
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
};
dma@7ff00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0 0x7ff00000 0 0x1000>;
interrupts = <0 92 4>,
<0 88 4>,
<0 89 4>,
<0 90 4>,
<0 91 4>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
};
scc@7fff0000 {
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
reg = <0 0x7fff0000 0 0x1000>;
interrupts = <0 95 4>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
pmu-a15 {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
interrupt-affinity = <&cpu0>,
<&cpu1>;
};
pmu-a7 {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 128 4>,
<0 129 4>,
<0 130 4>;
interrupt-affinity = <&cpu2>,
<&cpu3>,
<&cpu4>;
};
oscclk6a: oscclk6a {
/* Reference 24MHz clock */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "oscclk6a";
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0 {
/* A15 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <17000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk0";
};
oscclk1 {
/* A15 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <17000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk1";
};
oscclk2 {
/* A7 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <17000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk2";
};
oscclk3 {
/* A7 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
freq-range = <17000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk3";
};
oscclk4 {
/* External AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <20000000 40000000>;
#clock-cells = <0>;
clock-output-names = "oscclk4";
};
hdlcd_clk: oscclk5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
freq-range = <23750000 165000000>;
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
smbclk: oscclk6 {
/* Static memory controller clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
freq-range = <20000000 40000000>;
#clock-cells = <0>;
clock-output-names = "oscclk6";
};
oscclk7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
freq-range = <17000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk7";
};
oscclk8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
freq-range = <20000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk8";
};
volt-a15 {
/* A15 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "A15 Vcore";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
label = "A15 Vcore";
};
volt-a7 {
/* A7 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
regulator-name = "A7 Vcore";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
label = "A7 Vcore";
};
amp-a15 {
/* Total current for the two A15 cores */
compatible = "arm,vexpress-amp";
arm,vexpress-sysreg,func = <3 0>;
label = "A15 Icore";
};
amp-a7 {
/* Total current for the three A7 cores */
compatible = "arm,vexpress-amp";
arm,vexpress-sysreg,func = <3 1>;
label = "A7 Icore";
};
temp-dcc {
/* DCC internal temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
power-a15 {
/* Total power for the two A15 cores */
compatible = "arm,vexpress-power";
arm,vexpress-sysreg,func = <12 0>;
label = "A15 Pcore";
};
power-a7 {
/* Total power for the three A7 cores */
compatible = "arm,vexpress-power";
arm,vexpress-sysreg,func = <12 1>;
label = "A7 Pcore";
};
energy-a15 {
/* Total energy for the two A15 cores */
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>, <13 1>;
label = "A15 Jcore";
};
energy-a7 {
/* Total energy for the three A7 cores */
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 2>, <13 3>;
label = "A7 Jcore";
};
};
etb@20010000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
tpiu@20030000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0x20030000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
replicator {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
funnel@20040000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
/* Input port #3 is for ITM, not supported here */
port@4 {
reg = <4>;
funnel_in_port4: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@5 {
reg = <5>;
funnel_in_port5: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
};
};
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2201c000 0 0x1000>;
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
ptm@2201d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2201d000 0 0x1000>;
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
etm@2203c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2203c000 0 0x1000>;
cpu = <&cpu2>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port2>;
};
};
};
};
etm@2203d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2203d000 0 0x1000>;
cpu = <&cpu3>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port4>;
};
};
};
};
etm@2203e000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2203e000 0 0x1000>;
cpu = <&cpu4>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out_port: endpoint {
remote-endpoint = <&funnel_in_port5>;
};
};
};
};
smb: smb@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
};
site2: hsb@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40000000 0x3fef0000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 3>;
interrupt-map = <0 0 &gic 0 36 4>,
<0 1 &gic 0 37 4>,
<0 2 &gic 0 38 4>,
<0 3 &gic 0 39 4>;
};
};

280
arch/arm/dts/vexpress-v2p-ca5s.dts
View file

@ -1,280 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ARM Ltd. Versatile Express
*
* CoreTile Express A5x2
* Cortex-A5 MPCore (V2P-CA5s)
*
* HBI-0225B
*/
/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"
/ {
model = "V2P-CA5s";
arm,hbi = <0x225>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <1>;
next-level-cache = <&L2>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Chipselect 2 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0x18000000 0x00800000>;
no-map;
};
};
hdlcd@2a110000 {
compatible = "arm,hdlcd";
reg = <0x2a110000 0x1000>;
interrupts = <0 85 4>;
clocks = <&hdlcd_clk>;
clock-names = "pxlclk";
};
memory-controller@2a150000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0x2a150000 0x1000>;
clocks = <&axi_clk>;
clock-names = "apb_pclk";
};
memory-controller@2a190000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0x2a190000 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
clocks = <&axi_clk>;
clock-names = "apb_pclk";
};
scu@2c000000 {
compatible = "arm,cortex-a5-scu";
reg = <0x2c000000 0x58>;
};
timer@2c000600 {
compatible = "arm,cortex-a5-twd-timer";
reg = <0x2c000600 0x20>;
interrupts = <1 13 0x304>;
};
timer@2c000200 {
compatible = "arm,cortex-a5-global-timer",
"arm,cortex-a9-global-timer";
reg = <0x2c000200 0x20>;
interrupts = <1 11 0x304>;
clocks = <&cpu_clk>;
};
watchdog@2c000620 {
compatible = "arm,cortex-a5-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <1 14 0x304>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
<0x2c000100 0x100>;
};
L2: cache-controller@2c0f0000 {
compatible = "arm,pl310-cache";
reg = <0x2c0f0000 0x1000>;
interrupts = <0 84 4>;
cache-level = <2>;
};
pmu {
compatible = "arm,cortex-a5-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
cpu_clk: oscclk0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <50000000 100000000>;
#clock-cells = <0>;
clock-output-names = "oscclk0";
};
axi_clk: oscclk1 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <5000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk1";
};
oscclk2 {
/* DDR2 */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <80000000 120000000>;
#clock-cells = <0>;
clock-output-names = "oscclk2";
};
hdlcd_clk: oscclk3 {
/* HDLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
freq-range = <23750000 165000000>;
#clock-cells = <0>;
clock-output-names = "oscclk3";
};
oscclk4 {
/* Test chip gate configuration */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <80000000 80000000>;
#clock-cells = <0>;
clock-output-names = "oscclk4";
};
smbclk: oscclk5 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
freq-range = <25000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
temp-dcc {
/* DCC internal operating temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
};
smb: smb@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x04000000>,
<1 0 0x14000000 0x04000000>,
<2 0 0x18000000 0x04000000>,
<3 0 0x1c000000 0x04000000>,
<4 0 0x0c000000 0x04000000>,
<5 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
};
site2: hsb@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000000 0x40000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 3>;
interrupt-map = <0 0 &gic 0 36 4>,
<0 1 &gic 0 37 4>,
<0 2 &gic 0 38 4>,
<0 3 &gic 0 39 4>;
};
};

368
arch/arm/dts/vexpress-v2p-ca9.dts
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@ -1,368 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ARM Ltd. Versatile Express
*
* CoreTile Express A9x4
* Cortex-A9 MPCore (V2P-CA9)
*
* HBI-0191B
*/
/dts-v1/;
#include "vexpress-v2m.dtsi"
/ {
model = "V2P-CA9";
arm,hbi = <0x191>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
A9_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
A9_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
A9_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
next-level-cache = <&L2>;
};
A9_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
next-level-cache = <&L2>;
};
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Chipselect 3 is physically at 0x4c000000 */
vram: vram@4c000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0x4c000000 0x00800000>;
no-map;
};
};
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <0 44 4>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
/* 1024x768 16bpp @65MHz */
max-memory-bandwidth = <95000000>;
port {
clcd_pads_ct: endpoint {
remote-endpoint = <&dvi_bridge_in_ct>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
};
memory-controller@100e0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0x100e0000 0x1000>;
clocks = <&oscclk2>;
clock-names = "apb_pclk";
};
memory-controller@100e1000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0x100e1000 0x1000>;
interrupts = <0 45 4>,
<0 46 4>;
clocks = <&oscclk2>;
clock-names = "apb_pclk";
};
timer@100e4000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x100e4000 0x1000>;
interrupts = <0 48 4>,
<0 49 4>;
clocks = <&oscclk2>, <&oscclk2>;
clock-names = "timclk", "apb_pclk";
status = "disabled";
};
watchdog@100e5000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x100e5000 0x1000>;
interrupts = <0 51 4>;
clocks = <&oscclk2>, <&oscclk2>;
clock-names = "wdogclk", "apb_pclk";
};
scu@1e000000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1e000000 0x58>;
};
timer@1e000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e000600 0x20>;
interrupts = <1 13 0xf04>;
};
watchdog@1e000620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x1e000620 0x20>;
interrupts = <1 14 0xf04>;
};
gic: interrupt-controller@1e001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1e001000 0x1000>,
<0x1e000100 0x100>;
};
L2: cache-controller@1e00a000 {
compatible = "arm,pl310-cache";
reg = <0x1e00a000 0x1000>;
interrupts = <0 43 4>;
cache-unified;
cache-level = <2>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0: extsaxiclk {
/* ACLK clock to the AXI master port on the test chip */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <30000000 50000000>;
#clock-cells = <0>;
clock-output-names = "extsaxiclk";
};
oscclk1: clcdclk {
/* Reference clock for the CLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <10000000 80000000>;
#clock-cells = <0>;
clock-output-names = "clcdclk";
};
smbclk: oscclk2: tcrefclk {
/* Reference clock for the test chip internal PLLs */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <33000000 100000000>;
#clock-cells = <0>;
clock-output-names = "tcrefclk";
};
volt-vd10 {
/* Test Chip internal logic voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "VD10";
regulator-always-on;
label = "VD10";
};
volt-vd10-s2 {
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
regulator-name = "VD10_S2";
regulator-always-on;
label = "VD10_S2";
};
volt-vd10-s3 {
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 2>;
regulator-name = "VD10_S3";
regulator-always-on;
label = "VD10_S3";
};
volt-vcc1v8 {
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 3>;
regulator-name = "VCC1V8";
regulator-always-on;
label = "VCC1V8";
};
volt-ddr2vtt {
/* DDR2 SDRAM VTT termination voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 4>;
regulator-name = "DDR2VTT";
regulator-always-on;
label = "DDR2VTT";
};
volt-vcc3v3 {
/* Local board supply for miscellaneous logic external to the Test Chip */
arm,vexpress-sysreg,func = <2 5>;
compatible = "arm,vexpress-volt";
regulator-name = "VCC3V3";
regulator-always-on;
label = "VCC3V3";
};
amp-vd10-s2 {
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
compatible = "arm,vexpress-amp";
arm,vexpress-sysreg,func = <3 0>;
label = "VD10_S2";
};
amp-vd10-s3 {
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
compatible = "arm,vexpress-amp";
arm,vexpress-sysreg,func = <3 1>;
label = "VD10_S3";
};
power-vd10-s2 {
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
compatible = "arm,vexpress-power";
arm,vexpress-sysreg,func = <12 0>;
label = "PVD10_S2";
};
power-vd10-s3 {
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
compatible = "arm,vexpress-power";
arm,vexpress-sysreg,func = <12 1>;
label = "PVD10_S3";
};
};
smb: smb@4000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x40000000 0x04000000>,
<1 0 0x44000000 0x04000000>,
<2 0 0x48000000 0x04000000>,
<3 0 0x4c000000 0x04000000>,
<7 0 0x10000000 0x00020000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
};
site2: hsb@e0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe0000000 0x20000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 3>;
interrupt-map = <0 0 &gic 0 36 4>,
<0 1 &gic 0 37 4>,
<0 2 &gic 0 38 4>,
<0 3 &gic 0 39 4>;
};
};

31
arch/arm/include/asm/arch-s32v234/clock.h
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@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_BUS_CLK,
MXC_PERIPHERALS_CLK,
MXC_UART_CLK,
MXC_USDHC_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
};
enum pll_type {
ARM_PLL = 0,
PERIPH_PLL,
ENET_PLL,
DDR_PLL,
VIDEO_PLL,
};
unsigned int mxc_get_clock(enum mxc_clock clk);
void clock_init(void);
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
#endif /* __ASM_ARCH_CLOCK_H */

156
arch/arm/include/asm/arch-s32v234/ddr.h
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@ -1,156 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
#define __ARCH_ARM_MACH_S32V234_DDR_H__
#define DDR0 0
#define DDR1 1
/* DDR offset in MSCR register */
#define _DDR0_RESET 168
#define _DDR0_CLK0 169
#define _DDR0_CAS 170
#define _DDR0_RAS 171
#define _DDR0_WE_B 172
#define _DDR0_CKE0 173
#define _DDR0_CKE1 174
#define _DDR0_CS_B0 175
#define _DDR0_CS_B1 176
#define _DDR0_BA0 177
#define _DDR0_BA1 178
#define _DDR0_BA2 179
#define _DDR0_A0 180
#define _DDR0_A1 181
#define _DDR0_A2 182
#define _DDR0_A3 183
#define _DDR0_A4 184
#define _DDR0_A5 185
#define _DDR0_A6 186
#define _DDR0_A7 187
#define _DDR0_A8 188
#define _DDR0_A9 189
#define _DDR0_A10 190
#define _DDR0_A11 191
#define _DDR0_A12 192
#define _DDR0_A13 193
#define _DDR0_A14 194
#define _DDR0_A15 195
#define _DDR0_DM0 196
#define _DDR0_DM1 197
#define _DDR0_DM2 198
#define _DDR0_DM3 199
#define _DDR0_DQS0 200
#define _DDR0_DQS1 201
#define _DDR0_DQS2 202
#define _DDR0_DQS3 203
#define _DDR0_D0 204
#define _DDR0_D1 205
#define _DDR0_D2 206
#define _DDR0_D3 207
#define _DDR0_D4 208
#define _DDR0_D5 209
#define _DDR0_D6 210
#define _DDR0_D7 211
#define _DDR0_D8 212
#define _DDR0_D9 213
#define _DDR0_D10 214
#define _DDR0_D11 215
#define _DDR0_D12 216
#define _DDR0_D13 217
#define _DDR0_D14 218
#define _DDR0_D15 219
#define _DDR0_D16 220
#define _DDR0_D17 221
#define _DDR0_D18 222
#define _DDR0_D19 223
#define _DDR0_D20 224
#define _DDR0_D21 225
#define _DDR0_D22 226
#define _DDR0_D23 227
#define _DDR0_D24 228
#define _DDR0_D25 229
#define _DDR0_D26 230
#define _DDR0_D27 231
#define _DDR0_D28 232
#define _DDR0_D29 233
#define _DDR0_D30 234
#define _DDR0_D31 235
#define _DDR0_ODT0 236
#define _DDR0_ODT1 237
#define _DDR0_ZQ 238
#define _DDR1_RESET 239
#define _DDR1_CLK0 240
#define _DDR1_CAS 241
#define _DDR1_RAS 242
#define _DDR1_WE_B 243
#define _DDR1_CKE0 244
#define _DDR1_CKE1 245
#define _DDR1_CS_B0 246
#define _DDR1_CS_B1 247
#define _DDR1_BA0 248
#define _DDR1_BA1 249
#define _DDR1_BA2 250
#define _DDR1_A0 251
#define _DDR1_A1 252
#define _DDR1_A2 253
#define _DDR1_A3 254
#define _DDR1_A4 255
#define _DDR1_A5 256
#define _DDR1_A6 257
#define _DDR1_A7 258
#define _DDR1_A8 259
#define _DDR1_A9 260
#define _DDR1_A10 261
#define _DDR1_A11 262
#define _DDR1_A12 263
#define _DDR1_A13 264
#define _DDR1_A14 265
#define _DDR1_A15 266
#define _DDR1_DM0 267
#define _DDR1_DM1 268
#define _DDR1_DM2 269
#define _DDR1_DM3 270
#define _DDR1_DQS0 271
#define _DDR1_DQS1 272
#define _DDR1_DQS2 273
#define _DDR1_DQS3 274
#define _DDR1_D0 275
#define _DDR1_D1 276
#define _DDR1_D2 277
#define _DDR1_D3 278
#define _DDR1_D4 279
#define _DDR1_D5 280
#define _DDR1_D6 281
#define _DDR1_D7 282
#define _DDR1_D8 283
#define _DDR1_D9 284
#define _DDR1_D10 285
#define _DDR1_D11 286
#define _DDR1_D12 287
#define _DDR1_D13 288
#define _DDR1_D14 289
#define _DDR1_D15 290
#define _DDR1_D16 291
#define _DDR1_D17 292
#define _DDR1_D18 293
#define _DDR1_D19 294
#define _DDR1_D20 295
#define _DDR1_D21 296
#define _DDR1_D22 297
#define _DDR1_D23 298
#define _DDR1_D24 299
#define _DDR1_D25 300
#define _DDR1_D26 301
#define _DDR1_D27 302
#define _DDR1_D28 303
#define _DDR1_D29 304
#define _DDR1_D30 305
#define _DDR1_D31 306
#define _DDR1_ODT0 307
#define _DDR1_ODT1 308
#define _DDR1_ZQ 309
#endif

328
arch/arm/include/asm/arch-s32v234/imx-regs.h
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@ -1,328 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ASM_ARCH_IMX_REGS_H__
#define __ASM_ARCH_IMX_REGS_H__
#define ARCH_MXC
#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
#define IRAM_SIZE 0x00400000 /* 4MB */
#define AIPS0_BASE_ADDR (0x40000000UL)
#define AIPS1_BASE_ADDR (0x40080000UL)
/* AIPS 0 */
#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000)
#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000)
#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000)
#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000)
#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000)
#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000)
#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000)
#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000)
#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000)
#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000)
#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000)
#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000)
#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000)
#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000)
#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000)
#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000)
#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000)
#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000)
#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000)
#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000)
#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000)
#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000)
#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000)
#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000)
/* AIPS 1 */
#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000)
#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000)
#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000)
#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000)
#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000)
#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000)
#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000)
#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000)
#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000)
#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000)
#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000)
#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000)
#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000)
#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000)
#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000)
#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000)
#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000)
#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000)
#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000)
#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000)
#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000)
#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000)
#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000)
#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000)
#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000)
#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000)
#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000)
#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000)
#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000)
#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000)
#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000)
#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000)
#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000)
#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000)
/* TODO Remove this after the IOMUX framework is implemented */
#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
/* MUX mode and PAD ctrl are in one register */
#define CONFIG_IOMUX_SHARE_CONF_REG
#define FEC_QUIRK_ENET_MAC
#define I2C_QUIRK_REG
/* MSCM interrupt router */
#define MSCM_IRSPRC_CPn_EN 3
#define MSCM_IRSPRC_NUM 176
#define MSCM_CPXTYPE_RYPZ_MASK 0xFF
#define MSCM_CPXTYPE_RYPZ_OFFSET 0
#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00
#define MSCM_CPXTYPE_PERS_OFFSET 8
#define MSCM_CPXTYPE_PERS_A53 0x413533
#define MSCM_CPXTYPE_PERS_CM4 0x434d34
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
/* System Reset Controller (SRC) */
struct src {
u32 bmr1;
u32 bmr2;
u32 gpr1_boot;
u32 reserved_0x00C[61];
u32 gpr1;
u32 gpr2;
u32 gpr3;
u32 gpr4;
u32 gpr5;
u32 gpr6;
u32 gpr7;
u32 reserved_0x11C[1];
u32 gpr9;
u32 gpr10;
u32 gpr11;
u32 gpr12;
u32 gpr13;
u32 gpr14;
u32 gpr15;
u32 gpr16;
u32 reserved_0x140[1];
u32 gpr17;
u32 gpr18;
u32 gpr19;
u32 gpr20;
u32 gpr21;
u32 gpr22;
u32 gpr23;
u32 gpr24;
u32 gpr25;
u32 gpr26;
u32 gpr27;
u32 reserved_0x16C[5];
u32 pcie_config1;
u32 ddr_self_ref_ctrl;
u32 pcie_config0;
u32 reserved_0x18C[4];
u32 soc_misc_config2;
};
/* SRC registers definitions */
/* SRC_GPR1 */
#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
(SRC_GPR1_PLL_OFFSET + (pll)) )
#define SRC_GPR1_PLL_SOURCE_MASK (0x1)
#define SRC_GPR1_PLL_OFFSET (27)
#define SRC_GPR1_FIRC_CLK_SOURCE (0x0)
#define SRC_GPR1_XOSC_CLK_SOURCE (0x1)
/* Periodic Interrupt Timer (PIT) */
struct pit_reg {
u32 mcr;
u32 recv0[55];
u32 ltmr64h;
u32 ltmr64l;
u32 recv1[6];
u32 ldval0;
u32 cval0;
u32 tctrl0;
u32 tflg0;
u32 ldval1;
u32 cval1;
u32 tctrl1;
u32 tflg1;
u32 ldval2;
u32 cval2;
u32 tctrl2;
u32 tflg2;
u32 ldval3;
u32 cval3;
u32 tctrl3;
u32 tflg3;
u32 ldval4;
u32 cval4;
u32 tctrl4;
u32 tflg4;
u32 ldval5;
u32 cval5;
u32 tctrl5;
u32 tflg5;
};
/* Watchdog Timer (WDOG) */
struct wdog_regs {
u32 cr;
u32 ir;
u32 to;
u32 wn;
u32 sr;
u32 co;
u32 sk;
};
/* UART */
struct linflex_fsl {
u32 lincr1;
u32 linier;
u32 linsr;
u32 linesr;
u32 uartcr;
u32 uartsr;
u32 lintcsr;
u32 linocr;
u32 lintocr;
u32 linfbrr;
u32 linibrr;
u32 lincfr;
u32 lincr2;
u32 bidr;
u32 bdrl;
u32 bdrm;
u32 ifer;
u32 ifmi;
u32 ifmr;
u32 ifcr0;
u32 ifcr1;
u32 ifcr2;
u32 ifcr3;
u32 ifcr4;
u32 ifcr5;
u32 ifcr6;
u32 ifcr7;
u32 ifcr8;
u32 ifcr9;
u32 ifcr10;
u32 ifcr11;
u32 ifcr12;
u32 ifcr13;
u32 ifcr14;
u32 ifcr15;
u32 gcr;
u32 uartpto;
u32 uartcto;
u32 dmatxe;
u32 dmarxe;
};
/* MSCM Interrupt Router */
struct mscm_ir {
u32 cpxtype; /* Processor x Type Register */
u32 cpxnum; /* Processor x Number Register */
u32 cpxmaster; /* Processor x Master Number Register */
u32 cpxcount; /* Processor x Count Register */
u32 cpxcfg0; /* Processor x Configuration 0 Register */
u32 cpxcfg1; /* Processor x Configuration 1 Register */
u32 cpxcfg2; /* Processor x Configuration 2 Register */
u32 cpxcfg3; /* Processor x Configuration 3 Register */
u32 cp0type; /* Processor 0 Type Register */
u32 cp0num; /* Processor 0 Number Register */
u32 cp0master; /* Processor 0 Master Number Register */
u32 cp0count; /* Processor 0 Count Register */
u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
u32 cp1type; /* Processor 1 Type Register */
u32 cp1num; /* Processor 1 Number Register */
u32 cp1master; /* Processor 1 Master Number Register */
u32 cp1count; /* Processor 1 Count Register */
u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
u32 reserved_0x060[232];
u32 ocmdr0; /* On-Chip Memory Descriptor Register */
u32 reserved_0x404[2];
u32 ocmdr3; /* On-Chip Memory Descriptor Register */
u32 reserved_0x410[28];
u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
u32 reserved_0x490[28];
u32 cpce0; /* Core Parity Checking Enable Register 0 */
u32 reserved_0x504[191];
u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
u32 reserved_0x808[6];
u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
u32 reserved_0x824[23];
u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
u32 reserved_0x9e0[136];
u32 iahbbe0; /* Gasket Burst Enable Register */
u32 reserved_0xc04[63];
u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
u32 reserved_0xd04[3];
u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
u32 reserved_0xd20[8];
u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
u32 reserved_0xd44[3];
u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IMX_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/lpddr2.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
/* definitions for LPDDR2 PAD values */
#define LPDDR2_CLK0_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \
SIUL2_MSCR_DCYCLE_TRIM_NONE)
#define LPDDR2_CKEn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
#define LPDDR2_CS_Bn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
#define LPDDR2_DMn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
#define LPDDR2_DQSn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \
SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
#define LPDDR2_An_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
SIUL2_MSCR_PUS_100K_UP)
#define LPDDR2_Dn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
SIUL2_MSCR_PUS_100K_UP)
#define _MDCTL 0x03010000
#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */
#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */
#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */
#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */
#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */
#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */
#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */
#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */
#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */
#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */
#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */
#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */
#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */
#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */
#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */
#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */
#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */
/* set I/O pads for DDR */
void lpddr2_config_iomux(uint8_t module);
void config_mmdc(uint8_t module);
#endif

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arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
#ifndef __ASSEMBLY__
/* MC_CGM registers definitions */
/* MC_CGM_SC_SS */
#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) )
#define MC_CGM_SC_SEL_FIRC (0x0)
#define MC_CGM_SC_SEL_XOSC (0x1)
#define MC_CGM_SC_SEL_ARMPLL (0x2)
#define MC_CGM_SC_SEL_CLKDISABLE (0xF)
/* MC_CGM_SC_DCn */
#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000)
#define MC_CGM_SC_DCn_PREDIV_OFFSET (16)
#define MC_CGM_SC_DCn_DE (1 << 31)
#define MC_CGM_SC_SEL_MASK (0x0F000000)
#define MC_CGM_SC_SEL_OFFSET (24)
/* MC_CGM_ACn_DCm */
#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
/*
* MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
* that the 5th bit is always ignored during writes if the current
* MC_CGM_ACn_DCm_PREDIV field has only 4 bits
*
* The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
*
* This should be changed if any problems occur.
*/
#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000)
#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16)
#define MC_CGM_ACn_DCm_DE (1 << 31)
/*
* MC_CGM_ACn_SC/MC_CGM_ACn_SS
*/
#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20))
#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20))
#define MC_CGM_ACn_SEL_MASK (0x07000000)
#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
#define MC_CGM_ACn_SEL_OFFSET (24)
#define MC_CGM_ACn_SEL_FIRC (0x0)
#define MC_CGM_ACn_SEL_XOSC (0x1)
#define MC_CGM_ACn_SEL_ARMPLL (0x2)
/*
* According to the manual some PLL can be divided by X (X={1,3,5}):
* PERPLLDIVX, VIDEOPLLDIVX.
*/
#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3)
#define MC_CGM_ACn_SEL_ENETPLL (0x4)
#define MC_CGM_ACn_SEL_DDRPLL (0x5)
#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7)
#define MC_CGM_ACn_SEL_SYSCLK (0x8)
#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9)
#define MC_CGM_ACn_SEL_PERCLK (0xA)
/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div))
#define PLLDIG_PLLDV_MFD_MASK (0x000000FF)
/*
* PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
* the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
*/
#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000)
#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F)
#define PLLDIG_PLLDV_RFDPHI_OFFSET (16)
#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000)
#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F)
#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25)
#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000)
#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7)
#define PLLDIG_PLLDV_PREDIV_OFFSET (12)
/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */
#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val))
#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF)
#define PLLDIG_PLLFD_SMDEN (1 << 30)
/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24)
#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000)
/* Digital Frequency Synthesizer (DFS) */
/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040)
/* DFS DLL Program Register 1 */
#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
#define DFS_DLLPRG1_V2IGC_OFFSET (0)
#define DFS_DLLPRG1_V2IGC_MASK (0x00000007)
#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
#define DFS_DLLPRG1_LCKWT_OFFSET (4)
#define DFS_DLLPRG1_LCKWT_MASK (0x00000030)
#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
#define DFS_DLLPRG1_DACIN_OFFSET (6)
#define DFS_DLLPRG1_DACIN_MASK (0x000001C0)
#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
#define DFS_DLLPRG1_CALBYPEN_OFFSET (9)
#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200)
#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10)
#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00)
#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
#define DFS_DLLPRG1_CPICTRL_OFFSET (12)
#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000)
/* DFS Control Register (DFS_CTRL) */
#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
#define DFS_CTRL_DLL_LOLIE (1 << 0)
#define DFS_CTRL_DLL_RESET (1 << 1)
/* DFS Port Status Register (DFS_PORTSR) */
#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
/* DFS Port Reset Register (DFS_PORTRESET) */
#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF)
#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F)
#define DFS_PORTRESET_PORTRESET_OFFSET (0)
/* DFS Divide Register Portn (DFS_DVPORTn) */
#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
/*
* The mathematical formula for fdfs_clockout is the following:
* fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
*/
#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
#define DFS_DVPORTn_MFI_MASK (0x0000FF00)
#define DFS_DVPORTn_MFN_MASK (0x000000FF)
#define DFS_DVPORTn_MFI_MAXVAL (0xFF)
#define DFS_DVPORTn_MFN_MAXVAL (0xFF)
#define DFS_DVPORTn_MFI_OFFSET (8)
#define DFS_DVPORTn_MFN_OFFSET (0)
#define DFS_MAXNUMBER (4)
#define DFS_PARAMS_Nr (3)
/* Frequencies are in Hz */
#define FIRC_CLK_FREQ (48000000)
#define XOSC_CLK_FREQ (40000000)
#define PLL_MIN_FREQ (650000000)
#define PLL_MAX_FREQ (1300000000)
#define ARM_PLL_PHI0_FREQ (1000000000)
#define ARM_PLL_PHI1_FREQ (1000000000)
/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
#define ARM_PLL_PHI1_DFS1_EN (1)
#define ARM_PLL_PHI1_DFS1_MFI (3)
#define ARM_PLL_PHI1_DFS1_MFN (194)
/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
#define ARM_PLL_PHI1_DFS2_EN (1)
#define ARM_PLL_PHI1_DFS2_MFI (1)
#define ARM_PLL_PHI1_DFS2_MFN (170)
/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
#define ARM_PLL_PHI1_DFS3_EN (1)
#define ARM_PLL_PHI1_DFS3_MFI (1)
#define ARM_PLL_PHI1_DFS3_MFN (170)
#define ARM_PLL_PHI1_DFS_Nr (3)
#define ARM_PLL_PLLDV_PREDIV (2)
#define ARM_PLL_PLLDV_MFD (50)
#define ARM_PLL_PLLDV_MFN (0)
#define PERIPH_PLL_PHI0_FREQ (400000000)
#define PERIPH_PLL_PHI1_FREQ (100000000)
#define PERIPH_PLL_PHI1_DFS_Nr (0)
#define PERIPH_PLL_PLLDV_PREDIV (1)
#define PERIPH_PLL_PLLDV_MFD (30)
#define PERIPH_PLL_PLLDV_MFN (0)
#define ENET_PLL_PHI0_FREQ (500000000)
#define ENET_PLL_PHI1_FREQ (1000000000)
/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
#define ENET_PLL_PHI1_DFS1_EN (1)
#define ENET_PLL_PHI1_DFS1_MFI (2)
#define ENET_PLL_PHI1_DFS1_MFN (219)
/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
#define ENET_PLL_PHI1_DFS2_EN (1)
#define ENET_PLL_PHI1_DFS2_MFI (2)
#define ENET_PLL_PHI1_DFS2_MFN (219)
/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
#define ENET_PLL_PHI1_DFS3_EN (1)
#define ENET_PLL_PHI1_DFS3_MFI (3)
#define ENET_PLL_PHI1_DFS3_MFN (32)
/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
#define ENET_PLL_PHI1_DFS4_EN (1)
#define ENET_PLL_PHI1_DFS4_MFI (2)
#define ENET_PLL_PHI1_DFS4_MFN (0)
#define ENET_PLL_PHI1_DFS_Nr (4)
#define ENET_PLL_PLLDV_PREDIV (2)
#define ENET_PLL_PLLDV_MFD (50)
#define ENET_PLL_PLLDV_MFN (0)
#define DDR_PLL_PHI0_FREQ (533000000)
#define DDR_PLL_PHI1_FREQ (1066000000)
/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
#define DDR_PLL_PHI1_DFS1_EN (1)
#define DDR_PLL_PHI1_DFS1_MFI (2)
#define DDR_PLL_PHI1_DFS1_MFN (33)
/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
#define DDR_PLL_PHI1_DFS2_EN (1)
#define DDR_PLL_PHI1_DFS2_MFI (2)
#define DDR_PLL_PHI1_DFS2_MFN (33)
/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
#define DDR_PLL_PHI1_DFS3_EN (1)
#define DDR_PLL_PHI1_DFS3_MFI (3)
#define DDR_PLL_PHI1_DFS3_MFN (11)
#define DDR_PLL_PHI1_DFS_Nr (3)
#define DDR_PLL_PLLDV_PREDIV (2)
#define DDR_PLL_PLLDV_MFD (53)
#define DDR_PLL_PLLDV_MFN (6144)
#define VIDEO_PLL_PHI0_FREQ (600000000)
#define VIDEO_PLL_PHI1_FREQ (0)
#define VIDEO_PLL_PHI1_DFS_Nr (0)
#define VIDEO_PLL_PLLDV_PREDIV (1)
#define VIDEO_PLL_PLLDV_MFD (30)
#define VIDEO_PLL_PLLDV_MFN (0)
#endif
#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/mc_me_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
#ifndef __ASSEMBLY__
/* MC_ME registers definitions */
/* MC_ME_GS */
#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000)
#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0)
#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0)
#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0)
#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0)
#define MC_ME_GS_S_FIRC (1 << 4)
#define MC_ME_GS_S_XOSC (1 << 5)
#define MC_ME_GS_S_ARMPLL (1 << 6)
#define MC_ME_GS_S_PERPLL (1 << 7)
#define MC_ME_GS_S_ENETPLL (1 << 8)
#define MC_ME_GS_S_DDRPLL (1 << 9)
#define MC_ME_GS_S_VIDEOPLL (1 << 10)
#define MC_ME_GS_S_MVR (1 << 20)
#define MC_ME_GS_S_PDO (1 << 23)
#define MC_ME_GS_S_MTRANS (1 << 27)
#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28)
#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28)
#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28)
/* MC_ME_MCTL */
#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004)
#define MC_ME_MCTL_KEY (0x00005AF0)
#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F)
#define MC_ME_MCTL_RESET (0x0 << 28)
#define MC_ME_MCTL_TEST (0x1 << 28)
#define MC_ME_MCTL_DRUN (0x3 << 28)
#define MC_ME_MCTL_RUN0 (0x4 << 28)
#define MC_ME_MCTL_RUN1 (0x5 << 28)
#define MC_ME_MCTL_RUN2 (0x6 << 28)
#define MC_ME_MCTL_RUN3 (0x7 << 28)
/* MC_ME_ME */
#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008)
#define MC_ME_ME_RESET_FUNC (1 << 0)
#define MC_ME_ME_TEST (1 << 1)
#define MC_ME_ME_DRUN (1 << 3)
#define MC_ME_ME_RUN0 (1 << 4)
#define MC_ME_ME_RUN1 (1 << 5)
#define MC_ME_ME_RUN2 (1 << 6)
#define MC_ME_ME_RUN3 (1 << 7)
/* MC_ME_RUN_PCn */
#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
#define MC_ME_RUN_PCn_RESET (1 << 0)
#define MC_ME_RUN_PCn_TEST (1 << 1)
#define MC_ME_RUN_PCn_DRUN (1 << 3)
#define MC_ME_RUN_PCn_RUN0 (1 << 4)
#define MC_ME_RUN_PCn_RUN1 (1 << 5)
#define MC_ME_RUN_PCn_RUN2 (1 << 6)
#define MC_ME_RUN_PCn_RUN3 (1 << 7)
/*
* MC_ME_RESET_MC/MC_ME_TEST_MC
* MC_ME_DRUN_MC
* MC_ME_RUNn_MC
*/
#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020)
#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024)
#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C)
#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F)
#define MC_ME_RUNMODE_MC_FIRCON (1 << 4)
#define MC_ME_RUNMODE_MC_XOSCON (1 << 5)
#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll)))
#define MC_ME_RUNMODE_MC_MVRON (1 << 20)
#define MC_ME_RUNMODE_MC_PDO (1 << 23)
#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28)
#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29)
#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30)
/* MC_ME_DRUN_SEC_CC_I */
#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260)
/* MC_ME_RUNn_SEC_CC_I */
#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3)
/*
* ME_PCTLn
* Please note that these registers are 8 bits width, so
* the operations over them should be done using 8 bits operations.
*/
#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK )
#define MC_ME_PCTLn_RUNPCm_MASK (0x7)
/* DEC200 Peripheral Control Register */
#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4)
/* 2D-ACE Peripheral Control Register */
#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB)
/* ENET Peripheral Control Register */
#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1)
/* DMACHMUX0 Peripheral Control Register */
#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2)
/* CSI0 Peripheral Control Register */
#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3)
/* MMDC0 Peripheral Control Register */
#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5)
/* FRAY Peripheral Control Register */
#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7)
/* PIT0 Peripheral Control Register */
#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9)
/* FlexTIMER0 Peripheral Control Register */
#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C)
/* SARADC0 Peripheral Control Register */
#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E)
/* LINFLEX0 Peripheral Control Register */
#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110)
/* IIC0 Peripheral Control Register */
#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112)
/* DSPI0 Peripheral Control Register */
#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114)
/* CANFD0 Peripheral Control Register */
#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116)
/* CRC0 Peripheral Control Register */
#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118)
/* DSPI2 Peripheral Control Register */
#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A)
/* SDHC Peripheral Control Register */
#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E)
/* VIU0 Peripheral Control Register */
#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127)
/* HPSMI Peripheral Control Register */
#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B)
/* SIPI Peripheral Control Register */
#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137)
/* LFAST Peripheral Control Register */
#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B)
/* MMDC1 Peripheral Control Register */
#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161)
/* DMACHMUX1 Peripheral Control Register */
#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162)
/* CSI1 Peripheral Control Register */
#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163)
/* QUADSPI0 Peripheral Control Register */
#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165)
/* PIT1 Peripheral Control Register */
#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169)
/* FlexTIMER1 Peripheral Control Register */
#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175)
/* IIC2 Peripheral Control Register */
#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179)
/* IIC1 Peripheral Control Register */
#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B)
/* CANFD1 Peripheral Control Register */
#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D)
/* LINFLEX1 Peripheral Control Register */
#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F)
/* DSPI3 Peripheral Control Register */
#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181)
/* DSPI1 Peripheral Control Register */
#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183)
/* TSENS Peripheral Control Register */
#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D)
/* CRC1 Peripheral Control Register */
#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F)
/* VIU1 Peripheral Control Register */
#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193)
/* JPEG Peripheral Control Register */
#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197)
/* H264_DEC Peripheral Control Register */
#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B)
/* H264_ENC Peripheral Control Register */
#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F)
/* MBIST Peripheral Control Register */
#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9)
/* Core status register */
#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0)
#endif
#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
#define MC_RGM_DES (MC_RGM_BASE_ADDR)
#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
/* function reset sources mask */
#define F_SWT4 0x8000
#define F_JTAG 0x400
#define F_FCCU_SOFT 0x40
#define F_FCCU_HARD 0x20
#define F_SOFT_FUNC 0x8
#define F_ST_DONE 0x4
#define F_EXT_RST 0x1
#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/mmdc.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
#define __ARCH_ARM_MACH_S32V234_MMDC_H__
#define MMDC0 0
#define MMDC1 1
#define MMDC_MDCTL 0x0
#define MMDC_MDPDC 0x4
#define MMDC_MDOTC 0x8
#define MMDC_MDCFG0 0xC
#define MMDC_MDCFG1 0x10
#define MMDC_MDCFG2 0x14
#define MMDC_MDMISC 0x18
#define MMDC_MDSCR 0x1C
#define MMDC_MDREF 0x20
#define MMDC_MDRWD 0x2C
#define MMDC_MDOR 0x30
#define MMDC_MDMRR 0x34
#define MMDC_MDCFG3LP 0x38
#define MMDC_MDMR4 0x3C
#define MMDC_MDASP 0x40
#define MMDC_MAARCR 0x400
#define MMDC_MAPSR 0x404
#define MMDC_MAEXIDR0 0x408
#define MMDC_MAEXIDR1 0x40C
#define MMDC_MADPCR0 0x410
#define MMDC_MADPCR1 0x414
#define MMDC_MADPSR0 0x418
#define MMDC_MADPSR1 0x41C
#define MMDC_MADPSR2 0x420
#define MMDC_MADPSR3 0x424
#define MMDC_MADPSR4 0x428
#define MMDC_MADPSR5 0x42C
#define MMDC_MASBS0 0x430
#define MMDC_MASBS1 0x434
#define MMDC_MAGENP 0x440
#define MMDC_MPZQHWCTRL 0x800
#define MMDC_MPWLGCR 0x808
#define MMDC_MPWLDECTRL0 0x80C
#define MMDC_MPWLDECTRL1 0x810
#define MMDC_MPWLDLST 0x814
#define MMDC_MPODTCTRL 0x818
#define MMDC_MPRDDQBY0DL 0x81C
#define MMDC_MPRDDQBY1DL 0x820
#define MMDC_MPRDDQBY2DL 0x824
#define MMDC_MPRDDQBY3DL 0x828
#define MMDC_MPDGCTRL0 0x83C
#define MMDC_MPDGCTRL1 0x840
#define MMDC_MPDGDLST0 0x844
#define MMDC_MPRDDLCTL 0x848
#define MMDC_MPRDDLST 0x84C
#define MMDC_MPWRDLCTL 0x850
#define MMDC_MPWRDLST 0x854
#define MMDC_MPZQLP2CTL 0x85C
#define MMDC_MPRDDLHWCTL 0x860
#define MMDC_MPWRDLHWCTL 0x864
#define MMDC_MPRDDLHWST0 0x868
#define MMDC_MPRDDLHWST1 0x86C
#define MMDC_MPWRDLHWST1 0x870
#define MMDC_MPWRDLHWST2 0x874
#define MMDC_MPWLHWERR 0x878
#define MMDC_MPDGHWST0 0x87C
#define MMDC_MPDGHWST1 0x880
#define MMDC_MPDGHWST2 0x884
#define MMDC_MPDGHWST3 0x888
#define MMDC_MPPDCMPR1 0x88C
#define MMDC_MPPDCMPR2 0x890
#define MMDC_MPSWDAR0 0x894
#define MMDC_MPSWDRDR0 0x898
#define MMDC_MPSWDRDR1 0x89C
#define MMDC_MPSWDRDR2 0x8A0
#define MMDC_MPSWDRDR3 0x8A4
#define MMDC_MPSWDRDR4 0x8A8
#define MMDC_MPSWDRDR5 0x8AC
#define MMDC_MPSWDRDR6 0x8B0
#define MMDC_MPSWDRDR7 0x8B4
#define MMDC_MPMUR0 0x8B8
#define MMDC_MPDCCR 0x8C0
#define MMDC_MPMUR0_FRC_MSR (1 << 11)
#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16)
#endif

149
arch/arm/include/asm/arch-s32v234/siul.h
View file

@ -1,149 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
#define __ARCH_ARM_MACH_S32V234_SIUL_H__
#include "ddr.h"
#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i))
#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
/* SIUL2_MSCR specifications as stated in Reference Manual:
* 0 - 359 Output Multiplexed Signal Configuration Registers
* 512- 1023 Input Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240)
#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i))
#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40)
#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i))
#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300)
#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i))
#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500)
#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i))
#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700)
#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i))
#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740)
#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i))
#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780)
#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i))
/* SIUL2_MSCR masks */
#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000)
#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30)
#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30)
#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30)
#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30)
#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000)
#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29)
#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29)
#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000)
#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27)
#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27)
#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000)
#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24)
#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24)
#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24)
#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24)
#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24)
#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24)
#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24)
#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000)
#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22)
#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22)
#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22)
#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000)
#define SIUL2_MSCR_OBE_EN (1 << 21)
#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000)
#define SIUL2_MSCR_ODE_EN (1 << 20)
#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000)
#define SIUL2_MSCR_IBE_EN (1 << 19)
#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000)
#define SIUL2_MSCR_HYS_EN (1 << 18)
#define SIUL2_MSCR_INV(v) ((v) & 0x00020000)
#define SIUL2_MSCR_INV_EN (1 << 17)
#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000)
#define SIUL2_MSCR_PKE_EN (1 << 16)
#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000)
#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14)
#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14)
#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14)
#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14)
#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000)
#define SIUL2_MSCR_PUE_EN (1 << 13)
#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800)
#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11)
#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11)
#define SIUL2_MSCR_PUS_100K_UP (2 << 11)
#define SIUL2_MSCR_PUS_33K_UP (3 << 11)
#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700)
#define SIUL2_MSCR_DSE_240ohm (1 << 8)
#define SIUL2_MSCR_DSE_120ohm (2 << 8)
#define SIUL2_MSCR_DSE_80ohm (3 << 8)
#define SIUL2_MSCR_DSE_60ohm (4 << 8)
#define SIUL2_MSCR_DSE_48ohm (5 << 8)
#define SIUL2_MSCR_DSE_40ohm (6 << 8)
#define SIUL2_MSCR_DSE_34ohm (7 << 8)
#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0)
#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6)
#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020)
#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f)
#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1)
#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2)
#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3)
/* UART settings */
#define SIUL2_UART0_TXD_PAD 12
#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \
SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_UART0_MSCR_RXD_PAD 11
#define SIUL2_UART0_IMCR_RXD_PAD 200
#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2)
/* uSDHC settings */
#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \
SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */

21
arch/arm/mach-at91/Kconfig
View file

@ -134,11 +134,6 @@ config TARGET_PM9G45
bool "Ronetix pm9g45 board"
select AT91SAM9G45
config TARGET_PICOSAM9G45
bool "Mini-box picosam9g45 board"
select AT91SAM9M10G45
select SUPPORT_SPL
config TARGET_AT91SAM9N12EK
bool "Atmel AT91SAM9N12-EK board"
select AT91SAM9N12
@ -303,19 +298,6 @@ config TARGET_VINCO
select SUPPORT_SPL
imply CMD_DM
config TARGET_WB45N
bool "Support Laird WB45N"
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_WB50N
bool "Support Laird WB50N"
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select SUPPORT_SPL
select ATMEL_SFR
endchoice
config ATMEL_SFR
@ -351,15 +333,12 @@ source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/gardena/smart-gateway-at91sam/Kconfig"
source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
source "board/laird/wb45n/Kconfig"
source "board/laird/wb50n/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS

11
arch/arm/mach-imx/mx5/Kconfig
View file

@ -52,11 +52,6 @@ config TARGET_MX53CX9020
select MX53
imply CMD_DM
config TARGET_MX53EVK
bool "Support mx53evk"
select BOARD_LATE_INIT
select MX53
config TARGET_MX53LOCO
bool "Support mx53loco"
select BOARD_LATE_INIT
@ -68,10 +63,6 @@ config TARGET_MX53PPD
help
Enable support for the GE Healthcare PPD.
config TARGET_TS4800
bool "Support TS4800"
select MX51
config TARGET_USBARMORY
bool "Support USB armory"
select MX53
@ -83,12 +74,10 @@ config SYS_SOC
source "board/beckhoff/mx53cx9020/Kconfig"
source "board/freescale/mx51evk/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/k+p/kp_imx53/Kconfig"
source "board/menlo/m53menlo/Kconfig"
source "board/technologic/ts4800/Kconfig"
endif

79
arch/arm/mach-imx/mx6/Kconfig
View file

@ -111,12 +111,6 @@ choice
prompt "MX6 board select"
optional
config TARGET_ADVANTECH_DMS_BA16
bool "Advantech dms-ba16"
depends on MX6Q
select BOARD_LATE_INIT
imply CMD_SATA
config TARGET_APALIS_IMX6
bool "Toradex Apalis iMX6 board"
depends on MX6Q
@ -150,15 +144,6 @@ config TARGET_ARISTAINETOS2CCSLB
imply CMD_SATA
imply CMD_DM
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
depends on MX6QDL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
config TARGET_CM_FX6
bool "CM-FX6"
depends on MX6QDL
@ -302,9 +287,6 @@ config TARGET_MX6MEMCAL
and characterize the memory layout of a new design during the initial
development and pre-production stages.
config TARGET_MX6QARM2
bool "mx6qarm2"
config TARGET_MX6DL_MAMOJ
bool "Support BTicino Mamoj"
depends on MX6QDL
@ -476,11 +458,6 @@ config TARGET_OPOS6ULDEV
depends on MX6UL
select MX6UL_OPOS6UL
config TARGET_OT1200
bool "Bachmann OT1200"
select SUPPORT_SPL
imply CMD_SATA
config TARGET_PICO_IMX6
bool "PICO-IMX6"
depends on MX6QDL
@ -504,14 +481,6 @@ config TARGET_LITEBOARD
select BOARD_LATE_INIT
select MX6UL_LITESOM
config TARGET_PLATINUM_PICON
bool "platinum-picon"
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
select SUPPORT_SPL
config TARGET_PCM058
bool "Phytec PCM058 i.MX6 Quad"
depends on MX6Q
@ -521,12 +490,6 @@ config TARGET_PCM058
select OF_CONTROL
imply CMD_DM
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
depends on MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_PCL063
bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
depends on MX6UL
@ -551,9 +514,6 @@ config TARGET_PCL063_ULL
select DM_THERMAL
select SUPPORT_SPL
config TARGET_SECOMX6
bool "secomx6 boards"
config TARGET_SOMLABS_VISIONSOM_6ULL
bool "visionsom-6ull"
depends on MX6ULL
@ -570,10 +530,6 @@ config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
depends on MX6Q
config TARGET_TITANIUM
bool "titanium"
depends on MX6Q
config TARGET_KP_IMX6Q_TPC
bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
depends on MX6QDL
@ -645,31 +601,6 @@ config TARGET_WARP
depends on MX6SL
select BOARD_LATE_INIT
config TARGET_XPRESS
bool "CCV xPress"
depends on MX6UL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
config TARGET_ZC5202
bool "zc5202"
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
config TARGET_ZC5601
bool "zc5601"
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
config TARGET_BRPPT2
bool "brppt2"
depends on MX6QDL
@ -695,23 +626,15 @@ config SYS_SOC
source "board/ge/bx50v3/Kconfig"
source "board/ge/b1x5v2/Kconfig"
source "board/advantech/dms-ba16/Kconfig"
source "board/aristainetos/Kconfig"
source "board/armadeus/opos6uldev/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/bticino/mamoj/Kconfig"
source "board/ccv/xpress/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6memcal/Kconfig"
source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
@ -723,7 +646,6 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pfla02/Kconfig"
source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
@ -731,7 +653,6 @@ source "board/softing/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"

13
arch/arm/mach-imx/mxs/Kconfig
View file

@ -16,9 +16,6 @@ config TARGET_MX23EVK
bool "Support mx23evk"
select BOARD_EARLY_INIT_F
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
config TARGET_XFI3
bool "Support xfi3"
@ -29,8 +26,6 @@ config SYS_SOC
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/creative/xfi3/Kconfig"
endif
@ -51,12 +46,6 @@ config TARGET_MX28EVK
bool "Support mx28evk"
select BOARD_EARLY_INIT_F
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
config TARGET_TS4600
bool "Support TS4600"
config TARGET_XEA
bool "Support XEA"
@ -68,7 +57,5 @@ config SYS_SOC
source "board/freescale/mx28evk/Kconfig"
source "board/liebherr/xea/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/technologic/ts4600/Kconfig"
endif

2
arch/arm/mach-kirkwood/include/mach/config.h
View file

@ -74,8 +74,6 @@
*/
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */

10
arch/arm/mach-omap2/omap3/Kconfig
View file

@ -89,18 +89,11 @@ config TARGET_OMAP3_OVERO
select OMAP3_GPIO_6
imply CMD_DM
config TARGET_AM3517_CRANE
bool "am3517_crane"
config TARGET_OMAP3_PANDORA
bool "OMAP3 Pandora"
select OMAP3_GPIO_4
select OMAP3_GPIO_6
config TARGET_TRICORDER
bool "Tricorder"
select OMAP3_GPIO_2
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
select BOARD_LATE_INIT
@ -166,11 +159,8 @@ source "board/ti/beagle/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/lg/sniper/Kconfig"
endif

4
arch/arm/mach-omap2/omap4/Kconfig
View file

@ -10,9 +10,6 @@ config TARGET_OMAP4_PANDA
config TARGET_OMAP4_SDP4430
bool "TI OMAP4 SDP4430"
config TARGET_KC1
bool "Amazon Kindle Fire (first generation)"
endchoice
config SYS_SOC
@ -20,6 +17,5 @@ config SYS_SOC
source "board/ti/panda/Kconfig"
source "board/ti/sdp4430/Kconfig"
source "board/amazon/kc1/Kconfig"
endif

30
arch/powerpc/cpu/mpc83xx/Kconfig
View file

@ -28,11 +28,6 @@ config TARGET_CADDY2
bool "Support caddy2"
select ARCH_MPC8349
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB_NOR
bool "Support MPC8313ERDB_NOR"
select ARCH_MPC8313
@ -75,18 +70,6 @@ config TARGET_MPC8349EMDS_SDRAM
select SYS_FSL_DDR_BE
select SYS_FSL_HAS_DDR2
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
select ARCH_MPC8349
imply CMD_IRQ
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
select ARCH_MPC837X
select BOARD_EARLY_INIT_F
imply CMD_SATA
imply FSL_SATA
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
select ARCH_MPC837X
@ -142,16 +125,6 @@ config TARGET_TQM834X
bool "Support TQM834x"
select ARCH_MPC8349
config TARGET_HRCON
bool "Support hrcon"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_PCA953X
config TARGET_GAZERBEAM
bool "Support gazerbeam"
@ -330,14 +303,11 @@ config FSL_ELBC
bool
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc8349itx/Kconfig"
source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"

106
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -210,14 +210,6 @@ config TARGET_T2080RDB
imply CMD_SATA
imply PANIC_HANG
config TARGET_T2081QDS
bool "Support T2081QDS"
select ARCH_T2081
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
config TARGET_T4160RDB
bool "Support T4160RDB"
select ARCH_T4160
@ -234,10 +226,6 @@ config TARGET_T4240RDB
imply CMD_SATA
imply PANIC_HANG
config TARGET_CONTROLCENTERD
bool "Support controlcenterd"
select ARCH_P1022
config TARGET_KMP204X
bool "Support kmp204x"
select VENDOR_KM
@ -266,18 +254,6 @@ config TARGET_UCP1020
imply CMD_SATA
imply PANIC_HANG
config TARGET_CYRUS_P5020
bool "Support Varisys Cyrus P5020"
select ARCH_P5020
select PHYS_64BIT
imply PANIC_HANG
config TARGET_CYRUS_P5040
bool "Support Varisys Cyrus P5040"
select ARCH_P5040
select PHYS_64BIT
imply PANIC_HANG
endchoice
config ARCH_B4420
@ -576,23 +552,6 @@ config ARCH_P1021
imply CMD_REGINFO
imply SATA_SIL
config ARCH_P1022
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_SATA_A001
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1023
bool
select FSL_LAW
@ -756,31 +715,6 @@ config ARCH_P4080
imply CMD_REGINFO
imply SATA_SIL
config ARCH_P5020
bool
select E500MC
select FSL_LAW
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A005275
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_DDR_A003
select SYS_FSL_ERRATUM_DDR_A003474
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_SRIO_A004034
select SYS_FSL_ERRATUM_USB14
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
imply FSL_SATA
config ARCH_P5040
bool
select E500MC
@ -928,29 +862,6 @@ config ARCH_T2080
imply CMD_REGINFO
imply FSL_SATA
config ARCH_T2081
bool
select E500MC
select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
imply CMD_NAND
imply CMD_REGINFO
config ARCH_T4160
bool
select E500MC
@ -1052,19 +963,16 @@ config MAX_CPUS
ARCH_P5040 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T2081
ARCH_T2080
default 2 if ARCH_B4420 || \
ARCH_BSC9132 || \
ARCH_MPC8572 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020 || \
ARCH_P5020 || \
ARCH_T1023 || \
ARCH_T1024
default 1
@ -1093,7 +1001,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
@ -1103,14 +1010,12 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
@ -1224,7 +1129,7 @@ config SYS_FSL_A004447_SVR_REV
default 0x00 if ARCH_MPC8548
default 0x10 if ARCH_P1010
default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
default 0x20 if ARCH_P3041 || ARCH_P4080
config SYS_FSL_ERRATUM_IFC_A002769
bool
@ -1294,10 +1199,8 @@ config SYS_FSL_NUM_LAWS
ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
default 16 if ARCH_T1023 || \
@ -1313,7 +1216,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
@ -1363,7 +1265,6 @@ config SYS_PPC_E500_DEBUG_TLB
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
@ -1404,7 +1305,6 @@ config SYS_FSL_LBC_CLK_DIV
default 2 if ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040
default 1
@ -1429,11 +1329,9 @@ source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
source "board/varisys/cyrus/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
source "board/xes/xpedite550x/Kconfig"

5
arch/powerpc/cpu/mpc85xx/Makefile
View file

@ -40,7 +40,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
@ -51,7 +50,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
obj-$(CONFIG_QE) += qe_io.o
@ -70,7 +68,6 @@ obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
@ -78,7 +75,6 @@ obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
@ -90,7 +86,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o

129
arch/powerpc/cpu/mpc85xx/p1022_serdes.c
View file

@ -1,129 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Author: Timur Tabi <timur@freescale.com>
*/
#include <config.h>
#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
#define SRDS2_MAX_LANES 2
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x00] = {NONE, NONE, NONE, NONE},
[0x01] = {NONE, NONE, NONE, NONE},
[0x02] = {NONE, NONE, NONE, NONE},
[0x03] = {NONE, NONE, NONE, NONE},
[0x04] = {NONE, NONE, NONE, NONE},
[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
[0x09] = {PCIE1, NONE, NONE, NONE},
[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
};
static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x00] = {PCIE3, PCIE3},
[0x01] = {PCIE2, PCIE3},
[0x02] = {SATA1, SATA2},
[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
[0x04] = {NONE, NONE},
[0x06] = {SATA1, SATA2},
[0x07] = {NONE, NONE},
[0x09] = {PCIE3, PCIE2},
[0x0a] = {SATA1, SATA2},
[0x0b] = {NONE, NONE},
[0x0d] = {PCIE3, PCIE2},
[0x0e] = {SATA1, SATA2},
[0x0f] = {NONE, NONE},
[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
[0x16] = {SATA1, SATA2},
[0x17] = {NONE, NONE},
[0x18] = {PCIE3, PCIE3},
[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
[0x1a] = {SATA1, SATA2},
[0x1b] = {NONE, NONE},
[0x1c] = {PCIE3, PCIE3},
[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
[0x1e] = {SATA1, SATA2},
[0x1f] = {NONE, NONE},
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret;
if (!(serdes1_prtcl_map & (1 << NONE)))
fsl_serdes_init();
ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
if (!(serdes2_prtcl_map & (1 << NONE)))
fsl_serdes_init();
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
if (serdes1_prtcl_map & (1 << NONE) &&
serdes2_prtcl_map & (1 << NONE))
return;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
/* Set the first bit to indicate serdes has been initialized */
serdes1_prtcl_map |= (1 << NONE);
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
/* Set the first bit to indicate serdes has been initialized */
serdes2_prtcl_map |= (1 << NONE);
}

124
arch/powerpc/cpu/mpc85xx/p5020_ids.c
View file

@ -1,124 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 0),
SET_QP_INFO(7, 8, 4, 1),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 0),
SET_QP_INFO(15, 16, 8, 1),
SET_QP_INFO(17, 18, 9, 0),
SET_QP_INFO(19, 20, 10, 1),
};
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_2(1, 199, 200),
SET_SRIO_LIODN_2(2, 201, 202),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(31),
SET_BMAN_LIODN(32),
#endif
SET_SDHC_LIODN(1, 64),
SET_PME_LIODN(117),
SET_USB_LIODN(1, "fsl-usb2-mph", 125),
SET_USB_LIODN(2, "fsl-usb2-dr", 126),
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct fman_liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 0, 10),
SET_FMAN_RX_1G_LIODN(1, 1, 11),
SET_FMAN_RX_1G_LIODN(1, 2, 12),
SET_FMAN_RX_1G_LIODN(1, 3, 13),
SET_FMAN_RX_1G_LIODN(1, 4, 14),
SET_FMAN_RX_10G_LIODN(1, 0, 15),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
SET_SEC_RTIC_LIODN_ENTRY(a, 154),
SET_SEC_RTIC_LIODN_ENTRY(b, 155),
SET_SEC_RTIC_LIODN_ENTRY(c, 156),
SET_SEC_RTIC_LIODN_ENTRY(d, 157),
SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
struct liodn_id_table raide_liodn_tbl[] = {
SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
};
int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
SET_RMAN_LIODN(0, 6),
SET_RMAN_LIODN(1, 7),
SET_RMAN_LIODN(2, 8),
SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
#endif
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
#endif
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
[FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47),
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
#endif
};

134
arch/powerpc/cpu/mpc85xx/p5020_serdes.c
View file

@ -1,134 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_serdes.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "fsl_corenet_serdes.h"
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
[0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
[0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
[0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
XAUI_FM1, XAUI_FM1, },
[0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4, },
[0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
SRIO1, },
[0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
[0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
NONE, NONE, },
[0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
SATA1, SATA2, },
[0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
XAUI_FM1, XAUI_FM1, },
[0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4, },
[0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
[0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
NONE, NONE, },
[0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
[0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
NONE, NONE, },
[0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
XAUI_FM1, XAUI_FM1, },
[0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
NONE, NONE, },
[0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
NONE, NONE, SATA1, SATA2, },
[0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
NONE, SATA1, SATA2, },
[0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
[0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
NONE, SATA1, SATA2, },
[0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
};
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
if (!serdes_lane_enabled(lane))
return NONE;
return serdes_cfg_tbl[cfg][lane];
}
int is_serdes_prtcl_valid(u32 prtcl) {
int i;
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
return 0;
}

7
arch/powerpc/cpu/mpc85xx/speed.c
View file

@ -127,7 +127,7 @@ void get_sys_info(sys_info_t *sys_info)
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
defined(CONFIG_ARCH_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
@ -198,7 +198,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
defined(CONFIG_ARCH_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
@ -608,8 +608,7 @@ int get_clocks(void)
* AN2919.
*/
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
defined(CONFIG_ARCH_P1022)
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*

4
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
View file

@ -160,7 +160,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{}
};
#ifndef CONFIG_ARCH_T2081
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@ -176,13 +175,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
{}
};
#endif
static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
#ifndef CONFIG_ARCH_T2081
serdes2_cfg_tbl,
#endif
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)

27
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -66,10 +66,6 @@
#define QE_NUM_OF_SNUM 28
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
@ -157,24 +153,6 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
@ -364,7 +342,7 @@
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
@ -381,9 +359,6 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 1

2
arch/powerpc/include/asm/fsl_secure_boot.h
View file

@ -25,7 +25,6 @@
defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
defined(CONFIG_TARGET_T1040QDS) || \
defined(CONFIG_TARGET_T1040RDB) || \
defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042RDB) || \
@ -58,7 +57,6 @@
#if defined(CONFIG_ARCH_P3041) || \
defined(CONFIG_ARCH_P4080) || \
defined(CONFIG_ARCH_P5020) || \
defined(CONFIG_ARCH_P5040) || \
defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1

21
arch/powerpc/include/asm/immap_85xx.h
View file

@ -1808,7 +1808,7 @@ typedef struct ccsr_gur {
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#elif defined(CONFIG_ARCH_T2080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
@ -1853,7 +1853,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
#if defined(CONFIG_ARCH_P2041) || \
defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
defined(CONFIG_ARCH_P3041)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
@ -1880,7 +1880,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#if defined(CONFIG_ARCH_T2080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
@ -2157,10 +2157,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
#elif defined(CONFIG_ARCH_P1023)
#if defined(CONFIG_ARCH_P1023)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
@ -2278,12 +2275,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
#endif
#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
#define MPC85xx_PMUXCR_TDM 0x00014800
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
@ -2363,10 +2354,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
#endif
#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000

31
board/advantech/dms-ba16/Kconfig
View file

@ -1,31 +0,0 @@
if TARGET_ADVANTECH_DMS_BA16
choice
prompt "DDR Size"
default SYS_DDR_2G
config SYS_DDR_1G
bool "1GiB"
config SYS_DDR_2G
bool "2GiB"
endchoice
config IMX_CONFIG
default "board/advantech/dms-ba16/dms-ba16_2g.cfg" if SYS_DDR_2G
default "board/advantech/dms-ba16/dms-ba16_1g.cfg" if SYS_DDR_1G
config SYS_BOARD
default "dms-ba16"
config SYS_VENDOR
default "advantech"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "advantech_dms-ba16"
endif

8
board/advantech/dms-ba16/MAINTAINERS
View file

@ -1,8 +0,0 @@
ADVANTECH_DMS-BA16 BOARD
M: Akshay Bhat <akshaybhat@timesys.com>
M: Ken Lin <Ken.Lin@advantech.com.tw>
S: Maintained
F: board/advantech/dms-ba16/
F: include/configs/advantech_dms-ba16.h
F: configs/dms-ba16_defconfig
F: configs/dms-ba16-1g_defconfig

6
board/advantech/dms-ba16/Makefile
View file

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2016 Timesys Corporation
# Copyright 2016 Advantech Corporation
obj-y := dms-ba16.o

25
board/advantech/dms-ba16/clocks.cfg
View file

@ -1,25 +0,0 @@
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en 1 --> CKO1 enabled
* cko1_div 111 --> divide by 8
* cko1_sel 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
*/
DATA 4, CCM_CCOSR, 0x000000fb

39
board/advantech/dms-ba16/ddr-setup.cfg
View file

@ -1,39 +0,0 @@
/* DDR IO */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030

630
board/advantech/dms-ba16/dms-ba16.c
View file

@ -1,630 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Timesys Corporation
* Copyright 2016 Advantech Corporation
* Copyright 2012 Freescale Semiconductor, Inc.
*/
#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <input.h>
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
/* AR8033 PHY Reset */
MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset AR8033 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 28), 1);
mdelay(1);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
.gp = IMX_GPIO_NR(5, 26)
}
};
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info i2c_pad_info3 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 6)
}
};
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
}
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif
static iomux_v3_cfg_t const pcie_pads[] = {
MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_pcie(void)
{
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = 1; /* eMMC is always present */
break;
case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
int ret;
int i;
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers\n"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
static int mx6_rgmii_rework(struct phy_device *phydev)
{
/* set device address 0x7 */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
/* offset 0x8016: CLK_25M Clock Select */
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
/* enable register write, no post increment, address 0x7 */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
/* set to 125 MHz from local PLL source */
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
/* set debug port address: SerDes Test and System Mode Control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
/* enable rgmii tx clock delay */
/* set the reserved bits to avoid board specific voltage peak issue*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Power for LVDS Display */
MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
/* Backlight enable for LVDS display */
MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
/* backlight PWM brightness control */
MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void do_enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
}
int board_cfb_skip(void)
{
gpio_direction_output(LVDS_POWER_GP, 1);
return 0;
}
static int detect_baseboard(struct display_info_t const *dev)
{
return 0 == dev->addr;
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_baseboard,
.enable = NULL,
.mode = {
.name = "SHARP-LQ156M1LG21",
.refresh = 60,
.xres = 1920,
.yres = 1080,
.pixclock = 7851,
.left_margin = 100,
.right_margin = 40,
.upper_margin = 30,
.lower_margin = 3,
.hsync_len = 10,
.vsync_len = 2,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = -1,
.addr = 3,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
imx_setup_hdmi();
/* Set LDB_DI0 as clock source for IPU_DI0 */
clrsetbits_le32(&mxc_ccm->chsccdr,
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
(CHSCCDR_CLK_SEL_LDB_DI0 <<
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
/* Turn on IPU LDB DI0 clocks */
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
enable_ipu_clock();
writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
&iomux->gpr[2]);
clrsetbits_le32(&iomux->gpr[3],
IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
/* backlights off until needed */
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
gpio_direction_input(LVDS_POWER_GP);
gpio_direction_input(LVDS_BACKLIGHT_GP);
}
#endif /* CONFIG_VIDEO_IPUV3 */
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_eth_init(struct bd_info *bis)
{
setup_iomux_enet();
setup_pcie();
return cpu_eth_init(bis);
}
static iomux_v3_cfg_t const misc_pads[] = {
MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
};
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
#define WIFI_EN IMX_GPIO_NR(6, 14)
int setup_ba16_sata(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
ret = enable_sata_clock();
if (ret)
return ret;
clrsetbits_le32(&iomuxc_regs->gpr[13],
IOMUXC_GPR13_SATA_MASK,
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|IOMUXC_GPR13_SATA_PHY_7_SATA2M
|IOMUXC_GPR13_SATA_SPEED_3G
|(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
|IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
|IOMUXC_GPR13_SATA_PHY_1_SLOW);
return 0;
}
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(misc_pads,
ARRAY_SIZE(misc_pads));
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
/* Set LDB clock to PLL2 PFD0 */
select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
#endif
return 0;
}
int board_init(void)
{
gpio_direction_output(SUS_S3_OUT, 1);
gpio_direction_output(WIFI_EN, 1);
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{NULL, 0},
};
#endif
void pmic_init(void)
{
#define DA9063_ADDR 0x58
#define BCORE2_CONF 0x9D
#define BCORE1_CONF 0x9E
#define BPRO_CONF 0x9F
#define BIO_CONF 0xA0
#define BMEM_CONF 0xA1
#define BPERI_CONF 0xA2
#define MODE_BIT_H 7
#define MODE_BIT_L 6
uchar val;
i2c_set_bus_num(2);
i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
}
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
#if defined(CONFIG_VIDEO_IPUV3)
/*
* We need at least 200ms between power on and backlight on
* as per specifications from CHI MEI
*/
mdelay(250);
/* enable backlight PWM 1 */
pwm_init(0, 0, 0);
/* duty cycle 5000000ns, period: 5000000ns */
pwm_config(0, 5000000, 5000000);
/* Backlight Power */
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
pwm_enable(0);
#endif
#ifdef CONFIG_SATA
setup_ba16_sata();
#endif
/* board specific pmic init */
pmic_init();
return 0;
}
int checkboard(void)
{
printf("BOARD: %s\n", CONFIG_BOARD_NAME);
return 0;
}

24
board/advantech/dms-ba16/dms-ba16_1g.cfg
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@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
*
* Copyright 2015 Timesys Corporation.
* Copyright 2015 General Electric Company
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
IMAGE_VERSION 2
BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "micron-1g.cfg"
#include "clocks.cfg"

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board/advantech/dms-ba16/dms-ba16_2g.cfg
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@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
*
* Copyright 2015 Timesys Corporation.
* Copyright 2015 General Electric Company
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
IMAGE_VERSION 2
BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "samsung-2g.cfg"
#include "clocks.cfg"

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board/advantech/dms-ba16/micron-1g.cfg
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/* Calibrations */
/* ZQ */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
/* write leveling */
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
/* Read DQS Gating calibration */
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43480350
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x033C0340
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43480350
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03340314
/* Read calibration */
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x382E2C32
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363044
/* Write calibration */
DATA 4 MX6_MMDC_P0_MPWRDLCTL, 0x3A38403A
DATA 4 MX6_MMDC_P1_MPWRDLCTL, 0x4432483E
/* read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/* Complete calibration by forced measurment */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/* MMDC init */
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A79A5
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
DATA 4, MX6_MMDC_P0_MDOR, 0x005a1023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831a0000
/* Initialize memory */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048039
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00033337
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00033337
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

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board/advantech/dms-ba16/samsung-2g.cfg
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@ -1,63 +0,0 @@
/* Calibrations */
/* ZQ */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
/* write leveling */
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
/* Read DQS Gating calibration */
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C
/* Read calibration */
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042
/* Write calibration */
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E
/* read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/* Complete calibration by forced measurment */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/* MMDC init */
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000
/* Initialize memory */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031
DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

12
board/amazon/kc1/Kconfig
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@ -1,12 +0,0 @@
if TARGET_KC1
config SYS_BOARD
default "kc1"
config SYS_VENDOR
default "amazon"
config SYS_CONFIG_NAME
default "kc1"
endif

6
board/amazon/kc1/MAINTAINERS
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@ -1,6 +0,0 @@
KC1 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: board/amazon/kc1/
F: include/configs/kc1.h
F: configs/kc1_defconfig

7
board/amazon/kc1/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Amazon Kindle Fire (first generation) codename kc1 config
#
# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
obj-y := kc1.o

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board/amazon/kc1/kc1.c
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@ -1,184 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Amazon Kindle Fire (first generation) codename kc1 config
*
* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
*/
#include <config.h>
#include <common.h>
#include <env.h>
#include <fastboot.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/gpio.h>
#include <asm/emif.h>
#include <twl6030.h>
#include "kc1.h"
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
.board_string = "kc1"
};
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12
};
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_UTMI,
};
static struct musb_hdrc_platform_data musb_platform_data = {
.mode = MUSB_PERIPHERAL,
.config = &musb_config,
.power = 100,
.platform_ops = &omap2430_ops,
.board_data = &musb_board_data,
};
void set_muxconf_regs(void)
{
do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array,
sizeof(core_padconf_array) / sizeof(struct pad_conf_entry));
}
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
if (cs == CS1)
return NULL;
*lpddr2_dev_details = elpida_2G_S4_details;
return lpddr2_dev_details;
}
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
*cs0_device_timings = &elpida_2G_S4_timings;
*cs1_device_timings = NULL;
}
int board_init(void)
{
/* GPMC init */
gpmc_init();
/* MACH number */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
/* ATAGs location */
gd->bd->bi_boot_params = OMAP44XX_DRAM_ADDR_SPACE_START + 0x100;
return 0;
}
int misc_init_r(void)
{
char reboot_mode[2] = { 0 };
u32 data = 0;
u32 value;
int rc;
/* Reboot mode */
rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
/* USB ID pin pull-up indicates factory (fastboot) cable detection. */
gpio_request(KC1_GPIO_USB_ID, "USB_ID");
gpio_direction_input(KC1_GPIO_USB_ID);
value = gpio_get_value(KC1_GPIO_USB_ID);
if (value)
reboot_mode[0] = 'b';
if (rc < 0 || reboot_mode[0] == 'o') {
/*
* When not rebooting, valid power on reasons are either the
* power button, charger plug or USB plug.
*/
data |= twl6030_input_power_button();
data |= twl6030_input_charger();
data |= twl6030_input_usb();
if (!data)
twl6030_power_off();
}
if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
if (!env_get("reboot-mode"))
env_set("reboot-mode", (char *)reboot_mode);
}
omap_reboot_mode_clear();
/* Serial number */
omap_die_id_serial();
/* MUSB */
musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
return 0;
}
u32 get_board_rev(void)
{
u32 value = 0;
gpio_request(KC1_GPIO_MBID0, "MBID0");
gpio_request(KC1_GPIO_MBID1, "MBID1");
gpio_request(KC1_GPIO_MBID2, "MBID2");
gpio_request(KC1_GPIO_MBID3, "MBID3");
gpio_direction_input(KC1_GPIO_MBID0);
gpio_direction_input(KC1_GPIO_MBID1);
gpio_direction_input(KC1_GPIO_MBID2);
gpio_direction_input(KC1_GPIO_MBID3);
value |= (gpio_get_value(KC1_GPIO_MBID0) << 0);
value |= (gpio_get_value(KC1_GPIO_MBID1) << 1);
value |= (gpio_get_value(KC1_GPIO_MBID2) << 2);
value |= (gpio_get_value(KC1_GPIO_MBID3) << 3);
return value;
}
void get_board_serial(struct tag_serialnr *serialnr)
{
omap_die_id_get_board_serial(serialnr);
}
int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
{
if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
return -ENOTSUPP;
return omap_reboot_mode_store("b");
}
int board_mmc_init(struct bd_info *bis)
{
return omap_mmc_init(1, 0, 0, -1, -1);
}
void board_mmc_power_init(void)
{
twl6030_power_mmc_init(1);
}

97
board/amazon/kc1/kc1.h
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@ -1,97 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Amazon Kindle Fire (first generation) codename kc1 config
*
* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
*/
#ifndef _KC1_H_
#define _KC1_H_
#include <asm/arch/mux_omap4.h>
#define KC1_GPIO_USB_ID 52
#define KC1_GPIO_MBID1 173
#define KC1_GPIO_MBID0 174
#define KC1_GPIO_MBID3 177
#define KC1_GPIO_MBID2 178
const struct pad_conf_entry core_padconf_array[] = {
/* GPMC */
{ GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
{ GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
{ GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
{ GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */
{ GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */
{ GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */
{ GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */
{ GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */
{ GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */
{ GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */
{ GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */
/* CAM */
{ CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
{ CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
{ CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
/* HDQ */
{ HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
/* I2C1 */
{ I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */
{ I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */
/* I2C2 */
{ I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */
{ I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */
/* I2C3 */
{ I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */
{ I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */
/* I2C4 */
{ I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */
{ I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */
/* MCSPI1 */
{ MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */
/* UART3 */
{ UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */
{ UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */
{ UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */
{ UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */
/* SDMMC5 */
{ SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */
{ SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */
{ SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */
{ SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */
{ SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */
{ SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */
/* MCSPI4 */
{ MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */
{ MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */
{ MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */
{ MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */
/* UART4 */
{ UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */
{ UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */
/* UNIPRO */
{ UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
{ UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
{ UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
{ UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
{ UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
{ UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
{ UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */
/* USBA0_OTG */
{ USBA0_OTG_CE, (IDIS | PTD | M0) }, /* usba0_otg_ce */
{ USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */
{ USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */
};
#endif

15
board/armadeus/apf27/Kconfig
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@ -1,15 +0,0 @@
if TARGET_APF27
config SYS_BOARD
default "apf27"
config SYS_VENDOR
default "armadeus"
config SYS_SOC
default "mx27"
config SYS_CONFIG_NAME
default "apf27"
endif

7
board/armadeus/apf27/MAINTAINERS
View file

@ -1,7 +0,0 @@
APF27 BOARD
M: Philippe Reynes <tremyfr@yahoo.fr>
M: Eric Jarrige <eric.jarrige@armadeus.org>
S: Maintained
F: board/armadeus/apf27/
F: include/configs/apf27.h
F: configs/apf27_defconfig

12
board/armadeus/apf27/Makefile
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@ -1,12 +0,0 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2012-2013
# Eric Jarrige <eric.jarrige@armadeus.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := apf27.o
obj-y += lowlevel_init.o
obj-$(CONFIG_FPGA) += fpga.o

259
board/armadeus/apf27/apf27.c
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@ -1,259 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
*
* based on the files by
* Sascha Hauer, Pengutronix
*/
#include <common.h>
#include <hang.h>
#include <init.h>
#include <asm/global_data.h>
#include <jffs2/jffs2.h>
#include <nand.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
#include "apf27.h"
#include "fpga.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Fuse bank 1 row 8 is "reserved for future use" and therefore available for
* customer use. The APF27 board uses this fuse to store the board revision:
* 0: initial board revision
* 1: first revision - Presence of the second RAM chip on the board is blown in
* fuse bank 1 row 9 bit 0 - No hardware change
* N: to be defined
*/
static u32 get_board_rev(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
return readl(&iim->bank[1].fuse_regs[8]);
}
/*
* Fuse bank 1 row 9 is "reserved for future use" and therefore available for
* customer use. The APF27 board revision 1 uses the bit 0 to permanently store
* the presence of the second RAM chip
* 0: AFP27 with 1 RAM of 64 MiB
* 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
*/
static int get_num_ram_bank(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
int nr_dram_banks = 1;
if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
else
nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
return nr_dram_banks;
}
static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
u32 puen, u32 gius)
{
struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
writel(gpio_dr, &regs->port[port].gpio_dr);
writel(ocr1, &regs->port[port].ocr1);
writel(ocr2, &regs->port[port].ocr2);
writel(iconfa1, &regs->port[port].iconfa1);
writel(iconfa2, &regs->port[port].iconfa2);
writel(iconfb1, &regs->port[port].iconfb1);
writel(iconfb2, &regs->port[port].iconfb2);
writel(icr1, &regs->port[port].icr1);
writel(icr2, &regs->port[port].icr2);
writel(imr, &regs->port[port].imr);
writel(gpio_dir, &regs->port[port].gpio_dir);
writel(gpr, &regs->port[port].gpr);
writel(puen, &regs->port[port].puen);
writel(gius, &regs->port[port].gius);
}
#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \
ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \
ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \
ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \
ACFG_GIUS_##n##_VAL)
static void apf27_iomux_init(void)
{
APF27_PORT_INIT(A);
APF27_PORT_INIT(B);
APF27_PORT_INIT(C);
APF27_PORT_INIT(D);
APF27_PORT_INIT(E);
APF27_PORT_INIT(F);
}
static int apf27_devices_init(void)
{
int i;
unsigned int mode[] = {
PC5_PF_I2C2_DATA,
PC6_PF_I2C2_CLK,
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
#ifdef CONFIG_MXC_UART
mx27_uart1_init_pins();
#endif
#ifdef CONFIG_FEC_MXC
mx27_fec_init_pins();
#endif
#ifdef CONFIG_MMC_MXC
mx27_sd2_init_pins();
imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
gpio_request(PC_PWRON, "pc_pwron");
gpio_set_value(PC_PWRON, 1);
#endif
return 0;
}
static void apf27_setup_csx(void)
{
struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
writel(ACFG_CS0U_VAL, &weim->cs0u);
writel(ACFG_CS0L_VAL, &weim->cs0l);
writel(ACFG_CS0A_VAL, &weim->cs0a);
writel(ACFG_CS1U_VAL, &weim->cs1u);
writel(ACFG_CS1L_VAL, &weim->cs1l);
writel(ACFG_CS1A_VAL, &weim->cs1a);
writel(ACFG_CS2U_VAL, &weim->cs2u);
writel(ACFG_CS2L_VAL, &weim->cs2l);
writel(ACFG_CS2A_VAL, &weim->cs2a);
writel(ACFG_CS3U_VAL, &weim->cs3u);
writel(ACFG_CS3L_VAL, &weim->cs3l);
writel(ACFG_CS3A_VAL, &weim->cs3a);
writel(ACFG_CS4U_VAL, &weim->cs4u);
writel(ACFG_CS4L_VAL, &weim->cs4l);
writel(ACFG_CS4A_VAL, &weim->cs4a);
writel(ACFG_CS5U_VAL, &weim->cs5u);
writel(ACFG_CS5L_VAL, &weim->cs5l);
writel(ACFG_CS5A_VAL, &weim->cs5a);
writel(ACFG_EIM_VAL, &weim->eim);
}
static void apf27_setup_port(void)
{
struct system_control_regs *system =
(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
writel(ACFG_FMCR_VAL, &system->fmcr);
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
apf27_setup_csx();
apf27_setup_port();
apf27_iomux_init();
apf27_devices_init();
#if defined(CONFIG_FPGA)
APF27_init_fpga();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
if (get_num_ram_bank() > 1)
gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
if (get_num_ram_bank() > 1)
gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
else
gd->bd->bi_dram[1].size = 0;
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
ulong ramtop;
if (get_num_ram_bank() > 1)
ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
else
ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return ramtop;
}
int checkboard(void)
{
printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
return 0;
}
#ifdef CONFIG_SPL_BUILD
inline void hang(void)
{
for (;;)
;
}
void board_init_f(ulong bootflag)
{
/*
* copy ourselves from where we are running to where we were
* linked at. Use ulong pointers as all addresses involved
* are 4-byte-aligned.
*/
ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
for (dst = start_ptr; dst < end_ptr; dst++)
*dst = *(dst+(run_ptr-link_ptr));
/*
* branch to nand_boot's link-time address.
*/
asm volatile("ldr pc, =nand_boot");
}
#endif /* CONFIG_SPL_BUILD */

488
board/armadeus/apf27/apf27.h
View file

@ -1,488 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
*/
#ifndef __APF27_H
#define __APF27_H
/* FPGA program pin configuration */
#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */
#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */
#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
/* MMC pin */
#define PC_PWRON (GPIO_PORTF | 16)
/*
* MPU CLOCK source before PLL
* ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
*/
#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
#define ACFG_MPCTL1_VAL 0
#define CONFIG_MPLL_FREQ 399
#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
#define ACFG_SPCTL1_VAL 0
#define CONFIG_SPLL_FREQ 300 /* MHz */
/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */
#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */
#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */
#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */
#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */
#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
#define CONFIG_CLK0_EN 1 /* CLK0 enabled */
/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */
/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
#define CONFIG_USB_FREQ 60 /* 60 MHz */
/*
* SDRAM
*/
#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
* column address bits
*/
#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13
* row address bits
*/
#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
* 2=4096 3=8192 refresh
*/
#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
* down delay
*/
#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
* cycle delay > 0
*/
#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
* cycle delay 1..4
*/
#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
* SDRAM: 0=1ck 1=2ck
*/
#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
* refresh to command)
*/
#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
* estimated fo CL=1
* 0=force 3 for lpddr
*/
#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
* 3=Eighth 4=Sixteenth
*/
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
* 2=quater 3=Eighth
*/
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
* 0 = Burst mode
*/
#endif
#if (ACFG_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
* column address bits
*/
#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
* row address bits
*/
#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
* 2=4096 3=8192 refresh
*/
#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
* down delay
*/
#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
* cycle delay > 0
*/
#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
* cycle delay 1..4
*/
#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
* SDRAM: 0=1ck 1=2ck
*/
#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
* refresh to command)
*/
#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
* estimated fo CL=1
* 0=force 3 for lpddr
*/
#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
* 3=Eighth 4=Sixteenth
*/
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
* 2=quater 3=Eighth
*/
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
* 0 = Burst mode
*/
#endif
#if (ACFG_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11
* column address bits
*/
#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
* row address bits
*/
#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
* 2=4096 3=8192 refresh
*/
#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
* down delay
*/
#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle
* delay > 0
*/
#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
* cycle delay 1..4
*/
#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
* SDRAM: 0=1ck 1=2ck
*/
#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
* refresh to command)
*/
#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
* estimated fo CL=1
* 0=force 3 for lpddr
*/
#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
* 3=Eighth 4=Sixteenth
*/
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength
* 1=half
* 2=quater
* 3=Eighth
*/
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
* 0 = Burst mode
*/
#endif
/*
* External interface
*/
/*
* CSCRxU_VAL:
* 31| x | x | x x |x x x x| x x | x | x |x x x x|16
* |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL |
*
* 15| x x | x x x x x x | x | x x x x | x x x x |0
* | CNC | WSC |EW | WWS | EDC |
*
* CSCRxL_VAL:
* 31| x x x x | x x x x | x x x x | x x x x |16
* | OEA | OEN | EBWA | EBWN |
* 15|x x x x| x |x x x |x x x x| x | x | x | x | 0
* | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN|
*
* CSCRxA_VAL:
* 31| x x x x | x x x x | x x x x | x x x x |16
* | EBRA | EBRN | RWA | RWN |
* 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0
* |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
*/
/* CS0 configuration for 16 bit nor flash */
#define ACFG_CS0U_VAL 0x0000CC03
#define ACFG_CS0L_VAL 0xa0330D01
#define ACFG_CS0A_VAL 0x00220800
#define ACFG_CS1U_VAL 0x00000f00
#define ACFG_CS1L_VAL 0x00000D01
#define ACFG_CS1A_VAL 0
#define ACFG_CS2U_VAL 0
#define ACFG_CS2L_VAL 0
#define ACFG_CS2A_VAL 0
#define ACFG_CS3U_VAL 0
#define ACFG_CS3L_VAL 0
#define ACFG_CS3A_VAL 0
#define ACFG_CS4U_VAL 0
#define ACFG_CS4L_VAL 0
#define ACFG_CS4A_VAL 0
/* FPGA 16 bit data bus */
#define ACFG_CS5U_VAL 0x00000600
#define ACFG_CS5L_VAL 0x00000D01
#define ACFG_CS5A_VAL 0
#define ACFG_EIM_VAL 0x00002200
/*
* FPGA specific settings
*/
/* CLKO */
#define ACFG_CCSR_VAL 0x00000305
/* drive strength CLKO set to 2 */
#define ACFG_DSCR10_VAL 0x00020000
/* drive strength A1..A12 set to 2 */
#define ACFG_DSCR3_VAL 0x02AAAAA8
/* drive strength ctrl */
#define ACFG_DSCR7_VAL 0x00020880
/* drive strength data */
#define ACFG_DSCR2_VAL 0xAAAAAAAA
/*
* Default configuration for GPIOs and peripherals
*/
#define ACFG_DDIR_A_VAL 0x00000000
#define ACFG_OCR1_A_VAL 0x00000000
#define ACFG_OCR2_A_VAL 0x00000000
#define ACFG_ICFA1_A_VAL 0xFFFFFFFF
#define ACFG_ICFA2_A_VAL 0xFFFFFFFF
#define ACFG_ICFB1_A_VAL 0xFFFFFFFF
#define ACFG_ICFB2_A_VAL 0xFFFFFFFF
#define ACFG_DR_A_VAL 0x00000000
#define ACFG_GIUS_A_VAL 0xFFFFFFFF
#define ACFG_ICR1_A_VAL 0x00000000
#define ACFG_ICR2_A_VAL 0x00000000
#define ACFG_IMR_A_VAL 0x00000000
#define ACFG_GPR_A_VAL 0x00000000
#define ACFG_PUEN_A_VAL 0xFFFFFFFF
#define ACFG_DDIR_B_VAL 0x00000000
#define ACFG_OCR1_B_VAL 0x00000000
#define ACFG_OCR2_B_VAL 0x00000000
#define ACFG_ICFA1_B_VAL 0xFFFFFFFF
#define ACFG_ICFA2_B_VAL 0xFFFFFFFF
#define ACFG_ICFB1_B_VAL 0xFFFFFFFF
#define ACFG_ICFB2_B_VAL 0xFFFFFFFF
#define ACFG_DR_B_VAL 0x00000000
#define ACFG_GIUS_B_VAL 0xFF3FFFF0
#define ACFG_ICR1_B_VAL 0x00000000
#define ACFG_ICR2_B_VAL 0x00000000
#define ACFG_IMR_B_VAL 0x00000000
#define ACFG_GPR_B_VAL 0x00000000
#define ACFG_PUEN_B_VAL 0xFFFFFFFF
#define ACFG_DDIR_C_VAL 0x00000000
#define ACFG_OCR1_C_VAL 0x00000000
#define ACFG_OCR2_C_VAL 0x00000000
#define ACFG_ICFA1_C_VAL 0xFFFFFFFF
#define ACFG_ICFA2_C_VAL 0xFFFFFFFF
#define ACFG_ICFB1_C_VAL 0xFFFFFFFF
#define ACFG_ICFB2_C_VAL 0xFFFFFFFF
#define ACFG_DR_C_VAL 0x00000000
#define ACFG_GIUS_C_VAL 0xFFFFC07F
#define ACFG_ICR1_C_VAL 0x00000000
#define ACFG_ICR2_C_VAL 0x00000000
#define ACFG_IMR_C_VAL 0x00000000
#define ACFG_GPR_C_VAL 0x00000000
#define ACFG_PUEN_C_VAL 0xFFFFFF87
#define ACFG_DDIR_D_VAL 0x00000000
#define ACFG_OCR1_D_VAL 0x00000000
#define ACFG_OCR2_D_VAL 0x00000000
#define ACFG_ICFA1_D_VAL 0xFFFFFFFF
#define ACFG_ICFA2_D_VAL 0xFFFFFFFF
#define ACFG_ICFB1_D_VAL 0xFFFFFFFF
#define ACFG_ICFB2_D_VAL 0xFFFFFFFF
#define ACFG_DR_D_VAL 0x00000000
#define ACFG_GIUS_D_VAL 0xFFFFFFFF
#define ACFG_ICR1_D_VAL 0x00000000
#define ACFG_ICR2_D_VAL 0x00000000
#define ACFG_IMR_D_VAL 0x00000000
#define ACFG_GPR_D_VAL 0x00000000
#define ACFG_PUEN_D_VAL 0xFFFFFFFF
#define ACFG_DDIR_E_VAL 0x00000000
#define ACFG_OCR1_E_VAL 0x00000000
#define ACFG_OCR2_E_VAL 0x00000000
#define ACFG_ICFA1_E_VAL 0xFFFFFFFF
#define ACFG_ICFA2_E_VAL 0xFFFFFFFF
#define ACFG_ICFB1_E_VAL 0xFFFFFFFF
#define ACFG_ICFB2_E_VAL 0xFFFFFFFF
#define ACFG_DR_E_VAL 0x00000000
#define ACFG_GIUS_E_VAL 0xFCFFCCF8
#define ACFG_ICR1_E_VAL 0x00000000
#define ACFG_ICR2_E_VAL 0x00000000
#define ACFG_IMR_E_VAL 0x00000000
#define ACFG_GPR_E_VAL 0x00000000
#define ACFG_PUEN_E_VAL 0xFFFFFFFF
#define ACFG_DDIR_F_VAL 0x00000000
#define ACFG_OCR1_F_VAL 0x00000000
#define ACFG_OCR2_F_VAL 0x00000000
#define ACFG_ICFA1_F_VAL 0xFFFFFFFF
#define ACFG_ICFA2_F_VAL 0xFFFFFFFF
#define ACFG_ICFB1_F_VAL 0xFFFFFFFF
#define ACFG_ICFB2_F_VAL 0xFFFFFFFF
#define ACFG_DR_F_VAL 0x00000000
#define ACFG_GIUS_F_VAL 0xFF7F8000
#define ACFG_ICR1_F_VAL 0x00000000
#define ACFG_ICR2_F_VAL 0x00000000
#define ACFG_IMR_F_VAL 0x00000000
#define ACFG_GPR_F_VAL 0x00000000
#define ACFG_PUEN_F_VAL 0xFFFFFFFF
/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
#define ACFG_GPCR_VAL 0x0003000F
#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
#if (CONFIG_NR_DRAM_BANKS == 1)
#define ACFG_FMCR_VAL 0xFFFFFFF9
#elif (CONFIG_NR_DRAM_BANKS == 2)
#define ACFG_FMCR_VAL 0xFFFFFFFB
#endif
#define ACFG_AIPI1_PSR0_VAL 0x20040304
#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB
#define ACFG_AIPI2_PSR0_VAL 0x00000000
#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF
/* PCCR enable DMA FEC I2C1 IIM SDHC1 */
#define ACFG_PCCR0_VAL 0x05070410
#define ACFG_PCCR1_VAL 0xA14A0608
/*
* From here, there should not be any user configuration.
* All Equations are automatic
*/
/* fixme none integer value (7.5ns) => 2*hclock = 15ns */
#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */
/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
#define CSCR_MASK 0x0300800D
#define ACFG_CSCR_VAL \
(CSCR_MASK \
|((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \
|((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \
|((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8))
/* SSIx CLKO NFC H264 MSHC */
#define ACFG_PCDR0_VAL\
(((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \
|((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \
|(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
|(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
|(((CONFIG_CLK0_DIV)&0x07)<<22)\
|(((CONFIG_CLK0_EN)&0x01)<<25)\
|(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
/* PERCLKx */
#define ACFG_PCDR1_VAL\
(((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \
|((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \
|((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \
|((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
/* SDRAM controller programming Values */
#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
(ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
#define REG_FIELD_SCL_VAL 3
#define REG_FIELD_SCLIMX_VAL 0
#else
#define REG_FIELD_SCL_VAL\
((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
ACFG_2XHCLK_LGTH)
#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL
#endif
#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH))
#define REG_FIELD_SRC_VAL 0
#else
#define REG_FIELD_SRC_VAL\
((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
ACFG_2XHCLK_LGTH)
#endif
/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/
#define REG_ESDCTL_BASE_CONFIG (0x80020485\
| (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
| (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\
| (((ACFG_SDRAM_REFRESH)&0x7)<<13))
#define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG)
#define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG)
#define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG)
#define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG)
/* ESDRAMC Configuration Registers : force CL=3 to lpddr */
#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\
| (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\
| (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\
| (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \
ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \
| (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
| (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\
| (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \
| (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \
| (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\
| (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \
| (((REG_FIELD_SRC_VAL)&0x0F)<<0))
/* Issue Mode register Command to SDRAM */
#define ACFG_SDRAM_MODE_REGISTER_VAL\
((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
| (((REG_FIELD_SCL_VAL)&0x7)<<(4))\
| ((0)<<(3)) /* sequentiql access */ \
/*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/)
/* Issue Extended Mode register Command to SDRAM */
#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\
((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\
| (ACFG_SDRAM_DRIVE_STRENGH<<(5))\
| (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2)))
/* Issue Precharge all Command to SDRAM */
#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10)
#endif /* __APF27_H */

226
board/armadeus/apf27/fpga.c
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@ -1,226 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002-2013
* Eric Jarrige <eric.jarrige@armadeus.org>
*
* based on the files by
* Rich Ireland, Enterasys Networks, rireland@enterasys.com
* and
* Keith Outwater, keith_outwater@mvis.com
*/
#include <common.h>
#include <log.h>
#include <linux/delay.h>
#include <asm/arch/imx-regs.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <command.h>
#include <config.h>
#include "fpga.h"
#include <spartan3.h>
#include "apf27.h"
/*
* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
NULL,
fpga_done_fn,
fpga_clk_fn,
fpga_cs_fn,
fpga_wr_fn,
fpga_rdata_fn,
fpga_wdata_fn,
fpga_busy_fn,
fpga_abort_fn,
fpga_post_fn,
};
xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)&fpga_fns,
0,
&spartan3_op,
"3s200aft256"}
};
/*
* Initialize GPIO port B before download
*/
int fpga_pre_fn(int cookie)
{
/* Initialize GPIO pins */
gpio_set_value(ACFG_FPGA_PWR, 1);
imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
gpio_set_value(ACFG_FPGA_RESET, 1);
imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
gpio_set_value(ACFG_FPGA_PRG, 1);
gpio_set_value(ACFG_FPGA_CLK, 1);
gpio_set_value(ACFG_FPGA_RW, 1);
gpio_set_value(ACFG_FPGA_CS, 1);
gpio_set_value(ACFG_FPGA_SUSPEND, 0);
gpio_set_value(ACFG_FPGA_PWR, 0);
udelay(30000); /*wait until supply started*/
return cookie;
}
/*
* Set the FPGA's active-low program line to the specified level
*/
int fpga_pgm_fn(int assert, int flush, int cookie)
{
debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
assert ? "high" : "low");
gpio_set_value(ACFG_FPGA_PRG, !assert);
return assert;
}
/*
* Set the FPGA's active-high clock line to the specified level
*/
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
assert_clk ? "high" : "low");
gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
return assert_clk;
}
/*
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
int fpga_init_fn(int cookie)
{
int value;
debug("%s:%d: INIT check... ", __func__, __LINE__);
value = gpio_get_value(ACFG_FPGA_INIT);
/* printf("init value read %x",value); */
#ifdef CONFIG_SYS_FPGA_IS_PROTO
return value;
#else
return !value;
#endif
}
/*
* Test the state of the active-high FPGA DONE pin
*/
int fpga_done_fn(int cookie)
{
debug("%s:%d: DONE check... %s", __func__, __LINE__,
gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
}
/*
* Set the FPGA's wr line to the specified level
*/
int fpga_wr_fn(int assert_write, int flush, int cookie)
{
debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
assert_write ? "high" : "low");
gpio_set_value(ACFG_FPGA_RW, !assert_write);
return assert_write;
}
int fpga_cs_fn(int assert_cs, int flush, int cookie)
{
debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
assert_cs ? "high" : "low");
gpio_set_value(ACFG_FPGA_CS, !assert_cs);
return assert_cs;
}
int fpga_rdata_fn(unsigned char *data, int cookie)
{
debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
*((char *)ACFG_FPGA_RDATA));
*data = (unsigned char)
((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
return *data;
}
int fpga_wdata_fn(unsigned char data, int flush, int cookie)
{
debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
data);
*((unsigned short *)ACFG_FPGA_WDATA) = data;
return data;
}
int fpga_abort_fn(int cookie)
{
return fpga_post_fn(cookie);
}
int fpga_busy_fn(int cookie)
{
return 1;
}
int fpga_post_fn(int cookie)
{
debug("%s:%d: FPGA POST ", __func__, __LINE__);
imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
gpio_set_value(ACFG_FPGA_PRG, 1);
gpio_set_value(ACFG_FPGA_RESET, 0);
imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
return cookie;
}
void apf27_fpga_setup(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
struct system_control_regs *system =
(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
/* Configure FPGA CLKO */
writel(ACFG_CCSR_VAL, &pll->ccsr);
/* Configure strentgh for FPGA */
writel(ACFG_DSCR10_VAL, &system->dscr10);
writel(ACFG_DSCR3_VAL, &system->dscr3);
writel(ACFG_DSCR7_VAL, &system->dscr7);
writel(ACFG_DSCR2_VAL, &system->dscr2);
}
/*
* Initialize the fpga. Return 1 on success, 0 on failure.
*/
void APF27_init_fpga(void)
{
int i;
apf27_fpga_setup();
fpga_init();
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
fpga_add(fpga_xilinx, &fpga[i]);
}
return;
}

24
board/armadeus/apf27/fpga.h
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@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002-2013
* Eric Jarrige <eric.jarrige@armadeus.org>
*
* based on the files by
* Rich Ireland, Enterasys Networks, rireland@enterasys.com
* and
* Keith Outwater, keith_outwater@mvis.com
*/
extern void APF27_init_fpga(void);
extern int fpga_pre_fn(int cookie);
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
extern int fpga_init_fn(int cookie);
extern int fpga_done_fn(int cookie);
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
extern int fpga_wr_fn(int assert_write, int flush, int cookie);
extern int fpga_rdata_fn(unsigned char *data, int cookie);
extern int fpga_wdata_fn(unsigned char data, int flush, int cookie);
extern int fpga_abort_fn(int cookie);
extern int fpga_post_fn(int cookie);
extern int fpga_busy_fn(int cookie);

166
board/armadeus/apf27/lowlevel_init.S
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@ -1,166 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
*/
#include <config.h>
#include <generated/asm-offsets.h>
#include <asm/macro.h>
#include <asm/arch/imx-regs.h>
#include "apf27.h"
.macro init_aipi
/*
* setup AIPI1 and AIPI2
*/
write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
/* Change SDRAM signal strengh */
ldr r0, =GPCR
ldr r1, =ACFG_GPCR_VAL
ldr r5, [r0]
orr r5, r5, r1
str r5, [r0]
.endm /* init_aipi */
.macro init_clock
ldr r0, =CSCR
/* disable MPLL/SPLL first */
ldr r1, [r0]
bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
str r1, [r0]
/*
* pll clock initialization predefined in apf27.h
*/
write32 MPCTL0, ACFG_MPCTL0_VAL
write32 SPCTL0, ACFG_SPCTL0_VAL
write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
/*
* add some delay here
*/
mov r1, #0x1000
1: subs r1, r1, #0x1
bne 1b
/* peripheral clock divider */
write32 PCDR0, ACFG_PCDR0_VAL
write32 PCDR1, ACFG_PCDR1_VAL
/* Configure PCCR0 and PCCR1 */
write32 PCCR0, ACFG_PCCR0_VAL
write32 PCCR1, ACFG_PCCR1_VAL
.endm /* init_clock */
.macro init_ddr
/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
ldr r0, =IMX_ESD_BASE
ldr r4, =ESDMISC_SDRAM_RDY
2: ldr r1, [r0, #ESDMISC_ROF]
ands r1, r1, r4
bpl 2b
/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
ldr r0, =IMX_ESD_BASE
ldr r4, =ACFG_ESDMISC_VAL
orr r1, r4, #ESDMISC_MDDR_DL_RST
str r1, [r0, #ESDMISC_ROF]
/* Hold for more than 200ns */
ldr r1, =0x10000
1: subs r1, r1, #0x1
bne 1b
str r4, [r0]
ldr r0, =IMX_ESD_BASE
ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
str r1, [r0, #ESDCFG0_ROF]
ldr r0, =IMX_ESD_BASE
ldr r1, =ACFG_PRECHARGE_CMD
str r1, [r0, #ESDCTL0_ROF]
/* write8(0xA0001000, any value) */
ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
strb r2, [r1]
ldr r1, =ACFG_AUTOREFRESH_CMD
str r1, [r0, #ESDCTL0_ROF]
ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
ldr r6,=0x7 /* load loop counter */
1: str r5,[r4] /* run auto-refresh cycle to array 0 */
subs r6,r6,#1
bne 1b
ldr r1, =ACFG_SET_MODE_REG_CMD
str r1, [r0, #ESDCTL0_ROF]
/* set standard mode register */
ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
strb r2, [r4]
/* set extended mode register */
ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
strb r5, [r4]
ldr r1, =ACFG_NORMAL_RW_CMD
str r1, [r0, #ESDCTL0_ROF]
/* 2nd sdram */
ldr r0, =IMX_ESD_BASE
ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
str r1, [r0, #ESDCFG1_ROF]
ldr r0, =IMX_ESD_BASE
ldr r1, =ACFG_PRECHARGE_CMD
str r1, [r0, #ESDCTL1_ROF]
/* write8(0xB0001000, any value) */
ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
strb r2, [r1]
ldr r1, =ACFG_AUTOREFRESH_CMD
str r1, [r0, #ESDCTL1_ROF]
ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
ldr r6,=0x7 /* load loop counter */
1: str r5,[r4] /* run auto-refresh cycle to array 0 */
subs r6,r6,#1
bne 1b
ldr r1, =ACFG_SET_MODE_REG_CMD
str r1, [r0, #ESDCTL1_ROF]
/* set standard mode register */
ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
strb r2, [r4]
/* set extended mode register */
ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
strb r2, [r4]
ldr r1, =ACFG_NORMAL_RW_CMD
str r1, [r0, #ESDCTL1_ROF]
.endm /* init_ddr */
.globl lowlevel_init
lowlevel_init:
init_aipi
init_clock
#ifdef CONFIG_SPL_BUILD
init_ddr
#endif
mov pc, lr

38
board/armltd/vexpress/Kconfig
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@ -1,38 +0,0 @@
if TARGET_VEXPRESS_CA15_TC2
config SYS_BOARD
default "vexpress"
config SYS_VENDOR
default "armltd"
config SYS_CONFIG_NAME
default "vexpress_ca15_tc2"
endif
if TARGET_VEXPRESS_CA5X2
config SYS_BOARD
default "vexpress"
config SYS_VENDOR
default "armltd"
config SYS_CONFIG_NAME
default "vexpress_ca5x2"
endif
if TARGET_VEXPRESS_CA9X4
config SYS_BOARD
default "vexpress"
config SYS_VENDOR
default "armltd"
config SYS_CONFIG_NAME
default "vexpress_ca9x4"
endif

10
board/armltd/vexpress/MAINTAINERS
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@ -1,10 +0,0 @@
VERSATILE EXPRESS BOARDS
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: board/armltd/vexpress/
F: include/configs/vexpress_ca15_tc2.h
F: configs/vexpress_ca15_tc2_defconfig
F: include/configs/vexpress_ca5x2.h
F: configs/vexpress_ca5x2_defconfig
F: include/configs/vexpress_ca9x4.h
F: configs/vexpress_ca9x4_defconfig

7
board/armltd/vexpress/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := vexpress_common.o
obj-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress_tc2.o

204
board/armltd/vexpress/vexpress_common.c
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@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* (C) Copyright 2004
* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*/
#include <common.h>
#include <bootstage.h>
#include <cpu_func.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
#include <net.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/systimer.h>
#include <asm/arch/sysctrl.h>
#include <asm/arch/wdt.h>
#include "../drivers/mmc/arm_pl180_mmci.h"
static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
static void flash__init(void);
static void vexpress_timer_init(void);
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
#endif
static inline void delay(ulong loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b" : "=r" (loops) : "0" (loops));
}
int board_init(void)
{
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
icache_enable();
flash__init();
vexpress_timer_init();
return 0;
}
int board_eth_init(struct bd_info *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
int cpu_mmc_init(struct bd_info *bis)
{
int rc = 0;
(void) bis;
#ifdef CONFIG_ARM_PL180_MMCI
struct pl180_mmc_host *host;
struct mmc *mmc;
host = malloc(sizeof(struct pl180_mmc_host));
if (!host)
return -ENOMEM;
memset(host, 0, sizeof(*host));
strcpy(host->name, "MMC");
host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
host->pwr_init = INIT_PWR;
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
host->voltages = VOLTAGE_WINDOW_MMC;
host->caps = 0;
host->clock_in = ARM_MCLK;
host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
rc = arm_pl180_mmci_init(host, &mmc);
#endif
return rc;
}
static void flash__init(void)
{
/* Setup the sytem control register to allow writing to flash */
writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
&sysctrl_base->scflashctrl);
}
int dram_init(void)
{
gd->ram_size =
get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size =
get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size =
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
return 0;
}
/*
* Start timer:
* Setup a 32 bit timer, running at 1KHz
* Versatile Express Motherboard provides 1 MHz timer
*/
static void vexpress_timer_init(void)
{
/*
* Set clock frequency in system controller:
* VEXPRESS_REFCLK is 32KHz
* VEXPRESS_TIMCLK is 1MHz
*/
writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
/*
* Set Timer0 to be:
* Enabled, free running, no interrupt, 32-bit, wrapping
*/
writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
writel(SYSTIMER_EN | SYSTIMER_32BIT |
readl(&systimer_base->timer0control),
&systimer_base->timer0control);
}
int v2m_cfg_write(u32 devfn, u32 data)
{
/* Configuration interface broken? */
u32 val;
devfn |= SYS_CFG_START | SYS_CFG_WRITE;
val = readl(V2M_SYS_CFGSTAT);
writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
writel(data, V2M_SYS_CFGDATA);
writel(devfn, V2M_SYS_CFGCTRL);
do {
val = readl(V2M_SYS_CFGSTAT);
} while (val == 0);
return !!(val & SYS_CFG_ERR);
}
/* Use the ARM Watchdog System to cause reset */
void reset_cpu(void)
{
if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
printf("Unable to reboot\n");
}
void lowlevel_init(void)
{
}
ulong get_board_rev(void){
return readl((u32 *)SYS_ID);
}
#ifdef CONFIG_ARMV7_NONSEC
/* Setting the address at which secondary cores start from.
* Versatile Express uses one address for all cores, so ignore corenr
*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
/* The SYSFLAGS register on VExpress needs to be cleared first
* by writing to the next address, since any writes to the address
* at offset 0 will only be ORed in
*/
writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
writel(addr, CONFIG_SYSFLAGS_ADDR);
}
#endif

84
board/armltd/vexpress/vexpress_tc2.c
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@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Linaro
* Jon Medhurst <tixy@linaro.org>
*
* TC2 specific code for Versatile Express.
*/
#include <asm/armv7.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <common.h>
#include <linux/libfdt.h>
#define SCC_BASE 0x7fff0000
bool armv7_boot_nonsec_default(void)
{
#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT
return false;
#else
/*
* The Serial Configuration Controller (SCC) register at address 0x700
* contains flags for configuring the behaviour of the Boot Monitor
* (which CPUs execute from reset). Two of these bits are of interest:
*
* bit 12 = Use per-cpu mailboxes for power management
* bit 13 = Power down the non-boot cluster
*
* It is only when both of these are false that U-Boot's current
* implementation of 'nonsec' mode can work as expected because we
* rely on getting all CPUs to execute _nonsec_init, so let's check that.
*/
return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0;
#endif
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *fdt, struct bd_info *bd)
{
int offset, tmp, len;
const struct fdt_property *prop;
const char *cci_compatible = "arm,cci-400-ctrl-if";
#ifdef CONFIG_ARMV7_NONSEC
if (!armv7_boot_nonsec())
return 0;
#else
return 0;
#endif
/* Booting in nonsec mode, disable CCI access */
offset = fdt_path_offset(fdt, "/cpus");
if (offset < 0) {
printf("couldn't find /cpus\n");
return offset;
}
/* delete cci-control-port in each cpu node */
for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0;
tmp = fdt_next_subnode(fdt, tmp))
fdt_delprop(fdt, tmp, "cci-control-port");
/* disable all ace cci slave ports */
offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible",
cci_compatible, 20);
while (offset > 0) {
prop = fdt_get_property(fdt, offset, "interface-type",
&len);
if (!prop)
continue;
if (len < 4)
continue;
if (strcmp(prop->data, "ace"))
continue;
fdt_setprop_string(fdt, offset, "status", "disabled");
offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible",
cci_compatible, 20);
}
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

12
board/bachmann/ot1200/Kconfig
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@ -1,12 +0,0 @@
if TARGET_OT1200
config SYS_BOARD
default "ot1200"
config SYS_VENDOR
default "bachmann"
config SYS_CONFIG_NAME
default "ot1200"
endif

6
board/bachmann/ot1200/MAINTAINERS
View file

@ -1,6 +0,0 @@
BACHMANN ELECTRONIC OT1200 BOARD
M: Christian Gmeiner <christian.gmeiner@gmail.com>
S: Maintained
F: board/bachmann/ot1200
F: include/configs/ot1200.h
F: configs/ot1200*_defconfig

11
board/bachmann/ot1200/Makefile
View file

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
ifdef CONFIG_SPL_BUILD
obj-y := ot1200.o ot1200_spl.o
else
obj-y := ot1200.o
endif

20
board/bachmann/ot1200/README
View file

@ -1,20 +0,0 @@
U-Boot for the Bachmann electronic GmbH OT1200 devices
There are two different versions of the base board, which differ
in the way ethernet is done. The variant detection is done during
runtime based on the address of the found phy.
- "mr" variant
FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
port is always up and auto-negotiation is not possible.
- normal variant
FEC is connected to a normal phy and auto-negotiation is possible.
The variant name is part of the dtb file name loaded by u-boot. This
make is possible to boot the linux kernel and make use variant specific
devicetree (fixed-phy link).
In order to support different display resoltuions/sizes the OT1200 devices
are making use of EDID data stored in an i2c EEPROM.

154
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
View file

@ -1,154 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e05ac 0x00020030
DATA 4 0x020e05b4 0x00020030
DATA 4 0x020e0528 0x00020030
DATA 4 0x020e0520 0x00020030
DATA 4 0x020e0514 0x00020030
DATA 4 0x020e0510 0x00020030
DATA 4 0x020e05bc 0x00020030
DATA 4 0x020e05c4 0x00020030
DATA 4 0x020e056c 0x00020030
DATA 4 0x020e0578 0x00020030
DATA 4 0x020e0588 0x00020030
DATA 4 0x020e0594 0x00020030
DATA 4 0x020e057c 0x00020030
DATA 4 0x020e0590 0x00003000
DATA 4 0x020e0598 0x00003000
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0798 0x000C0000
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b000c 0x555A7974
DATA 4 0x021b0010 0xDB538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
DATA 4 0x021b0030 0x005A1023
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b001c 0x04088032
DATA 4 0x021b001c 0x0408803A
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803B
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x19308030
DATA 4 0x021b001c 0x19308038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0800 0xA1380003
DATA 4 0x021b4800 0xA1380003
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b4818 0x00022227
DATA 4 0x021b083c 0x434B0350
DATA 4 0x021b0840 0x034C0359
DATA 4 0x021b483c 0x434B0350
DATA 4 0x021b4840 0x03650348
DATA 4 0x021b0848 0x4436383B
DATA 4 0x021b4848 0x39393341
DATA 4 0x021b0850 0x35373933
DATA 4 0x021b4850 0x48254A36
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x00440044
DATA 4 0x021b4810 0x00440044
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4 0x020c4060 0x000000fb

360
board/bachmann/ot1200/ot1200.c
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@ -1,360 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
* Copyright (C) 2014, Bachmann electronic GmbH
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <env.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>
#include <asm/gpio.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};
static void setup_iomux_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
}
static iomux_v3_cfg_t const feature_pads[] = {
/* SD card detect */
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
/* eMMC soldered? */
MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
};
static void setup_iomux_features(void)
{
imx_iomux_v3_setup_multiple_pads(feature_pads,
ARRAY_SIZE(feature_pads));
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C2 - EEPROM */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
.gp = IMX_GPIO_NR(3, 16)
}
};
/* I2C3 - IO expander */
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
.gp = IMX_GPIO_NR(3, 17)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
static void setup_iomux_i2c(void)
{
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
}
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC33, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
int board_early_init_f(void)
{
ccgr_init();
gpr_init();
setup_iomux_uart();
setup_iomux_spi();
setup_iomux_i2c();
setup_iomux_features();
return 0;
}
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
gpio_direction_input(IMX_GPIO_NR(4, 5));
ret = gpio_get_value(IMX_GPIO_NR(4, 5));
} else {
gpio_direction_input(IMX_GPIO_NR(1, 5));
ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
}
return ret;
}
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
int board_mmc_init(struct bd_info *bis)
{
int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].max_bus_width = 8;
usdhc_cfg[1].max_bus_width = 4;
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return 0;
}
static void leds_on(void)
{
/* turn on all possible leds connected via GPIO expander */
i2c_set_bus_num(2);
pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
}
static void backlight_lcd_off(void)
{
unsigned gpio = IMX_GPIO_NR(2, 0);
gpio_direction_output(gpio, 0);
gpio = IMX_GPIO_NR(2, 3);
gpio_direction_output(gpio, 0);
}
int board_eth_init(struct bd_info *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
bus = fec_get_miibus(base, -1);
if (!bus)
return -EINVAL;
/* scan phy 0 and 5 */
phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
ret = -EINVAL;
goto free_bus;
}
/* depending on the phy address we can detect our board version */
if (phydev->addr == 0)
env_set("boardver", "");
else
env_set("boardver", "mr");
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret)
goto free_phydev;
return 0;
free_phydev:
free(phydev);
free_bus:
free(bus);
return ret;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
backlight_lcd_off();
leds_on();
#ifdef CONFIG_SATA
setup_sata();
#endif
return 0;
}
int checkboard(void)
{
puts("Board: "CONFIG_SYS_BOARD"\n");
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{NULL, 0},
};
#endif
int misc_init_r(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}

152
board/bachmann/ot1200/ot1200_spl.c
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@ -1,152 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015, Bachmann electronic GmbH
*/
#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
/* Configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
.dram_sdclk_0 = 0x00000028,
.dram_sdclk_1 = 0x00000028,
.dram_cas = 0x00000028,
.dram_ras = 0x00000028,
.dram_reset = 0x00000028,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 48 ohm */
.dram_sdodt0 = 0x00000028,
.dram_sdodt1 = 0x00000028,
/* SDQS[0:7]: Differential input, 48 ohm */
.dram_sdqs0 = 0x00000028,
.dram_sdqs1 = 0x00000028,
.dram_sdqs2 = 0x00000028,
.dram_sdqs3 = 0x00000028,
.dram_sdqs4 = 0x00000028,
.dram_sdqs5 = 0x00000028,
.dram_sdqs6 = 0x00000028,
.dram_sdqs7 = 0x00000028,
/* DQM[0:7]: Differential input, 48 ohm */
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
.dram_dqm2 = 0x00000028,
.dram_dqm3 = 0x00000028,
.dram_dqm4 = 0x00000028,
.dram_dqm5 = 0x00000028,
.dram_dqm6 = 0x00000028,
.dram_dqm7 = 0x00000028,
};
/* Configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* Disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 48 ohm */
.grp_addds = 0x00000028,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
.grp_ctlds = 0x00000028,
/* DATA[00:63]: Differential input, 48 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000028,
.grp_b1ds = 0x00000028,
.grp_b2ds = 0x00000028,
.grp_b3ds = 0x00000028,
.grp_b4ds = 0x00000028,
.grp_b5ds = 0x00000028,
.grp_b6ds = 0x00000028,
.grp_b7ds = 0x00000028,
};
static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
/* Width of data bus: 0=16, 1=32, 2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* Single chip select */
.ncs = 1,
.cs1_mirror = 0, /* war 0 */
.rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
.rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */ /* war 1 */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg micron_2gib_1600 = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 1,
};
static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x00260025,
.p0_mpwldectrl1 = 0x00270021,
.p1_mpwldectrl0 = 0x00180034,
.p1_mpwldectrl1 = 0x00180024,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x04380344,
.p0_mpdgctrl1 = 0x0330032C,
.p1_mpdgctrl0 = 0x0338033C,
.p1_mpdgctrl1 = 0x032C0300,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x3C2E3238,
.p1_mprddlctl = 0x3A2E303C,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x36384036,
.p1_mpwrdlctl = 0x442E4438,
};
static void ot1200_spl_dram_init(void)
{
mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
&micron_2gib_1600);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* configure MMDC for SDRAM width/size and per-model calibration */
ot1200_spl_dram_init();
}

31
board/barco/platinum/Kconfig
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@ -1,31 +0,0 @@
if TARGET_PLATINUM_PICON
config SYS_CPU
default "armv7"
config SYS_VENDOR
default "barco"
config SYS_BOARD
default "platinum"
config SYS_CONFIG_NAME
default "platinum_picon"
endif
if TARGET_PLATINUM_TITANIUM
config SYS_CPU
default "armv7"
config SYS_VENDOR
default "barco"
config SYS_BOARD
default "platinum"
config SYS_CONFIG_NAME
default "platinum_titanium"
endif

7
board/barco/platinum/MAINTAINERS
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@ -1,7 +0,0 @@
PLATINUM BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
F: board/barco/platinum/
F: include/configs/platinum.h
F: configs/platinum_picon_defconfig
F: configs/platinum_titanium_defconfig

12
board/barco/platinum/Makefile
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@ -1,12 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2014, Barco (www.barco.com)
obj-y := platinum.o
obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o
obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o
obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o
endif

219
board/barco/platinum/platinum.c
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@ -1,219 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, Barco (www.barco.com)
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <init.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include "platinum.h"
DECLARE_GLOBAL_DATA_PTR;
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
};
struct fsl_esdhc_cfg usdhc_cfg[] = {
{ USDHC3_BASE_ADDR },
};
void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
int board_ehci_hcd_init(int port)
{
return 0;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
unsigned sd3_cd = IMX_GPIO_NR(7, 0);
gpio_direction_input(sd3_cd);
return !gpio_get_value(sd3_cd);
}
return 0;
}
int board_mmc_init(struct bd_info *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
void board_init_gpio(void)
{
platinum_init_gpio();
}
void board_init_gpmi_nand(void)
{
setup_gpmi_nand();
}
void board_init_i2c(void)
{
platinum_setup_i2c();
}
void board_init_spi(void)
{
platinum_setup_spi();
}
void board_init_uart(void)
{
platinum_setup_uart();
}
void board_init_usb(void)
{
platinum_init_usb();
}
void board_init_finished(void)
{
platinum_init_finished();
}
int board_phy_config(struct phy_device *phydev)
{
return platinum_phy_config(phydev);
}
int board_eth_init(struct bd_info *bis)
{
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
board_init_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
board_init_spi();
board_init_i2c();
board_init_gpmi_nand();
board_init_gpio();
board_init_usb();
board_init_finished();
return 0;
}
int checkboard(void)
{
puts("Board: " CONFIG_PLATINUM_BOARD "\n");
return 0;
}
static const struct boot_mode board_boot_modes[] = {
/* NAND */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
/* 4 bit bus width */
{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
{ NULL, 0 },
};
int misc_init_r(void)
{
add_board_boot_modes(board_boot_modes);
return 0;
}

77
board/barco/platinum/platinum.h
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@ -1,77 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
#ifndef _PLATINUM_H_
#define _PLATINUM_H_
#include <miiphy.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
/* Defines */
#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
PAD_CTL_HYS)
#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL)
/* Prototypes */
int platinum_setup_enet(void);
int platinum_setup_i2c(void);
int platinum_setup_spi(void);
int platinum_setup_uart(void);
int platinum_phy_config(struct phy_device *phydev);
int platinum_init_gpio(void);
int platinum_init_usb(void);
int platinum_init_finished(void);
static inline void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
#endif /* _PLATINUM_H_ */

244
board/barco/platinum/platinum_picon.c
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@ -1,244 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, Barco (www.barco.com)
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/delay.h>
#include "platinum.h"
#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18)
#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13)
#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19)
#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2)
#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11)
#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13)
#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17)
#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20)
#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14)
#define GPIO_USB_RESET IMX_GPIO_NR(1, 5)
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const ecspi2_pads[] = {
MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
/* PHY nRESET */
iomux_v3_cfg_t const phy_reset_pad = {
MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart5_pads[] = {
MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const i2c0_mux_pads[] = {
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const i2c2_mux_pads[] = {
MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
/*
* This enet related pin-muxing and GPIO handling is done
* in SPL U-Boot. For early initialization. And to give the
* PHY some time to come out of reset before the U-Boot
* ethernet driver tries to access its registers via MDIO.
*/
int platinum_setup_enet(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned phy_reset = IMX_GPIO_NR(1, 19);
/* First configure PHY reset GPIO pin */
imx_iomux_v3_setup_pad(phy_reset_pad);
/* Reconfigure enet muxing while PHY is in reset */
gpio_direction_output(phy_reset, 0);
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
mdelay(10);
gpio_set_value(phy_reset, 1);
udelay(100);
/* set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int platinum_setup_i2c(void)
{
imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads,
ARRAY_SIZE(i2c0_mux_pads));
imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads,
ARRAY_SIZE(i2c2_mux_pads));
mdelay(10);
/* Disable i2c mux 0 */
gpio_direction_output(GPIO_I2C0_SEL0, 0);
gpio_direction_output(GPIO_I2C0_SEL1, 0);
gpio_direction_output(GPIO_I2C0_ENBN, 1);
/* Disable i2c mux 1 */
gpio_direction_output(GPIO_I2C2_SEL0, 0);
gpio_direction_output(GPIO_I2C2_SEL1, 0);
gpio_direction_output(GPIO_I2C2_ENBN, 1);
udelay(10);
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
/* Disable all leds */
i2c_set_bus_num(0);
i2c_reg_write(0x60, 0x05, 0x55);
return 0;
}
int platinum_setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
return 0;
}
int platinum_setup_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
return 0;
}
int platinum_phy_config(struct phy_device *phydev)
{
/* Use generic infrastructure, no specific setup */
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int platinum_init_gpio(void)
{
/* Reset FPGA's */
gpio_direction_output(GPIO_IP_NCONFIG, 0);
gpio_direction_output(GPIO_HK_NCONFIG, 0);
gpio_direction_output(GPIO_LS_NCONFIG, 0);
udelay(3);
gpio_set_value(GPIO_IP_NCONFIG, 1);
gpio_set_value(GPIO_HK_NCONFIG, 1);
gpio_set_value(GPIO_LS_NCONFIG, 1);
/* no dmd configuration yet */
return 0;
}
int platinum_init_usb(void)
{
/* Reset usb hub */
gpio_direction_output(GPIO_USB_RESET, 0);
udelay(100);
gpio_set_value(GPIO_USB_RESET, 1);
return 0;
}
int platinum_init_finished(void)
{
/* Enable led 0 */
i2c_set_bus_num(0);
i2c_reg_write(0x60, 0x05, 0x54);
return 0;
}

209
board/barco/platinum/platinum_titanium.c
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@ -1,209 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, Barco (www.barco.com)
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <miiphy.h>
#include <micrel.h>
#include <linux/delay.h>
#include "platinum.h"
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
/* non mounted spi nor flash for booting */
MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const ecspi2_pads[] = {
MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
/*
* This enet related pin-muxing and GPIO handling is done
* in SPL U-Boot. For early initialization. And to give the
* PHY some time to come out of reset before the U-Boot
* ethernet driver tries to access its registers via MDIO.
*/
int platinum_setup_enet(void)
{
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
mdelay(10);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
udelay(100);
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
return 0;
}
int platinum_setup_i2c(void)
{
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
return 0;
}
int platinum_setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
return 0;
}
int platinum_setup_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
return 0;
}
int platinum_phy_config(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int platinum_init_gpio(void)
{
/* Default GPIO's */
/* Toggle CONFIG_n to reset fpga on every boot */
gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
/* Need delay >=2uS */
udelay(3);
gpio_set_value(IMX_GPIO_NR(5, 18), 1);
/* Default pin 1,15 high - DLP_FLASH_WPZ */
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
return 0;
}
int platinum_init_usb(void)
{
return 0;
}
int platinum_init_finished(void)
{
return 0;
}

183
board/barco/platinum/spl_picon.c
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@ -1,183 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* Based on: gw_ventana_spl.c which is:
* Copyright (C) 2014 Gateworks Corporation
*/
#include <common.h>
#include <i2c.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
.dram_reset = 0x00020030,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 40 ohm */
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
/* SDQS[0:7]: Differential input, 40 ohm */
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
/* DQM[0:7]: Differential input, 40 ohm */
.dram_dqm0 = 0x00020030,
.dram_dqm1 = 0x00020030,
.dram_dqm2 = 0x00020030,
.dram_dqm3 = 0x00020030,
.dram_dqm4 = 0x00020030,
.dram_dqm5 = 0x00020030,
.dram_dqm6 = 0x00020030,
.dram_dqm7 = 0x00020030,
};
/* Configure MX6Q/DUAL mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
.grp_addds = 0x00000030,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
.grp_ctlds = 0x00000030,
/* DATA[00:63]: Differential input, 40 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
/* MT41K256M16HA-125 */
static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
.mem_speed = 1600,
.density = 4, /* 4Gbit */
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
/*
* Values from running the Freescale DDR stress tool via USB
*/
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x0044004E,
.p0_mpwldectrl1 = 0x001F0023,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x02480248,
.p0_mpdgctrl1 = 0x0210021C,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x42444444,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x36322C32,
};
static void spl_dram_init(int width)
{
struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width / 32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
#else
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
#endif
.walat = 0, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
}
/*
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* Setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* UART iomux */
board_early_init_f();
/* Setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Init DDR with 32bit width */
spl_dram_init(32);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/*
* Setup enet related MUXing early to give the PHY
* some time to wake-up from reset
*/
platinum_setup_enet();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

186
board/barco/platinum/spl_titanium.c
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@ -1,186 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* Based on: gw_ventana_spl.c which is:
* Copyright (C) 2014 Gateworks Corporation
*/
#include <common.h>
#include <i2c.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
.dram_reset = 0x00020030,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 40 ohm */
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
/* SDQS[0:7]: Differential input, 40 ohm */
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
/* DQM[0:7]: Differential input, 40 ohm */
.dram_dqm0 = 0x00020030,
.dram_dqm1 = 0x00020030,
.dram_dqm2 = 0x00020030,
.dram_dqm3 = 0x00020030,
.dram_dqm4 = 0x00020030,
.dram_dqm5 = 0x00020030,
.dram_dqm6 = 0x00020030,
.dram_dqm7 = 0x00020030,
};
/* Configure MX6Q/DUAL mmdc GRP io registers */
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
.grp_addds = 0x00000030,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
.grp_ctlds = 0x00000030,
/* DATA[00:63]: Differential input, 40 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
/* MT41J128M16JT-125 */
static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
/* Write leveling calibration determine */
.p0_mpwldectrl0 = 0x001f001f,
.p0_mpwldectrl1 = 0x001f001f,
.p1_mpwldectrl0 = 0x00440044,
.p1_mpwldectrl1 = 0x00440044,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x434b0350,
.p0_mpdgctrl1 = 0x034c0359,
.p1_mpdgctrl0 = 0x434b0350,
.p1_mpdgctrl1 = 0x03650348,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x4436383b,
.p1_mprddlctl = 0x39393341,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x35373933,
.p1_mpwrdlctl = 0x48254a36,
};
static void spl_dram_init(int width)
{
struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width / 32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
#else
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
#endif
.walat = 0, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
}
/*
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* Setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* UART iomux */
board_early_init_f();
/* Setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Init DDR with 32bit width */
spl_dram_init(32);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/*
* Setup enet related MUXing early to give the PHY
* some time to wake-up from reset
*/
platinum_setup_enet();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

12
board/barco/titanium/Kconfig
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@ -1,12 +0,0 @@
if TARGET_TITANIUM
config SYS_BOARD
default "titanium"
config SYS_VENDOR
default "barco"
config SYS_CONFIG_NAME
default "titanium"
endif

6
board/barco/titanium/MAINTAINERS
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@ -1,6 +0,0 @@
TITANIUM BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
F: board/barco/titanium/
F: include/configs/titanium.h
F: configs/titanium_defconfig

7
board/barco/titanium/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
obj-y := titanium.o

166
board/barco/titanium/imximage.cfg
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@ -1,166 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Projectiondesign AS
* Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* sd, nand
*/
BOOT_FROM nand
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
/* (differential input) */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
/* disable ddr pullups */
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
/* (differential input) */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* Read data DQ Byte0-3 delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/*
* MDMISC mirroring interleaved (row/bank/col)
*/
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F

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board/barco/titanium/titanium.c
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@ -1,320 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nfc_pads,
ARRAY_SIZE(nfc_pads));
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
static void setup_iomux_enet(void)
{
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
udelay(1000 * 10);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
return 0;
}
#endif
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{ USDHC3_BASE_ADDR },
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
gpio_direction_input(IMX_GPIO_NR(7, 0));
return !gpio_get_value(IMX_GPIO_NR(7, 0));
}
return 0;
}
int board_mmc_init(struct bd_info *bis)
{
/*
* Only one USDHC controller on titianium
*/
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif
int board_phy_config(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_eth_init(struct bd_info *bis)
{
setup_iomux_enet();
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
setup_gpmi_nand();
return 0;
}
int checkboard(void)
{
puts("Board: Titanium\n");
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* NAND */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
/* 4 bit bus width */
{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
{ NULL, 0 },
};
#endif
int misc_init_r(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}

15
board/broadcom/bcm23550_w1d/Kconfig
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@ -1,15 +0,0 @@
if TARGET_BCM23550_W1D
config SYS_BOARD
default "bcm23550_w1d"
config SYS_VENDOR
default "broadcom"
config SYS_SOC
default "bcm235xx"
config SYS_CONFIG_NAME
default "bcm23550_w1d"
endif

6
board/broadcom/bcm23550_w1d/MAINTAINERS
View file

@ -1,6 +0,0 @@
BCM23550_W1D BOARD
M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm23550_w1d/
F: include/configs/bcm23550_w1d.h
F: configs/bcm23550_w1d_defconfig

5
board/broadcom/bcm23550_w1d/Makefile
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@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
obj-y += bcm23550_w1d.o

125
board/broadcom/bcm23550_w1d/bcm23550_w1d.c
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@ -1,125 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <common.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <env.h>
#include <mmc.h>
#include <asm/kona-common/kona_sdhci.h>
#include <asm/kona-common/clk.h>
#include <asm/arch/sysmap.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <g_dnl.h>
#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
#define SECWATCHDOG_SDOGCR_EN_SHIFT 27
#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
#define SECWATCHDOG_SDOGCR_LD_SHIFT 0
#ifndef CONFIG_USB_SERIALNO
#define CONFIG_USB_SERIALNO "1234567890"
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* board_init - early hardware init
*/
int board_init(void)
{
printf("Relocation Offset is: %08lx\n", gd->reloc_off);
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
clk_init();
return 0;
}
/*
* misc_init_r - miscellaneous platform dependent initializations
*/
int misc_init_r(void)
{
return 0;
}
/*
* dram_init - sets uboots idea of sdram size
*/
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
#ifdef CONFIG_MMC_SDHCI_KONA
/*
* mmc_init - Initializes mmc
*/
int board_mmc_init(struct bd_info *bis)
{
int ret = 0;
/* Register eMMC - SDIO2 */
ret = kona_sdhci_init(1, 400000, 0);
if (ret)
return ret;
/* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
ret = kona_sdhci_init(3, 400000, 0);
return ret;
}
#endif
#ifdef CONFIG_USB_GADGET
static struct dwc2_plat_otg_data bcm_otg_data = {
.regs_otg = HSOTG_BASE_ADDR
};
int board_usb_init(int index, enum usb_init_type init)
{
debug("%s: performing dwc2_udc_probe\n", __func__);
return dwc2_udc_probe(&bcm_otg_data);
}
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
debug("%s\n", __func__);
if (!env_get("serial#"))
g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
return 0;
}
int g_dnl_get_board_bcd_device_number(int gcnum)
{
debug("%s\n", __func__);
return 1;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
debug("%s\n", __func__);
return 0;
}
#endif

15
board/broadcom/bcm28155_ap/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_BCM28155_AP
config SYS_BOARD
default "bcm28155_ap"
config SYS_VENDOR
default "broadcom"
config SYS_SOC
default "bcm281xx"
config SYS_CONFIG_NAME
default "bcm28155_ap"
endif

6
board/broadcom/bcm28155_ap/MAINTAINERS
View file

@ -1,6 +0,0 @@
BCM28155_AP BOARD
M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm28155_ap/
F: include/configs/bcm28155_ap.h
F: configs/bcm28155_ap_defconfig

5
board/broadcom/bcm28155_ap/Makefile
View file

@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
obj-y += bcm28155_ap.o

132
board/broadcom/bcm28155_ap/bcm28155_ap.c
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@ -1,132 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <common.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <env.h>
#include <mmc.h>
#include <asm/kona-common/kona_sdhci.h>
#include <asm/kona-common/clk.h>
#include <asm/arch/sysmap.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <g_dnl.h>
#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
#define SECWATCHDOG_SDOGCR_EN_SHIFT 27
#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
#define SECWATCHDOG_SDOGCR_LD_SHIFT 0
#ifndef CONFIG_USB_SERIALNO
#define CONFIG_USB_SERIALNO "1234567890"
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* board_init - early hardware init
*/
int board_init(void)
{
printf("Relocation Offset is: %08lx\n", gd->reloc_off);
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
clk_init();
return 0;
}
/*
* misc_init_r - miscellaneous platform dependent initializations
*/
int misc_init_r(void)
{
/* Disable watchdog reset - watchdog unused */
writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) |
(0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) |
(4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) |
(0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT),
(SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET));
return 0;
}
/*
* dram_init - sets uboots idea of sdram size
*/
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
#ifdef CONFIG_MMC_SDHCI_KONA
/*
* mmc_init - Initializes mmc
*/
int board_mmc_init(struct bd_info *bis)
{
int ret = 0;
/* Register eMMC - SDIO2 */
ret = kona_sdhci_init(1, 400000, 0);
if (ret)
return ret;
/* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
ret = kona_sdhci_init(3, 400000, 0);
return ret;
}
#endif
#ifdef CONFIG_USB_GADGET
static struct dwc2_plat_otg_data bcm_otg_data = {
.regs_otg = HSOTG_BASE_ADDR
};
int board_usb_init(int index, enum usb_init_type init)
{
debug("%s: performing dwc2_udc_probe\n", __func__);
return dwc2_udc_probe(&bcm_otg_data);
}
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
debug("%s\n", __func__);
if (!env_get("serial#"))
g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
return 0;
}
int g_dnl_get_board_bcd_device_number(int gcnum)
{
debug("%s\n", __func__);
return 1;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
debug("%s\n", __func__);
return 0;
}
#endif

6
board/broadcom/bcm911360_entphn-ns/MAINTAINERS
View file

@ -1,6 +0,0 @@
BCM911360_ENTPHN-NS BOARD
M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
F: configs/bcm911360_entphn-ns_defconfig

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