Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected
offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
output fit before the 0x60000 offset in u-boot-rockchip-spi.bin.
=> sf probe
SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1442304 bytes read in 27 ms (50.9 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x160200
1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.
Using mmc read command to read 32 MiB data shows following improvement:
=> time mmc read 10000000 2000 10000
Before: time: 3.178 seconds
After: time: 0.402 seconds
This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Unfortunately the IRAM used to stash the bootstage records in TPL
becomes inaccessible after SPL runs. Presumably this is because of ATF
taking it over.
We could move the stash to another address in SPL, before passing it to
U-Boot proper. But it seems easier to wait until we have support for
standard passage[1] which should not be too far away.
For now, disable it in TPL and SPL.
[1] https://patchwork.ozlabs.org/project/uboot/cover/
20220117150428.1580273-1-sjg@chromium.org/
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
This board is useful for benchmarking overall U-Boot performance. Enable
the bootstage feature so we get a report.
Since this returns to the boot rom before finishing executing
board_init_r() in SPL, add a few bootstage calls so that we can collect
timing from TPL.
For the stash region, use a portion of SRAM, 64KB below the stack top.
This allows the TPL image to be up to nearly 120KB (it is typically about
64KB). SPL normally runs from SDRAM at 0, so can use the same stash
region.
Signed-off-by: Simon Glass <sjg@chromium.org>
We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This converts the following to Kconfig:
CONFIG_SPL_NS16550_MIN_FUNCTIONS
CONFIG_SYS_NS16550_MEM32
CONFIG_SYS_NS16550_PORT_MAPPED
CONFIG_SYS_NS16550_REG_SIZE
CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that
platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini <trini@konsulko.com>
The struct is only used to overlay the MMIO region, so the behavior is
the same. This obsoletes the Kconfig option for the number of ports.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
CONFIG_SYS_USB_OHCI_CPU_INIT
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_OHCI_SLOT_NAME
CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
Signed-off-by: Tom Rini <trini@konsulko.com>
The Rockpro64 has some GPIO leds so let's enable them so the
user gets some output in early boot.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR
- Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack
pointer directly, otherwise we use the common calculation.
- On some platforms that were using the standard calculation but did not
set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them.
- On a small number of platforms that were not subtracting
GENERATED_GBL_DATA_SIZE do so now via the standard calculation.
- CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most
board config header files.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SPL_BSS_MAX_SIZE
CONFIG_SPL_MAX_FOOTPRINT
Note that the da850evm platforms were violating the "only use one" rule
here, and so now hard-code their BSS limit.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SPL_PAD_TO
CONFIG_SPL_MAX_SIZE
CONFIG_TPL_PAD_TO
CONFIG_TPL_MAX_SIZE
Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the
existing places.
Signed-off-by: Tom Rini <trini@konsulko.com>
Set CONFIG_COUNTER_FREQUENCY according to COUNTER_FREQUENCY in
config header file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
[trini: Re-run migration]
Apple SoCs have an integrated NVMe controller that isn't connected
over a PCIe bus. In preparation for adding support for this NVMe
controller, split out the PCI support into its own file. This file
is selected through a new CONFIG_NVME_PCI Kconfig option, so do
a wholesale replacement of CONFIG_NVME with CONFIG_NVME_PCI.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on: Macbook Air M1
Tested-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SKIP_LOWLEVEL_INIT
CONFIG_SKIP_LOWLEVEL_INIT_ONLY
In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that we have consistent usage, migrate this symbol to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Enable the RNG on the Firefly, rock960 and RockPro64 devices
to enable KASLR on devices that support it.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Akash Gajjar <akash@openedev.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Commit c4cea2bbf9 ("rockchip: Enable building a SPI ROM image on bob")
added an alias spi1 referring to spi@ff1d0000, however there was already
an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and
having both aliases present broke booting from SPI flash for this board.
Remove the spi0 alias, set the default bus for SPI flash to 1, and
enable support for numbered aliases in SPL so that it uses the same bus
numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash
on the rockpro64 board.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bbf9 ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
This commit moves CONFIG_PREBOOT="usb start" to common/KConfig
for all boards also declaring USB_KEYBOARD.
Besides simplifying defconfig files, this also enables support for
board-specific CONFIG_PREBOOT for sunxi boards:
commit 37304aaf60 ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to
Kconfig") intended to support CONFIG_PREBOOT, but
include/configs/sunxi-common.h hardcodes preboot as part of internally
defined CONSOLE_STDIN_SETTINGS, silently ignoring any board-specific
CONFIG_PREBOOT.
Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Series-Cc: Jagan Teki <jagan@amarulasolutions.com>
Series-Cc: Lukasz Majewski <lukma@denx.de>
Series-Cc: Andre Przywara <andre.przywara@arm.com>
Enable USB3.0 Host support for RockPro64 boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
With video output enabled and USB keyboard supported there is no need
for serial console. So let initialize USB subsystem so keyboard connected to
board (either directly or via hub) can be used to interrupt autoboot.
U-Boot TPL 2020.07-rc3-00123-g52d6cbd1a7 (Jun 03 2020 - 17:34:20)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
256B stride
256B stride
lpddr4_set_rate: change freq to 400000000 mhz 0, 1
lpddr4_set_rate: change freq to 800000000 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2020.07-rc3-00123-g52d6cbd1a7 (Jun 03 2020 - 17:34:20 +0200)
Trying to boot from SPI
U-Boot 2020.07-rc3-00123-g52d6cbd1a7 (Jun 03 2020 - 17:34:20 +0200)
SoC: Rockchip rk3399
Reset cause: RST
Model: Pine64 RockPro64 v2.1
DRAM: 3.9 GiB
PMIC: RK808
MMC: mmc@fe310000: 2, mmc@fe320000: 1, sdhci@fe330000: 0
Loading Environment from SPI Flash... SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
In: serial
Out: vidconsole
Err: vidconsole
Model: Pine64 RockPro64 v2.1
Net: eth0: ethernet@fe300000
starting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3a0000: USB OHCI 1.0
Bus usb@fe3c0000: USB EHCI 1.00
Bus usb@fe3e0000: USB OHCI 1.0
Bus dwc3: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus dwc3: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3a0000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found
scanning bus usb@fe3e0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 1 USB Device(s) found
scanning bus dwc3 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Hit any key to stop autoboot: 0
=>
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Due to how the Makefile logic is we currently get DM_SPI support in SPL
enabled by having DM_SPI enabled for full U-Boot but not having
CONFIG_SPL_DM_SPI set. Add this missing option to boards that were
inadvertently making use of it.
Cc: Adam Ford <aford173@gmail.com>
Cc: Akash Gajjar <akash@openedev.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Chee Hong Ang <chee.hong.ang@intel.com>
Cc: Chin-Liang See <clsee@altera.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Klaus Goger <klaus.goger@theobroma-systems.com>
Cc: Levin Du <djw@t-chip.com.cn>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Luca Ceresoli <luca@lucaceresoli.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Suniel Mahesh <sunil@amarulasolutions.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Board has flash chip on board so let store U-Boot environment there.
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable CONFIG_PCI and CONFIG_NVME and related configs for the
ROCKPro64 board.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
USB stack uses DM so DM_KEYBOARD is needed to get USB keyboard working.
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
U-Boot has video output enabled so time to get keyboard working.
=> usb reset;usb tree
resetting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3a0000: USB OHCI 1.0
Bus usb@fe3c0000: USB EHCI 1.00
Bus usb@fe3e0000: USB OHCI 1.0
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3a0000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found
scanning bus usb@fe3e0000 for devices... 3 USB Device(s) found
scanning bus dwc3 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning usb for storage devices... 2 Storage Device(s) found
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
U-Boot Root Hub
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Hub (12 Mb/s, 100mA)
| ALCOR Generic USB Hub
|
+-3 Mass Storage (12 Mb/s, 200mA)
Kingston DT 101 G2 001478544887BB3157380157
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (5 Gb/s, 76mA)
ADATA ADATA USB Flash Drive 1520405012240002
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reference to commit that adds HDMI to other rk3399 boards:
commit 9778edae55 ("rockchip: Enable HDMI output on rk3399 board w/ HDMI")
Signed-off-by: Andrius Štikonas <andrius@stikonas.eu>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
