Commit graph

50410 commits

Author SHA1 Message Date
Tom Rini
f32a441b4a scripts/config_whitelist.txt: Resync
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-08 20:16:00 -05:00
Jagan Teki
a8eac0acdc mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfig
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
which is missing in below commit
"imx: mx6ull_14x14_evk: add plugin defconfig"
(sha1: b90ebf49bb)

Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-08 10:07:10 -05:00
Andrew F. Davis
4d82c4b53e am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASE
The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.

Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-01-08 08:31:46 -05:00
Andrew F. Davis
7410f1464e arm: mach-omap2: Fix secure file generation
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.

When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.

Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.

This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.

Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-01-08 08:31:33 -05:00
Jaehoon Chung
cf2a693864 arm: samsung: goni: use the driver model for max8998
Remove the "ifndef CONFIG_DM_I2C".
Instead, use the driver model for max8998.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-05 11:27:36 +09:00
Tom Rini
0ed06c7ee4 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2017-01-04 19:41:50 -05:00
Tom Rini
88c7da6275 Merge branch 'master' of git://git.denx.de/u-boot-spi 2017-01-04 19:41:23 -05:00
York Sun
4851278e30 powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig
Use Kconfig option SYS_PPC64 instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:56 -05:00
York Sun
7371774ab9 powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig
Use Kconfig option to select chassis version.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:55 -05:00
York Sun
9ec10107e1 powerpc: E6500: Move macro CONFIG_E6500 to Kconfig
Use Kconfig option E6500 and clean up existing usage.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:54 -05:00
York Sun
f43417ec97 powerpc: mpc85xx: Remove unused ifdef in config header
After most config options are moved to Kconfig, the unused ifdef
or elif can be removed.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:53 -05:00
York Sun
22120f11e2 ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig
Use Kconfig to select DDR version instead of using config header.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:53 -05:00
York Sun
51370d5618 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:52 -05:00
York Sun
66e399b68d ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:49 -05:00
York Sun
63659ff317 powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
Use Kconfig to select errata workaround.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:46 -05:00
York Sun
c01e4a1a6f mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04 19:40:44 -05:00
York Sun
ba1b6fb5cc arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
Use Kconfig to select errata workaround.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:42 -05:00
York Sun
d26e34c4c4 fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04 19:40:41 -05:00
York Sun
a105503851 powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS
Remove this macro. It was added by e622d9ed but actually wasn't used.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:29 -05:00
York Sun
146ded4d25 powerpc: T2081QDS: Remove macro T2081QDS
Use TARGET_T2081QDS from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:28 -05:00
York Sun
86e0a31321 powerpc: T2080RDB: Remove macro CONFIG_T2080RDB
Use TARGET_T2080RDB from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:27 -05:00
York Sun
80d261881f powerpc: T2080QDS: Remove macro T2080QDS
Use TARGET_T2080QDS from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:26 -05:00
York Sun
f4f6694060 powerpc: T1040QDS: Remove macro CONFIG_T1040QDS
Use TARGET_T1040QDS from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:24 -05:00
York Sun
960286b6d9 powerpc: T1024RDB: Remove macro CONFIG_T1024RDB
Use TARGET_T1024RDB from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Get missing hunk in board/freescale/t102xrdb/ddr.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04 19:40:24 -05:00
York Sun
9082405d47 powerpc: T1023RDB: Remove macro CONFIG_T1023RDB
Use TARGET_T1023RDB from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:22 -05:00
York Sun
08a37fd13b powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014
Remove these SoCs from Kconfig because they don't have individual
configuration. Clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:20 -05:00
York Sun
90b80386ff crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig
Use Kconfig option to set little- or big-endian access to secure
boot and trust architecture.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:19 -05:00
York Sun
2c2e2c9e14 crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:17 -05:00
York Sun
53c953841b powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04 19:40:14 -05:00
York Sun
26e79b6547 powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig
Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:13 -05:00
York Sun
f8dee36034 powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig
Use Kconfig option for E500 and E500MC macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:12 -05:00
Jagan Teki
101000b771 mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print
SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.

Original behaviour:
-------------------
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB

After the fix:
-------------
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB

Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:56:44 +01:00
Vignesh R
b63b46313e spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:38:35 +01:00
Vignesh R
57897c13de spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.

So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:38:12 +01:00
Andre Przywara
eb77f5c9f6 sunxi: A64: enable SPL
Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We disable FEL support for now by making its compilation conditional
and disabling it for ARM64, as the code isn't ready yet.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:43 +01:00
Andre Przywara
3a2175696d sunxi: DRAM: fix H3 DRAM size display on aarch64
Fix the output of the DRAM size on AArch64 SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:43 +01:00
Andre Przywara
ed25486215 sunxi: H3/A64: fix non-ODT setting
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.

Reported-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:43 +01:00
Jens Kuske
1bc464be1f sunxi: A64: use H3 DRAM initialization code for A64 as well
The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
This refactoring does not change the code size for the existing H3 part.

[Andre: rework from #ifdefs to using socid parameters in static
        functions, minor fixes, merging in fixes from Jens]

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Philipp Tomsich
b55615908b sunxi: clocks: Use the correct pattern register for PLL11
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Jens Kuske
e013bead30 sunxi: H3: add DRAM controller single bit delay support
So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
well) only applied coarse delay line settings, with one delay value for
all the data lines in each byte lane and one value for the control lines.

Instead of setting the delays for whole bytes only allow setting it for
each individual bit. Also add support for address/command lane delays.

For the purpose of this patch the rules for the existing coarse settings
were just applied to the new scheme, so the actual register writes don't
change for the H3. Other SoCs will utilize this feature later properly.

With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from
2296 to 2344 Bytes.

[Andre: move delay parameters into macros to ease later sharing, use
	defines for numbers of delay registers, extend commit message]

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Jens Kuske
0eb6f9fd81 sunxi: H3: add and rename some DRAM contoller registers
The IOCR registers got renamed to BDLR to match the public
documentation of similar controllers.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Philipp Tomsich
dcb50090d7 sunxi: H3: Rework MBUS priority setup
So far the MBUS priority setup was done by writing "magic" values taken
from a DRAM controller register dump after a boot0 run.
By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP
kernel, we learned more about the actual meaning of those bits.
Add macros and refactor the setup function to make the MBUS setup much
more readable and meaningful.
The actual values used now are a transformation of the values used
before, which are assembled by the new code to result in the same register
writes. So this rework does not change any settings, also the code size
stays the same.

The respective source files in the BSP kernel had a proper GPL header,
so lifting this code and information into U-Boot is legal.

[Andre: provide a convenience macro to fit definitions on one line]

[1] https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Andre Przywara
52e3182b82 sunxi: provide default DRAM config for sun50i in Kconfig
To avoid enumerating the very same DRAM values in defconfig files
for each and every Allwinner A64 board out there, let's put some sane
default values in the Kconfig file.
Boards with different needs can override them at any time.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Andre Przywara
83843c9b3a sunxi: A64: do an RMR switch if started in AArch32 mode
The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.

By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch32, we differentiate between being
entered in 64-bit or 32-bit mode.
If in 64-bit mode, we proceed with the branch to reset, but in 32-bit
mode we trigger an RMR write to bring the core into AArch64/EL3 and
re-enter U-Boot at CONFIG_SYS_TEXT_BASE.
This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode,
so we can use the same start code for the SPL and the U-Boot proper.

We use the existing custom header (boot0.h) functionality, but restrict
the existing boot0 header reservation to the non-SPL build now. A SPL
wouldn't need such header anyway. This allows to have both options
defined and lets us use one for the SPL and the other for U-Boot proper.

Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original
ARM assembly code and instructions how to re-generate the encoded
version.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:42 +01:00
Andre Przywara
b5402d13d4 sunxi: introduce extra config option for boot0 header
The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
other boards. To allow alternative code to be inserted, we create
another, now function specific config symbol on top of it to simplify
later additions. No functional change at this time.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:41 +01:00
Andre Przywara
ce62e57fc5 ARM: boot0 hook: remove macro, include whole header file
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickly gets messy with this approach,
so let's just drop that intermediate macro and let the #include actually
insert the code directly.
This converts the callers and the callees, but doesn't change anything
at this point.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:41 +01:00
Andre Przywara
a5168a5900 armv8: move reset branch into boot hook
The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point, just refactoring to simplify
upcoming patches.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:41 +01:00
Andre Przywara
8ed02bc2d9 armv8: add simple sdelay implementation
The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:41 +01:00
Andre Przywara
11e1479b9e SPL: make struct spl_image 64-bit safe
Since entry_point and load_addr are addresses, they should be
represented as longs to cover the whole address space and to avoid
warning when compiling the SPL in 64-bit.
Also adjust debug prints to add the 'l' specifier, where needed.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:41 +01:00
Andre Przywara
2a6713b09b move UL() macro from armv8/mmu.h into common.h
The UL() macro is pretty useful in sharing constants between assembly
and C files while still being able to specify a type for C.
Move the macro from an armv8 specific header into a common header file
to be able to use it by arm code (for instance) as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:37:41 +01:00