mirror of
https://github.com/AsahiLinux/u-boot
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sunxi: A64: use H3 DRAM initialization code for A64 as well
The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
This refactoring does not change the code size for the existing H3 part.
[Andre: rework from #ifdefs to using socid parameters in static
functions, minor fixes, merging in fixes from Jens]
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Jens Kuske
Jagan Teki
parent
b55615908b
commit
1bc464be1f
7 changed files with 172 additions and 54 deletions
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@ -322,6 +322,7 @@ struct sunxi_ccm_reg {
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#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
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#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
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#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
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#define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */
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#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
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#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
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#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
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@ -13,4 +13,7 @@
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#include <asm/arch/cpu_sun4i.h>
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#endif
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#define SOCID_A64 0x1689
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#define SOCID_H3 0x1680
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#endif /* _SUNXI_CPU_H */
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@ -24,7 +24,7 @@
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#include <asm/arch/dram_sun8i_a33.h>
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#elif defined(CONFIG_MACH_SUN8I_A83T)
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#include <asm/arch/dram_sun8i_a83t.h>
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#elif defined(CONFIG_MACH_SUN8I_H3)
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#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
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#include <asm/arch/dram_sun8i_h3.h>
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#elif defined(CONFIG_MACH_SUN9I)
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#include <asm/arch/dram_sun9i.h>
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@ -15,7 +15,8 @@
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struct sunxi_mctl_com_reg {
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u32 cr; /* 0x00 control register */
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u8 res0[0xc]; /* 0x04 */
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u8 res0[0x8]; /* 0x04 */
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u32 tmr; /* 0x0c (unused on H3) */
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u32 mcr[16][2]; /* 0x10 */
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u32 bwcr; /* 0x90 bandwidth control register */
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u32 maer; /* 0x94 master enable register */
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@ -32,7 +33,9 @@ struct sunxi_mctl_com_reg {
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u32 swoffr; /* 0xc4 */
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u8 res2[0x8]; /* 0xc8 */
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u32 cccr; /* 0xd0 */
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u8 res3[0x72c]; /* 0xd4 */
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u8 res3[0x54]; /* 0xd4 */
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u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
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u8 res4[0x6cc]; /* 0x134 */
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u32 protect; /* 0x800 */
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};
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@ -81,7 +84,8 @@ struct sunxi_mctl_ctl_reg {
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u32 rfshtmg; /* 0x90 refresh timing */
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u32 rfshctl1; /* 0x94 */
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u32 pwrtmg; /* 0x98 */
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u8 res3[0x20]; /* 0x9c */
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u8 res3[0x1c]; /* 0x9c */
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u32 vtfcr; /* 0xb8 (unused on H3) */
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u32 dqsgmr; /* 0xbc */
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u32 dtcr; /* 0xc0 */
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u32 dtar[4]; /* 0xc4 */
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@ -50,4 +50,5 @@ obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
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obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
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obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
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obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
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obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o
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endif
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@ -217,7 +217,7 @@ done:
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}
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#endif
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#ifdef CONFIG_MACH_SUN8I_A33
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#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
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void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
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{
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struct sunxi_ccm_reg * const ccm =
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@ -13,6 +13,7 @@
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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#include <linux/kconfig.h>
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/*
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@ -42,30 +43,6 @@ static inline int ns_to_t(int nanoseconds)
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
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}
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static u32 bin_to_mgray(int val)
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{
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static const u8 lookup_table[32] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
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0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
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0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
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0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
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};
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return lookup_table[clamp(val, 0, 31)];
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}
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static int mgray_to_bin(u32 val)
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{
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static const u8 lookup_table[32] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
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0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
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0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
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0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
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};
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return lookup_table[val & 0x1f];
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}
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static void mctl_phy_init(u32 val)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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@ -148,13 +125,13 @@ inline void mbus_configure_port(u8 port,
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mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
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MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
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static void mctl_set_master_priority(void)
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static void mctl_set_master_priority_h3(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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/* enable bandwidth limit windows and set windows size 1us */
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writel(0x00010190, &mctl_com->bwcr);
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writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
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/* set cpu high priority */
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writel(0x00000001, &mctl_com->mapr);
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@ -173,7 +150,46 @@ static void mctl_set_master_priority(void)
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MBUS_CONF(DE_CFD, true, HIGH, 0, 1024, 288, 64);
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}
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static void mctl_set_timing_params(struct dram_para *para)
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static void mctl_set_master_priority_a64(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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/* enable bandwidth limit windows and set windows size 1us */
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writel(399, &mctl_com->tmr);
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writel((1 << 16), &mctl_com->bwcr);
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/* Port 2 is reserved per Allwinner's linux-3.10 source, yet they
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* initialise it */
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MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
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MBUS_CONF( GPU, false, HIGH, 0, 1536, 1400, 256);
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MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
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MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100);
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MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
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MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0);
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MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
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MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
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MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048);
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MBUS_CONF(DE_CFD, true, HIGH, 0, 1280, 144, 64);
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writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
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}
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static void mctl_set_master_priority(uint16_t socid)
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{
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switch (socid) {
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case SOCID_H3:
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mctl_set_master_priority_h3();
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return;
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case SOCID_A64:
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mctl_set_master_priority_a64();
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return;
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}
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}
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static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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@ -254,7 +270,31 @@ static void mctl_set_timing_params(struct dram_para *para)
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writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
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}
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static void mctl_zq_calibration(struct dram_para *para)
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static u32 bin_to_mgray(int val)
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{
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static const u8 lookup_table[32] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
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0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
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0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
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0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
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};
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return lookup_table[clamp(val, 0, 31)];
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}
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static int mgray_to_bin(u32 val)
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{
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static const u8 lookup_table[32] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
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0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
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0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
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0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
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};
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return lookup_table[val & 0x1f];
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}
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static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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@ -324,7 +364,7 @@ static void mctl_set_cr(struct dram_para *para)
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MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
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}
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static void mctl_sys_init(struct dram_para *para)
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static void mctl_sys_init(uint16_t socid, struct dram_para *para)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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@ -336,16 +376,30 @@ static void mctl_sys_init(struct dram_para *para)
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
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if (socid == SOCID_A64)
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clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
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udelay(10);
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clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
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udelay(1000);
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clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
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clrsetbits_le32(&ccm->dram_clk_cfg,
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CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
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CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
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CCM_DRAMCLK_CFG_UPD);
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if (socid == SOCID_A64) {
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clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
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clrsetbits_le32(&ccm->dram_clk_cfg,
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CCM_DRAMCLK_CFG_DIV_MASK |
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CCM_DRAMCLK_CFG_SRC_MASK,
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CCM_DRAMCLK_CFG_DIV(1) |
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CCM_DRAMCLK_CFG_SRC_PLL11 |
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CCM_DRAMCLK_CFG_UPD);
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} else if (socid == SOCID_H3) {
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clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
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clrsetbits_le32(&ccm->dram_clk_cfg,
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CCM_DRAMCLK_CFG_DIV_MASK |
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CCM_DRAMCLK_CFG_SRC_MASK,
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CCM_DRAMCLK_CFG_DIV(1) |
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CCM_DRAMCLK_CFG_SRC_PLL5 |
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CCM_DRAMCLK_CFG_UPD);
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}
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mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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@ -360,7 +414,7 @@ static void mctl_sys_init(struct dram_para *para)
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udelay(500);
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}
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static int mctl_channel_init(struct dram_para *para)
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static int mctl_channel_init(uint16_t socid, struct dram_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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@ -370,8 +424,8 @@ static int mctl_channel_init(struct dram_para *para)
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unsigned int i;
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mctl_set_cr(para);
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mctl_set_timing_params(para);
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mctl_set_master_priority();
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mctl_set_timing_params(socid, para);
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mctl_set_master_priority(socid);
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/* setting VTC, default disable all VT */
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clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
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@ -397,12 +451,18 @@ static int mctl_channel_init(struct dram_para *para)
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/* set DQS auto gating PD mode */
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setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
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/* dx ddr_clk & hdr_clk dynamic mode */
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clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
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if (socid == SOCID_H3) {
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/* dx ddr_clk & hdr_clk dynamic mode */
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clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
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/* dphy & aphy phase select 270 degree */
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clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
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(0x1 << 10) | (0x2 << 8));
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/* dphy & aphy phase select 270 degree */
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clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
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(0x1 << 10) | (0x2 << 8));
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} else if (socid == SOCID_A64) {
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/* dphy & aphy phase select ? */
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clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
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(0x0 << 10) | (0x3 << 8));
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}
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/* set half DQ */
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if (para->bus_width != 32) {
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@ -417,10 +477,17 @@ static int mctl_channel_init(struct dram_para *para)
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mctl_set_bit_delays(para);
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udelay(50);
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mctl_zq_calibration(para);
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if (socid == SOCID_H3) {
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mctl_h3_zq_calibration_quirk(para);
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mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
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PIR_DRAMINIT | PIR_QSGATE);
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mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
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PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
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} else if (socid == SOCID_A64) {
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clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
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mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
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PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
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}
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/* detect ranks and bus width */
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if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
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@ -458,7 +525,10 @@ static int mctl_channel_init(struct dram_para *para)
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udelay(10);
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/* set PGCR3, CKE polarity */
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writel(0x00aa0060, &mctl_ctl->pgcr[3]);
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if (socid == SOCID_H3)
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writel(0x00aa0060, &mctl_ctl->pgcr[3]);
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else if (socid == SOCID_A64)
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writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
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/* power down zq calibration module for power save */
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setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
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@ -512,6 +582,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0 }
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#define SUN50I_A64_DX_READ_DELAYS \
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{{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
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{ 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
|
||||
{ 16, 17, 17, 16, 16, 16, 16, 16, 16, 0, 0 }, \
|
||||
{ 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }}
|
||||
#define SUN50I_A64_DX_WRITE_DELAYS \
|
||||
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15 }, \
|
||||
{ 0, 0, 0, 0, 1, 1, 1, 1, 0, 10, 10 }, \
|
||||
{ 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
|
||||
{ 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
|
||||
#define SUN50I_A64_AC_DELAYS \
|
||||
{ 5, 5, 13, 10, 2, 5, 3, 3, \
|
||||
0, 3, 3, 3, 1, 0, 0, 0, \
|
||||
3, 4, 0, 3, 4, 1, 4, 0, \
|
||||
1, 1, 0, 1, 13, 5, 4 }
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
struct sunxi_mctl_com_reg * const mctl_com =
|
||||
|
|
@ -524,13 +610,30 @@ unsigned long sunxi_dram_init(void)
|
|||
.bus_width = 32,
|
||||
.row_bits = 15,
|
||||
.page_size = 4096,
|
||||
|
||||
#if defined(CONFIG_MACH_SUN8I_H3)
|
||||
.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
|
||||
.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
|
||||
.ac_delays = SUN8I_H3_AC_DELAYS,
|
||||
#elif defined(CONFIG_MACH_SUN50I)
|
||||
.dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
|
||||
.dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
|
||||
.ac_delays = SUN50I_A64_AC_DELAYS,
|
||||
#endif
|
||||
};
|
||||
/*
|
||||
* Let the compiler optimize alternatives away by passing this value into
|
||||
* the static functions. This saves us #ifdefs, but still keeps the binary
|
||||
* small.
|
||||
*/
|
||||
#if defined(CONFIG_MACH_SUN8I_H3)
|
||||
uint16_t socid = SOCID_H3;
|
||||
#elif defined(CONFIG_MACH_SUN50I)
|
||||
uint16_t socid = SOCID_A64;
|
||||
#endif
|
||||
|
||||
mctl_sys_init(¶);
|
||||
if (mctl_channel_init(¶))
|
||||
mctl_sys_init(socid, ¶);
|
||||
if (mctl_channel_init(socid, ¶))
|
||||
return 0;
|
||||
|
||||
if (para.dual_rank)
|
||||
|
|
@ -540,7 +643,13 @@ unsigned long sunxi_dram_init(void)
|
|||
udelay(1);
|
||||
|
||||
/* odt delay */
|
||||
writel(0x0c000400, &mctl_ctl->odtcfg);
|
||||
if (socid == SOCID_H3)
|
||||
writel(0x0c000400, &mctl_ctl->odtcfg);
|
||||
|
||||
if (socid == SOCID_A64) {
|
||||
setbits_le32(&mctl_ctl->vtfcr, 2 << 8);
|
||||
clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
|
||||
}
|
||||
|
||||
/* clear credit value */
|
||||
setbits_le32(&mctl_com->cccr, 1 << 31);
|
||||
|
|
|
|||
Loading…
Reference in a new issue