Commit graph

13449 commits

Author SHA1 Message Date
Sebastian Reichel
64272efdaf board: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2
GE B1x5v2 patient monitor series is similar to the CARESCAPE Monitor
series (GE Bx50). It consists of a carrier PCB used in combination
with a Congatec QMX6 SoM. This adds U-Boot support using device model
everywhere and SPL for memory initialization.

Proper configuration is provided as 'ge_b1x5v2_defconfig' and the
combined image u-boot-with-spi.imx can be flashed directly to 1024
byte offset to /dev/mtdblock0. Alternatively SPL and u-boot.imx can
be loaded separately via USB-OTG using e.g. imx_usb.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-11-01 16:01:40 +01:00
Sebastian Reichel
436ba4e0c7 imx6: allow usage of disable_ldb_di_clock_sources for CONFIG_MX6QDL
Allow using disable_ldb_di_clock_sources with just the combined
CONFIG_MX6QDL being enabled.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-11-01 15:58:47 +01:00
Teresa Remmet
0cc2a07879 board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support
Add support PHYTEC phyCORE-i.MX8MM SOM.

Supported features:
 - 2GB LPDDR4 RAM
 - 1x 1Gbit Ethernet
 - eMMC
 - external SD
 - debug UART3
 - watchdog
 - i2c eeprom

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-11-01 15:58:19 +01:00
Marek Vasut
08945cceff ARM: imx: Add support for the primary/secondary bmode to MX53
Implement the 'getprisec' subcommand of 'bmode' command for i.MX53 and
also the primary/secondary bootmode switching.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-11-01 15:57:48 +01:00
Lukasz Majewski
8a8ec73ebd dts: Provide LED DTS description for HSC and DDC imx53 devices
Those two LEDs are used to indicate U-Boot's boot stage.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-11-01 15:53:51 +01:00
Fabio Estevam
fc4e69f63f mx7ulp: clock: Align the PLL_USB frequency
The command 'clocks' shows the following output:

=> clocks
PLL_A7_SPLL         528 MHz
PLL_A7_APLL         529 MHz
PLL_USB           0 MHz

Add some extra spaces so that the PLL_USB information gets aligned with
the previous reported frequencies.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-11-01 15:53:29 +01:00
Fabio Estevam
538723e012 mx7ulp: clock: Remove unuseful information
The command 'clocks' shows the following output:

=> clocks
PLL_A7_SPLL         528 MHz
PLL_A7_APLL         529 MHz
PLL_USB           0 MHz

....

[do_mx7_showclocks] addr = 0x9FFB61F1

The last line is not useful at all, so just remove it.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-11-01 15:53:17 +01:00
Tim Harvey
9d41628863 imx: cpu: terminate line with CR if invalid temp sensor
Ensure we terminate the line with a CR if we get an invalid sensor device
or reading.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-11-01 15:52:58 +01:00
Jorge Ramirez-Ortiz
74a039403c mx6: peripheral clock from oscillator
In order to be able to run the I2C bus at 400Khz, the chip errata[1]
recommends that the peripheral clock runs out of the 24MHz oscillator.

Systems running I2C from OP-TEE before Linux executes - for example to
access a Secure Element [2] providing the cryptographic support - expect
this clock to be configured by the bootloader [3].

[1] IMX6SLCE Rev. 5, 02/2019, ERR007805.
[2] OP-TEE: support for NXP SE05X Plug and Trust (patch on the list).
[3] OP-TEE: check the imx_i2c.c driver (imx6 patch on the list).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-11-01 15:52:47 +01:00
Tom Rini
2c31d7e746 Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
2020-10-30 23:13:13 -04:00
Tom Rini
63d4607e03 of-platdata and dtoc improvements
sandbox SPL tests
 binman support for compressed sections
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAl+cXssRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreaYuAgAjG05oxt8a4DXhdzGuXBCbehZv2T7X5Lg
 2+i9uwyg3MkKWp0Spm2J+0flWs+1Bynw335hgNVgq+bh29sajOQz2BtgfDKFY+Aw
 D+D16YBEiEuIbIXLzSsv+ct1va83A3JmlxxoaJ7+ZvoN/5Z3ZvJIZ7F4AzmwlAFT
 5pOFgDEfVM4MYFU4R2wZAaJMnYKQrqR5Tvrxecc6OkhvWIgq7j3elE4xOuh2hL/L
 Bz/KM+4Eq+EUALG+quyEzd+gDKoPY2rNOojxS/lg7PRsN6S8engwE+LkcAkMaNG3
 uDVrTYsA8lCJJwso0in25fUy8sEYWaCSVr/82xfRJMWksPajubem7w==
 =9u1O
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-30oct20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

of-platdata and dtoc improvements
sandbox SPL tests
binman support for compressed sections
2020-10-30 15:24:30 -04:00
Jagan Teki
51656ae1d1 rockchip: Add Engicam PX30.Core C.TOUCH 2.0
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
d432975cec arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.

Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

SOM's like PX30.Core needs to mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
39c8b2c72a rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.

PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
cf1b86a3ae rockchip: px30: Add EVB_PX30 Kconfig help
TARGET_EVB_PX30 can be possible to use other px30 boards.

Add the help text for existing EVB, so-that the new boards
which are resuing this config option can mention their board
help text.

This would help to track which boards are using EVB_PX30 config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Michael Trimarchi
9946bfd4a0 arm64: dts: rockchip: Add Engicam PX30.Core SOM
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features

PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.

Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
282ad86aaa arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
dfec5a4ec0 arm64: dts: rockchip: Add chosen node for ROCK-Pi N8
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.

This will help to get serial out messages.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:01 +08:00
Stefan Agner
ee68c83d0a rockchip: dts: tinker: remove unnecessary node
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:06:13 +08:00
Stefan Agner
cfac752dad rockchip: dts: tinker: move i2c node to shared device tree
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.

Cc: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:06:13 +08:00
Simon Glass
4e28a259fd imx: mx6cuboxi: Disable thermal driver in SPL
This feature is incompatble with of-platdata since it uses the
U_BOOT_DEVICE() macro. With of-platdata the only devices permitted are
those created by dtoc.

The driver is not used in SPL anyway, so exclude it from that build.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-10-29 14:42:56 -06:00
Tom Rini
8d7f3fcb4a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
  (Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
2020-10-29 11:30:29 -04:00
Tom Rini
47754334b1 Xilinx changes for v2021.01-v2
common:
 - Add support for 64bit loadables from SPL
 
 xilinx:
 - Update documentation and record ownership
 - Enable eeprom board detection based legacy and fru formats
 - Add support for FRU format
 
 microblaze:
 - Optimize low level ASM code
 - Enable SPI/I2C
 - Enable distro boot
 
 zynq:
 - Add support for Zturn V5
 
 zynqmp:
 - Improve silicon detection code
 - Enable several kconfig options
 - Align DT with the latest state
 - Enabling security commands
 - Enable and support FPGA loading from SPL
 - Optimize xilinx_pm_request() calling
 
 versal:
 - Some DTs/Kconfig/defconfig alignments
 - Add binding header for clock and power
 
 zynq-sdhci:
 - Add support for tap delay programming
 
 zynq-spi/zynq-qspi:
 - Use clock framework for getting clocks
 
 xilinx-spi:
 - Fix some code issues (unused variables)
 
 serial:
 - Check return value from clock functions in pl01x
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCX5rH/QAKCRDKSWXLKUoM
 IRPAAJ9SvHR3w1qTc5W+Q5CWBUH5wJbNYQCaA4PpqZCdvyu1+nF5luL6JHhbDgw=
 =hOd7
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x
2020-10-29 11:30:15 -04:00
Tom Rini
eca57cafa5 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
  platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
2020-10-29 09:10:24 -04:00
Michal Simek
05af4834ad xilinx: Consolidate board_fit_config_name_match() for Xilinx platforms
Move board_fit_config_name_match() from Zynq/ZynqMP to common location.
This change will open a way to use it also by Microblaze and Versal.
Through this function there is a way to handle images with multiple DTBs.
For now match it with DEVICE_TREE as is done for Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-29 08:55:43 +01:00
Baruch Siach
a941226e00 arm: dts: armada-cp110-master: update nand-controller
Align node properties to kernel dts node.

The change of compatible property does not affect any currently
supported board.

Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-10-29 08:00:12 +01:00
Shmuel Hazan
e2eafaa18a arm: dts: armada-cp110-slave: add missing cps_nand
Align node properties to kernel dts node.

Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-10-29 08:00:12 +01:00
T Karthik Reddy
d93fbac512 arm64: zynqmp: Fix zynqmp mini qspi max frequency
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.

With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
T Karthik Reddy
0af9de9a90 arm64: zynqmp: Add support for SHA3 command
This patch adds support for SHA3 command. It takes data blob
as input and generates 48 bytes sha3 hash value.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
T Karthik Reddy
650d02ae77 arm64: zynqmp: Add support for RSA command
This patch adds support for RSA command, performs RSA encrypt &
RSA decrypt on data blob of key size.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Siva Durga Prasad Paladugu
8e4e914652 arm64: zynqmp: Add support for encryption and decryption on data blob
This patch adds support for encryption and decryption on a given data
blob using different key sources such as userkey(KUP), device key and
PUF key. Inorder to support this a new zynqmp command(zynqmp aes) has
been introduced.

Command:
zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr]\n"
	Encrypts or decrypts blob of data at src address and puts it\n"
	back to dstaddr using key and iv at keyaddr and ivaddr\n"
	respectively. keysrc values specifies from which source key\n"
	has to be used, it can be User/Device/PUF key. A value of 0\n"
	for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
	aesop value would specify the operationwhich can be 0 for\n"
	decrypt and 1 for encrypt(1) operation\n";

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Ashok Reddy Soma
90f06e9d20 arm64: versal: Update mini u-boot eMMC node parameters
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt.

Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write
commands are failing. Increase frequency to 200Mhz to fix this issue.

Add bus-width = <8>, non-removable and disable-wp properties to the node
as this is eMMC.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Alexandre GRIVEAUX
bd897a0789 ARM: zynq: Add Z-turn board V5
Adding Z-turn board V5 to resolve the change between:

"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031

At this time the S25FL128SAGNFI003 doesn't work because of bug:

*** Warning - spi_flash_probe_bus_cs() failed, using default environment

zynq-zturn was checked on V5 board, same error.

Maybe Z-turn board have the same problem (board with W25Q128BVFIG).

Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Tom Rini
c3d3104506 Revert "arch: arm/xen: add putc() for debugging"
This reverts commit 3a51b2a2c3.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23 09:16:07 -04:00
Michael Walle
4eecc6f1a1 armv8: layerscape: don't remove crypto node if just partially disabled
On all newer Layerscape SoCs, only the export-controlled ciphers of the
crypto module are disabled on non-E parts. Thus it doesn't make sense to
completely remove the node. Linux will figure out what is there and what
is not.

Just remove it for older SoCs, where the module is indeed completely
disabled on non-E parts.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Michael Walle
4ceb5c6db2 board: kontron: add sl28 support
Add basic support for the Kontron SMARC-sAL28 board. This includes just
the bare minimum to be able to bring up the board and boot linux.

For now, the Single and Dual PHY variant is supported. Other variants
will fall back to the basic variant.

In particular, there is no watchdog support for now. This means that you
have to disable the default watchdog, otherwise you'll end up in the
recovery bootloader. See the board README for details.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Razvan Ionut Cirjan
c760095adb net: lx2160a.c: Update to set ECx_PMUX precedence
As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.

Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Laurentiu Tudor
2a5bbb13cc pci: layerscape: add a way of specifying additional iommu mappings
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more static scenarios such as hardwired PCI endpoints
that get initialized later in the system setup) that would allow
two things:
 - for a SRIOV capable PCI EP identified by its B.D.F specify
   the maximum number of VFs that will ever be created for it
 - for hot-plug case, specify the B.D.F with which the device
   will show up on the PCI bus
More details can be found in the included documentation:
  arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 16:52:09 +05:30
Tom Rini
18261b8552 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- sun8i emac changes (Andre)
- SCP firmware (Samuel)
2020-10-22 20:32:02 -04:00
AKASHI Takahiro
3a51b2a2c3 arch: arm/xen: add putc() for debugging
This new function, xen_debug_putc(), is intended to be used to
enable CONFIG_DEBUG_UART on xen guest.

Please note that the underlying functionality in Xen is available
only when Xen is configured with !NDEBUG but is much simpler than
a generic HYPERVISOR_console_io().

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22 11:26:14 -04:00
Chia-Wei, Wang
611a28ce27 reset: ast2500: Use SCU for reset control
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.

This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.

The Kconfig description is also updated accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-22 11:26:14 -04:00
Robert Marko
cfec8d36ce IPQ40xx: Add PRNG support
Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
5297341ab1 IPQ40xx: Add support for MDIO
Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
96d6036671 IPQ40xx: Add SPI support
Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Holger Brunck
5d57dfad3f km: fix license string and compatible strings
As the ownership is now Hitachi Power Grids, change the license string
and adapt the compatible string in DTS files. For kmeter1.dts we
change it to "keymile,KMETER1" for now, as this is then compliant with
what is submitted to the linux kernel. All other boards don't have
a upstreamed version in linux mainline.

Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-22 09:54:54 -04:00
Tom Rini
b90daf2743 - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
 - Update MAINTAINERS for ARM STM STM32MP
 - Manage eth1addr on dh board with KS8851
 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1
 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl+QXvgACgkQ4rK92eCq
 k3Vbrgf/cBKPY9bS+lJVARgjDvIOdcXzpgH/F7dUlq+dzu/mCwhIBVKxM7/nXh5p
 RhfGET2fpMYY/41LkKza7AqOiGTXZG4pTmCGe1UHXrXeIPjinWG1LQjU/KOk6U4n
 681P9BZfTUXrVgzLBIUY1KBFVyMaiYfVjxU3MnA1vqrubymFbf+IpUt3OIegUDCp
 AjrTdj7sFEQ3nG/pgTyqFCwkl/MG53aB9MiaBBRxeGHYnDn0qzAEHSGqzSZZGhNl
 1ubJDF3K7w6Pj3MzIeA80M5r0fJoTy/qWcNH31psOpyQaHJ9NbPGjFYE6AkDPV4l
 27QN71AcRtCzlv1XQpblA98pa1bUYw==
 =Bl3G
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20201021' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
- Update MAINTAINERS for ARM STM STM32MP
- Manage eth1addr on dh board with KS8851
- Limit size of cacheable DDR in pre-reloc stage in stm32mp1
- Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-22 08:25:41 -04:00
Tom Rini
281d94b986 Merge branch '2021.01-rc' of https://github.com/lftan/u-boot
- fix Gen5 enable of EMAC via FPGA
2020-10-22 08:25:14 -04:00
Samuel Holland
e72a6be4fc sunxi: binman: Add support for including SCP firmware
Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a
System Control Processor, or SCP. ARM Trusted Firmware (ATF)
communicates with the SCP over SCPI to implement the PSCI system
suspend, shutdown and reset functionality. Currently, SCP firmware is
optional; the system will boot and run without it, but system suspend
will be unavailable.

Since all communication with the SCP is mediated by ATF, the only thing
U-Boot needs to do is load the firmware into SRAM. The SCP firmware
occupies the last 16KiB of SRAM A2, immediately following ATF.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
68158d59d2 sunxi: binman: Update FIT component descriptions
Since commit d879616e9e ("spl: fit: simplify logic for FDT loading for
non-OS boots"), the SPL looks at the "os" properties of FIT images to
determine where to append the FDT.

The "os" property of the "firmware" image also determines how to execute
the next stage of the boot process, as in 1d3790905d ("spl: atf:
introduce spl_invoke_atf and make bl31_entry private"). For this reason,
the next stage must be specified in "firmware", not in "loadables".

To support this additional functionality, and to properly model the boot
process, where ATF runs before U-Boot, add the "os" properties and swap
the firmware/loadable images in the FIT image.

Since this description was copied as an example in commit 70248d6a2916
("binman: Support generating FITs with multiple dtbs"), update those
examples as well for correctness and consistency.

Acked-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
827c420c40 sunxi: binman: Use a macro for the BL31 load address
This consolidates the SoC-specific part at the top of the file to avoid
cluttering it up with preprocessor conditions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
6b7c7ed80a sunxi: binman: Provide a default BL31 filename
Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use
binman"), if the BL31 environment variable was not defined, the firmware
would be loaded from a file "bl31.bin" in the current directory. Restore
that behavior by providing that as the default filename in case no entry
arg is provided, which will be the case if the environment variable is
unset.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
eafbdbb8eb sunxi: binman: Fix spacing between nodes
Nodes should have a blank line separating them from sibling nodes and
properties. Add the necessary lines.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Icenowy Zheng
0e3160b723 sunxi: make V3s DRAM initialization more proper
Previously, because we have no source code about the DRAM initialization
of V3s and missing some configurations (delays and MBUS QoS info), our
V3s DRAM initialization sequence is hacked from the H3 one.

As the SDK shipped with PineCube contains source code for V3s libdram,
we can retrieve these information from it and tweak some other magic
bits.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:40:28 +05:30
Patrick Delaunay
53de79fecc stm32mp: stm32prog: accept device without partition
When partitions are not available on a device the command stm32prog raises
an error but a device can have no partition to check in init_device()
and the command need to continue to the next part_id.

This patch correct an issue for ram0 target, when block_dev and mtd
are NULL.

For example with the simple flashlayout file:

Opt	Part	Name	Type	Device	Offset	Binary
-	0x01	fsbl	Binary	none	0x0	tf-a-serialboot.stm32
-	0x03	ssbl	Binary	none	0x0	u-boot.stm32
P	0x10	kernel	System	ram0	0xC2000000	uImage.bin
P	0x11	dtb	FileSytem	ram0	0xC4000000	stm32mp157f-ev1.dtb

Fixes: ffc405e63b ("stm32mp: stm32prog: add upport of partial update")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
6af78d03d3 arm: stm32: cleanup arch gpio.h
Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
  because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
  as its value is IP dependent and not arch dependent

No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca60b ("pinctrl: stm32: Add get_pins_count() ops").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
67f9f11f19 stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Ralph Siemsen
b0b08ce0b7 arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a8 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-21 11:45:54 +08:00
Tom Rini
adc0c39633 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted R-Car Gen3 updates
2020-10-20 08:02:53 -04:00
Lad Prabhakar
a3c1fd6393 clk: renesas: Import R8A774C0 clock tables from Linux 5.9
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
e9d91b82fe clk: renesas: Add R8A774E1 clock tables
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
54db9e8b8f clk: renesas: Add R8A774B1 clock tables
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
fc5e552209 arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
051f1499c9 arm: renesas: Add config option for R8A774C0 SoC
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Biju Das
aca749a90f arm: renesas: Add config option for R8A774E1 SoC
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
4e4c0e5e42 arm: renesas: Add config option for R8A774B1 SoC
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.

Also fixed the alignment issue on R8A774A1 config.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Chunfeng Yun
d6fa8db8b9 arm: dts: mt8512: add usb related nodes
Add usb, usb phy, and fixed regulators nodes

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Nicolas Ferre
db228c5b46 ARM: at91: Add chip ID for SAM9X60 SiP
SAM9X60 SiP (System in Package) are added for SoC identification.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
42f2dfa789 ARM: dts: sam9x60: use alphabetical order
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
c37d59a170 ARM: dts: sam9x60: use CCF compatibles for PMC
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
dbe10b6274 ARM: dts: sam9x60: use slow clock CCF compatible bindings
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
5dff16db16 ARM: dts: sam9x60: use u-boot,dm-pre-reloc
Use u-boot,dm-pre-reloc for slow xtal and main xtal.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
ffd204f347 ARM: dts: sam9x60ek: add clock frequencies to board file
Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Tom Rini
dadc1e3830 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2
2020-10-16 09:56:15 -04:00
Tom Rini
e1f306c07c arm: fsl-layerscape: Include device_compat.h in soc.c
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16 09:44:27 -04:00
Stefan Roese
7a78074c18 arm: octeontx: Select CLK
Clock support is needed for all Octeon TX/TX2 boards. This patch selects
CONFIG_CLK so that it is available.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16 13:55:04 +02:00
Tom Rini
9dc6aef8c9 Merge tag 'mmc-2020-10-14' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc_imx cleanup
- not send cm13 if send_status is 0.
- Add reinit API
- Add mmc HS400 for fsl_esdhc
- Several cleanup for fsl_esdhc
- Add ADMA2 for sdhci
2020-10-15 08:20:42 -04:00
Tom Rini
0f35d96bfd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Octeon TX: Add NAND driver (Suneel)
- Octeon TX: Add NIC driver driver (Suneel)
- Octeon TX2: Add NIC driver driver (Suneel)
- Armada 8040: Add iEi Puzzle-M80 board support (Luka)
- Armada A37xx SPI: Add support for CS-GPIO (George)
- Espressobin: Use Linux model/compatible strings (Andre)
- Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre)
- Armada A37xx: Small cleanup of config header (Pali)
2020-10-14 13:51:56 -04:00
Heinrich Schuchardt
684710dc33 arm: enable DM_RNG on QEMU by default
The EFI_RNG_PROTOCOL is needed for address randomization in Linux.
We should provide it by default on QEMU.

Reported-by: François Ozog <francois.ozog@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-14 11:16:34 -04:00
Andre Heider
f1a43c84a9 arm64: dts: a3720: add support for espressobin with populated emmc
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14 07:56:17 +02:00
Andre Heider
03bb6a9b1e arm64: dts: armada-3720-espressobin: split common parts to .dtsi
Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.

The dts itself is imported from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14 07:56:17 +02:00
Andre Heider
559ae35c96 arm64: dts: armada-3720-espressobin: use Linux model/compatible strings
Fix the actual board vendor and ease synching dts files from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Luka Kovacic
2ae2b8a2f2 arm: mvebu: Initial iEi Puzzle-M801 support
Add initial U-Boot support for the iEi Puzzle-M801 board based on the
Marvell Armada 88F8040 SoC.

Currently supported hardware:
1x USB 3.0
4x Gigabit Ethernet
2x SFP+ (with NXP PCA9555 and NXP PCA9544)
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x EPSON RX8010 RTC

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Tom Rini
9885313b9a Merge branch 'for-next' of https://github.com/lftan/u-boot 2020-10-12 07:55:17 -04:00
Yangbo Lu
dedd632f56 arm: dts: lx2160ardb: support eMMC HS400 mode
Add properties related to eMMC HS400 mode.

mmc-hs400-1_8v;
bus-width = <8>;

They had been already in kernel dts file since the first
lx2160ardb dts patch.

b068890 arm64: dts: add LX2160ARDB board support

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:07 +08:00
Ley Foon Tan
98c28a79b4 arm: dts: socfpga: arria10: Move to use generic handoff dtsi
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Dalon Westergreen
ed9c0823c5 arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Dalon Westergreen
5c0adb0a71 arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Ley Foon Tan
de84e2d8c9 arm: socfpga: mailbox: Add mailbox retry support
Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.

Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Ley Foon Tan
6a48f95c6b arm: socfpga: mailbox: Update mailbox response codes
Sync latest mailbox response codes from SDM firmware.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
f6dcf40759 arm: socfpga: mailbox: Support sending large mailbox command
Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
833230ed33 arm: socfpga: mailbox: Always read mailbox responses before returning status
Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
e3fca5072b arm: socfpga: mailbox: Refactor mailbox timeout event handling
Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chin Liang See
e2afbee50c arm: socfpga: soc64: Document down boot_scratch_cold register usage
Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
5edf94d921 arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
bd99fa59d5 arm: socfpga: agilex: Enable FPGA Full Reconfiguration support
Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
d2170168dd fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
2473e13bb8 arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
b3e2d9fccb arm: socfpga: soc64: Show reset state in SPL
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
d7a1ff40d6 arm: socfpga: soc64: Add SDM triggered warm reset bit mask
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
289ebe077a sysreset: socfpga: agilex: Enable sysreset support
Enable sysreset support for Agilex platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00