Commit graph

2258 commits

Author SHA1 Message Date
Breno Matheus Lima
821d8d32cb mx6sxsabresd: imximage.cfg: Handle the CONFIG_SECURE_BOOT case
Secure boot is not enabled in mx6sxsabresd imximage.cfg, add support
for it.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-07-19 20:14:50 +02:00
Anatolij Gustschin
d87b2486e6 arm: imx8: don't duplicate build_info()
Move build_info() to common place.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Anatolij Gustschin
64b5f46975 arm: imx8: factor out uart init code
New imx8 boards started adding duplicated UART init code.
Factor out this to common function sc_pm_setup_uart().

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Ye Li
06fc74102a mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR
clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:

	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock

To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)

	NIC0_DIV:      1
	NIC1_DIV:      0
	LCDIF_PCC_DIV: 6

APLL and APLL PFD0 settings:

	PFD0 FRAC:  27
	APLL MULT:  22
	APLL NUM:   1
	APLL DENOM: 20

This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Ye Li
9c1563e3fd mx7ulp: Select the SCG1 APLL PFD as a system clock source
Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Ye Li
285aea01d2 mx7ulp_evk: Change APLL and its PFD0 frequencies
To support HDMI display on EVK board, the LCDIF pix clock must be
25.2Mhz. Since the its PCC divider range is from 1-8, the max rate
of LCDIF PCC source clock is 201.6Mhz. This limits the source clock
must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs
are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source
is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK,
NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz
(25.2 * 12), with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Ye Li
b4bd5d71ae mx7ulp_evk: Update LPDDR3 script
Update LPDDR3 script with the changes below:
  -Update the precharge command to CMD=01 at the DDR initialization phase
  -remove unimplemented registers
   Write data bit delay --refer to the DDR_TRIM bits in
   IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn

Test:
  One EVK board passes overnight stress test.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Ye Li
72a9414bd4 mx7ulp: Fix APLL num and denom setting issue
For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
the NUM should always be less than the DENOM. So our setting violates the rule.

Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
is 318.9888Mhz, which also meet the DDR requirement.
To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Yangbo Lu
e37ac717d7 Convert to use fsl_esdhc_imx for i.MX platforms
Converted to use fsl_esdhc_imx for i.MX platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
2019-06-23 14:18:34 +08:00
Tom Rini
f643fb9f4c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- PCIe driver change to support DM model
- T2080QDS migrated to use PCIe DM model
2019-06-20 09:14:35 -04:00
Hou Zhiqiang
15311c85db powerpc: T208xQDS: Compile the legacy PCIe routines conditionally
Compile the legacy PCIe initialization reoutines only when DM_PCI
is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20 10:44:10 +05:30
Udit Agarwal
da70f766dd board/freescale/common: secure_boot: Set bootdelay to -2.
Uboot prompt must not be available while running
secure boot. TO ensure this  bootdelay must be set
to -2.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Vabhav Sharma
d90c7ac7a9 armv8: ls1046afrwy: Add support for LS1046AFRWY platform
LS1046AFRWY board supports LS1046A family SoCs. This patch
add base support for this board.
Board support's 4GB ddr memory, i2c, micro-click module,microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie interface.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Yuantian Tang
a1e126bf8d armv8: ls1028a: Add secure boot defconfig
Add secure boot defconfig for ls1028aqds and ls1028ardb boards.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Mian Yousaf Kaukab
de0f9ad1de board: lx2160a: fix fsl-mc status in fdt with bootefi
fsl-mc lazyapply command applies dpl from efi_exit_boot_services().
Status of fsl-mc node in working fdt is updated at this stage.
However, an efi application like grub may already have copied the fdt.
So the updates to fdt done at efi_exit_boot_services() may not be
visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply
command is used.

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Pankaj Bansal
1be0c66c79 board/fsl/layerscape: Modify the aliases names
when compiling dts file using DTC_FLAG='-@', the device tree compiler
reports these warnings:

Warning (alias_paths): /aliases: aliases property name must include
only lowercase and '-'

Fixed the node aliases to silence these warnings.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Fabio Estevam
e0e5f6da6e imx8mq_evk: Staticize when appropriate
Staticize 'spl_dram_init' and 'i2c_pad_info1' to fix the
following sparse warnings:

board/freescale/imx8mq_evk/spl.c:30:6: warning: symbol 'spl_dram_init' was not declared. Should it be static?
board/freescale/imx8mq_evk/spl.c:41:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static?

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-11 10:43:00 +02:00
Fabio Estevam
934f9a653c mx6sabresd: Remove U-Boot proper mmc initialization
After the conversion to DM there is no need to have mmc initialization
code inside U-Boot proper.

Remove the unneeded code.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-06-11 10:42:48 +02:00
Florin Chiculita
4dde343d7e board: fsl: lx2160ardb: invert AQR107 pins polarity
AQR107 PHYs interrupt pins are active-low, while the GIC expects a
level-high signal.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
f278a21749 armv8: ls1028aqds: Add support of LS1028AQDS
LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
353f36d96e armv8: ls1028ardb: Add support for LS1028ARDB
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Mario Six
42c9a494f1 mpc83xx: Get rid of CONFIG_SYS_LBC_*
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value
of either 0x00040000 or 0x00000000.

CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.

CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.

CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).

To simplify the configuration files, hardcode the setting of these
values for mpc83xx.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:33 +02:00
Mario Six
133ec60284 mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:33 +02:00
Mario Six
8a81bfd271 mpc83xx: Get rid of CONFIG_SYS_DDR_BASE
CONFIG_SYS_DDR_BASE is specific to mpc83xx an is always set to the same
value as CONFIG_SYS_SDRAM_BASE. Just use CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:33 +02:00
Mario Six
fe7d654d04 mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig
Migrate the BR/OR settings to Kconfig. These must be known at compile
time, so cannot be configured via DT.

Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:33 +02:00
Mario Six
21c1502a4a mpc83xx: Kconfig: Migrate HRCW to Kconfig
The HRCW (hardware reset configuration word) is a constant that must be
hard-coded into the boot loader image. So, it must be available at
compile time, and cannot be migrated to the DT mechanism, but has to be
kept in Kconfig.

Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:25 +02:00
Mario Six
ff3bb0c435 mpc83xx: Get rid of CONFIG_83XX_CLKIN
MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the
system clock. To migrate the architecture, we can replace
CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ.

To do this
* replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ
* set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all
  MPC83xx config files

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:06 +02:00
Mario Six
1cbc10c815 mpc83xx: Migrate legacy PCI options to Kconfig
The MPC83xx include files contain some settings of the PCI subsystem.

Migrate these to Kconfig until a proper DM PCI driver exists.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:51:40 +02:00
Mario Six
4cb06d3edf MPC8349ITX: Migrate to CONFIG_TARGET_MPC8349ITX
Use the proper CONFIG_TARGET_MPC8349ITX Kconfig option to replace the
CONFIG_MPC8349ITX ad-hoc config option.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:51:40 +02:00
Mario Six
8014c16201 MPC832XEMDS: Migrate to CONFIG_TARGET_MPC832XEMDS
Use the proper CONFIG_TARGET_MPC832XEMDS Kconfig option to replace the
CONFIG_MPC832XEMDS ad-hoc config option.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:51:40 +02:00
Mario Six
ddc935fc09 mpc83xx: Make distinct MPC8349EMDS_SDRAM board
The MPC8349EMDS config file contains config options to enable SDRAM
support. To keep this ability after the Kconfig migration, create a new
MPC8349EMDS_SDRAM board that enables the SDRAM support and remove the
SDRAM support from the original board.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:51:36 +02:00
Mario Six
16aaca214e mpc83xx: Make distinct MPC8313ERDB targets
MPC8313ERDB has the option of either enabling NOR or NAND boot in its
config file (by commenting out certain #ifdefs). To keep this ability
after migrating options to Kconfig, we introduce two MPC8313ERDB
configs: one for NOR, and one for NAND.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20 13:50:34 +02:00
Stefano Babic
04ba62115c imx8qxp_mek: drop warning due to unused variable
Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-04-25 19:16:24 +02:00
Peng Fan
0d331c035a imx: support i.MX8QM MEK board
Add i.MX8QM MEK board support.
Included a basic dts, enabled SPL FIT

Boot log as below:
U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
Normal Boot
Trying to boot from MMC2_2

U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)

CPU:   NXP i.MX8QM RevB A53 at 142933 MHz

Model: Freescale i.MX8QM MEK
Board: iMX8QM MEK
Build: SCFW 9330215b
Boot:  SD1
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:
Error: ethernet@5b040000 address not set.
eth-1: ethernet@5b040000
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
e5b8f7e665 imx8qxp: mek: enable dm-spl for pm
with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.

Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
7b48e2b05a Add missing space in comment
Spotted two missing spaces in comments.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-13 20:30:09 +02:00
Fabio Estevam
6574931732 imx8mq_evk: README: Make the underline marker fill the whole sentence
Let the underline marker "=" fill the whole sentence for better
readability.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-02 10:36:35 +02:00
Fabio Estevam
d3c8727bcf imx8mq_evk: README: Fix a typo in the destination path
The DDR firmware binaries should be copied to '$(srctree)', so fix
a typo.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-02 10:36:35 +02:00
Fabio Estevam
0adc3f8538 imx8mq_evk: README: Need to copy bl31.bin to U-Boot source tree
After building ATF it is needed to copy the generated bl31.bin file to
the U-Boot source tree.

Make this step explicit in the instructions.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-02 10:36:35 +02:00
Alison Wang
158097052a armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Pankaj Bansal
d296842c2d board: fsl: lx2160aqds: modify the phy fixup code
Now that we are representing the MDIO mux in LX2160AQDS board in
producer/consumer terms, the consumer nodes' has been changed.

Therefore, modify the device tree fixups according to change in device
tree.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Fabio Estevam
f6c3a9136b imx8mq_evk: Add myself as a co-maintainer
I would like to help maintaining this board.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
1e46d0bc6e mx6sabreauto: README: Adjust the binary name after DM conversion
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
6e2025b476 mx6sabresd: README: Adjust the binary name after DM conversion
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Baruch Siach
34808caf7a imx8mq_evk/README: fix DDR training firmware path
Remove a redundant directory level.

Reported-by: Ofer Heifetz <ofer.heifetz@valens.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Baruch Siach
57390c3a92 imx8mq_evk/README: add missing firmware extract step
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
250cf75424 mx6ul_14x14_evk: Simplify the PMIC register writes
There is no need to store the values written to the PMIC inside the
'reg' variable. Make it simpler by writing the values directly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Tom Rini
85887300ae Merge git://git.denx.de/u-boot-fsl-qoriq
- Enable DHCP as boot-source in distro boot for NXP layerscape
  platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet
2019-03-04 13:05:53 -05:00
Mian Yousaf Kaukab
730bd5658b board: ls1088a: fix fsl-mc search path
Path for fsl-mc node in kernel device-tree is /soc/fsl-mc whereas
in u-boot it is /fsl-mc.

Fix the incorrect search path to fix following error:
fdt_fixup_board_enet: ERROR: fsl-mc node not found in device tree
(error -1)

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 20:56:00 +05:30
Mian Yousaf Kaukab
4130780a83 board: ls1088a: fix dppa exit when using efi boot
Same issue for ls2080a was fixed by following patch:
b7b8410a8f ls2080: Exit dpaa only right before exiting U-Boot

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 20:56:00 +05:30