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mx7ulp_evk: Change APLL and its PFD0 frequencies

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To support HDMI display on EVK board, the LCDIF pix clock must be
25.2Mhz. Since the its PCC divider range is from 1-8, the max rate
of LCDIF PCC source clock is 201.6Mhz. This limits the source clock
must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs
are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source
is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK,
NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz
(25.2 * 12), with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2019-05-15 09:56:56 +00:00 committed by Stefano Babic
parent b4bd5d71ae
commit 285aea01d2
2 changed files with 26 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
board/freescale/mx7ulp_evk/imximage.cfg
View file

@ -43,8 +43,14 @@ CSF CONFIG_CSF_SIZE
*/
DATA 4 0x403f00dc 0x00000000
DATA 4 0x403e0040 0x01000020
DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
DATA 4 0x403e050c 0x8080801E
DATA 4 0x403e0508 0x00160000
DATA 4 0x403E0510 0x00000002
DATA 4 0x403E0514 0x00000005
DATA 4 0x403e0500 0x00000001
CHECK_BITS_SET 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808020
CHECK_BITS_SET 4 0x403e050c 0x00000040
DATA 4 0x403E0030 0x00000001
DATA 4 0x403e0040 0x11000020

20
board/freescale/mx7ulp_evk/plugin.S
View file

@ -13,10 +13,28 @@
ldr r2, =0x403e0000
ldr r3, =0x01000020
str r3, [r2, #0x40]
ldr r3, =0x01000000
str r3, [r2, #0x500]
ldr r3, =0x80808080
str r3, [r2, #0x50c]
ldr r3, =0x8080801E
ldr r3, =0x00160000
str r3, [r2, #0x508]
ldr r3, =0x00000002
str r3, [r2, #0x510]
ldr r3, =0x00000005
str r3, [r2, #0x514]
ldr r3, =0x00000001
str r3, [r2, #0x500]
ldr r3, =0x01000000
wait1:
ldr r4, [r2, #0x500]
and r4, r3
cmp r4, r3
bne wait1
ldr r3, =0x80808020
str r3, [r2, #0x50c]
ldr r3, =0x00000040