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mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0

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On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR
clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:

	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock

To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)

	NIC0_DIV:      1
	NIC1_DIV:      0
	LCDIF_PCC_DIV: 6

APLL and APLL PFD0 settings:

	PFD0 FRAC:  27
	APLL MULT:  22
	APLL NUM:   1
	APLL DENOM: 20

This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2019-05-15 09:57:01 +00:00 committed by Stefano Babic
parent 9c1563e3fd
commit 06fc74102a
2 changed files with 7 additions and 6 deletions
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6
board/freescale/mx7ulp_evk/imximage.cfg
View file

@ -46,11 +46,11 @@ DATA 4 0x403e0040 0x01000020
DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
DATA 4 0x403e0508 0x00160002
DATA 4 0x403E0510 0x00000002
DATA 4 0x403E0514 0x00000005
DATA 4 0x403E0510 0x00000001
DATA 4 0x403E0514 0x00000014
DATA 4 0x403e0500 0x00000001
CHECK_BITS_SET 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808020
DATA 4 0x403e050c 0x8080801B
CHECK_BITS_SET 4 0x403e050c 0x00000040
DATA 4 0x403E0030 0x00000001
DATA 4 0x403e0040 0x11000020

7
board/freescale/mx7ulp_evk/plugin.S
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include <config.h>
@ -20,9 +21,9 @@
str r3, [r2, #0x50c]
ldr r3, =0x00160002
str r3, [r2, #0x508]
ldr r3, =0x00000002
ldr r3, =0x00000001
str r3, [r2, #0x510]
ldr r3, =0x00000005
ldr r3, =0x00000014
str r3, [r2, #0x514]
ldr r3, =0x00000001
str r3, [r2, #0x500]
@ -34,7 +35,7 @@ wait1:
cmp r4, r3
bne wait1
ldr r3, =0x80808020
ldr r3, =0x8080801B
str r3, [r2, #0x50c]
ldr r3, =0x00000040