Commit graph

23807 commits

Author SHA1 Message Date
Shaohui Xie
b0615f0bd2 powerpc/t1040rdb: added a break in switch case
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Haijun.Zhang
e2c9bc5ea6 Powerpc/mpc8536DS: Increase SPI/SD uboot Image size to 768K
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
9307cbaba9 powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot size
U-boot binary size has been increased from 512KB to 768KB.

So update CONFIG_SYS_MONITOR_LEN to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
0938b6094e powerpc/mpc85xx:Avoid fix address of bootpg section
It is not necessary for bootpg to be present at text + 512KB.
With increase of u-boot size (768KB), bootpg section's address
cannot be fixed.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
18c0144542 board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
      - Add spl.c which defines board_init_f, board_init_r
      - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
c5dfe6ec58 board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
  - Add spl.c which defines board_init_f, board_init_r
  - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
89ad7be8e7 Makefile: Add support of CONFIG_SPL_FSL_PBL
Objective of this target to have concatenate binary having
 - SPL binary in PBL command format
 - U-boot binary

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
1eaa742d85 driver: Add support of image load for MMC & SPI in SPL
Add support of loading image, binary for MMC and SPI during SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
e278ddcd7f driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.

During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.

Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
5abed9c546 driver/ifc: define nand_spl_load_image() for SPL
nand_spl_load_image() can also be used for non TPL framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
6b3d588efe powerpc/mpc85xx:Disable non DDR LAWs before init_law
Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
651fcf6019 powerpc:Add support of SPL non-relocation
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.

To avoid relocation:
	- Move bss_section within SPL range
	- Modify relocate_code()

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
49efe85b35 powerpc/mpc85xx: Avoid hardcoding in SPL linker script
SPL linker has fix location of bootpg and reset vector with respect to text base.
It is not necessary to have fixed locations.

Avoid such hardcoding.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
b26df185c3 powerpc/mpc85xx: Move LAW_EN define outside of config
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.

So LAW_EN define outside of configs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
099b86b7e7 board/t1042rdb_pi: Disable CONFIG_QE and CONFIG_U_QE
T1042RDB_PI board does not have QE connector.

So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Prabhakar Kushwaha
169ee57138 powerpc/mpc85xx: Remove QE firmware copy from NAND
qe_init() does not use data copied from NAND. Thise code is not tested or
complied causing compilation error during NAND boot

So, remove QE firmware copy from NAND to ddr.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Zhao Qiang
6259e29134 T1040QDS/U-QE: Add u-qe support to t1040qds
Add u-qe support for t1040qds

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
5303a3dea9 mpc85xx: Add deep sleep support on T104xRDB
Add deep sleep support on T104xRDB platforms.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
48f6a9a2bf mpc85xx: Add deep sleep support on T1040QDS
Add deep sleep support on T1040QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
aade20046b mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
5aef4c86f3 mpc85xx: Add support for the supplement configuration unit register
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
349689b802 drivers/ddr: Fix possible out of bounds error
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Priyanka Jain
2ee6c52e22 driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons

-On SoCs that have FMAN-v3H  like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.

So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.

This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Nikhil Badola
896720ceb2 fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Prabhakar Kushwaha
55153d6c30 board/t104xrdb: Add support of CPLD
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Codrin Ciubotariu
d616fc58e5 powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch
T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Prabhakar Kushwaha
68b747397b powerpc/T1040: add mtdparts suppport for T104xRDB and T1040QDS
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Shengzhou Liu
4feac1c661 powerpc/T208xRDB: add mtdparts suppport
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Shengzhou Liu
9941cf781f powerpc/T208xQDS: add mtdparts suppport
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
vijay rai
f4c3917a3c powerpc/t104xrdb: Unification of T104xRDB header files
T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.

Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header file

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Prabhakar Kushwaha
613ab32c47 driver/mmc: fix compile warnings
Fix following compile warnings
fsl_esdhc_spl.c: In function 'mmc_boot':
fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable]
fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable]
fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
c3678b0937 powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.

Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Shengzhou Liu
22cbf96434 powerpc/t208xqds: fix nor chip selection when nand boot
NOR flash is on CS1 instead of CS2 when NAND boot.
So correct NOR chip selection to CS1 from CS2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Nikhil Badola
11856919f2 fsl/usb: Workaround for USB erratum-A007075
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
        P1010 rev 1.0
        B4860 rev 1.0, 2.0
        P4080 rev 2.0, 3.0

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
c60dee03c0 mpc85xx/T1040QDS_D4: Add DDR4 support
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Scott Wood
8d451a7129 powerpc/85xx: Fix e6500 L2 cache stash IDs
The value written to L2CSR1 didn't match the value written to the
device tree.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Codrin Ciubotariu
44afbbc0f0 net/phy: Fix PHY id for VSC8514
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
York Sun
e77224e2d8 driver/fsl_ifc: Add a function to finalize CS0 address binding
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-04-22 17:58:47 -07:00
Prabhakar Kushwaha
6b50f62cc4 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Zhao Qiang
59ff5d3306 t1040rdb/qe: add QE support for T1040RDB
add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
"include/configs/T1040RDB.h"

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Zhao Qiang
2a44efeb21 QE/U-QE: Add U-QE support
Modify code to adapt to both u-qe and qe.

U_QE is a kind of cutted QE.
the differences between U_QE and QE
	1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
	2. IMMR: have different immr base addr.
	3. iopin: U_QE doesn't need to config iopin.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Zhao Qiang
dcf1d774bf QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Aneesh Bansal
2d8db6d315 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB
Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDB

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Aneesh Bansal
ca4819df83 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
796a781001 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
fb4a2409b4 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
bea3cbb07f powerpc/mpc85xx: SECURE BOOT- Add NAND secure boot target for BSC9132QDS
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
f978f7c203 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
Add NOR, SPI and SD secure boot targets for BSC9132QDS.

Changes:
- Debug TLB entry is not required for Secure Boot Target.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
7efb4b5197 powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platforms
ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00