Add common x86 ASL files, taken from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
When booting Chrome OS images the command line is stored separately
from the kernel. Add a way to specify this address so that images boot
correctly.
Also add comments to the zimage.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 8 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
There is a lot of information in the setup block and it is quite hard to
decode manually. Add a 'zboot dump' command to decode it into a
human-readable format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the setup block is always obtained from the image
automatically. In some cases it can be useful to use a setup block
obtained elsewhere, e.g. if the image has already been unpacked. Add an
argument to support this and update the logic to use it if provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 7 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present it is not possible to tell from a script where the setup block
is, or where the image was loaded to. Add environment variables for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a subcommand that sets up the kernel ready for execution.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a subcommand that loads the kernel into the right places in memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust ZBOOT_STATE_INFO value to match the command order]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add a little subcommand that prints out where the kernel was loaded and
its setup pointer. Run it by default in the normal boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Split out the code that actually boots linux into a separate sub-command.
Add base_ptr to the state to support this.
Show an error if the boot fails, since this should not happen.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add subcommands to zboot. At present there is only one called 'start'
which does the whole boot. It is the default command so is optional.
Change the 's' string variable to const while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: reduce maxargs to 6 of 'zboot start' subcommand]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present if an error occurs while setting up the boot, interrupts are
left disabled. Move this call later in the sequence to avoid this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present U-Boot sets a loader type of 8 which means LILO version 8,
according to the spec. Update it to 0x80, which means U-Boot with no
particular version.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To help reduce the size and complexity of load_zimage(), move the code
that reads the kernel version into a separate function. Update
get_boot_protocol() to allow printing the 'Magic signature' message only
once, under control of its callers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use IS_ENABLED() instead of #ifdef in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the 'zboot' command does everything in one go. It would be
better if it supported sub-commands like bootm, so it is possible to
examine what will be booted before actually booting it.
In preparation for this, move the 'state' of the command into a struct.
This will allow it to be shared among multiple functions in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This header is missing a few of the newer features from the specification.
Add these as well as a link to the spec. Also use the BIT() macros where
appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
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Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.01
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a776 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile
and zynqmp.c to simplify if/endif logic in zynqmp.c.
This change is mostly done to be able to use CONFIG_IS_ENABLED macro and
obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync.
And removing one line from Topic Miami boards which is not needed because
symbol is not enabled via Kconfig.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It was protected just for SPL_OS_BOOT but this function is only called when
SPL_ATF is enabled that's why change macro name.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power
rails are incorrect. This patch corrects those values.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1
ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and
channel 2 is connected to J288 connector for QSFP1.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add read/write memory utilities for 16 and 32 bits. Add these
api's for both little and big endian systems similar to arm
architecture.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not source xilinx board Kconfig by other boards. These configs should be
available only when Xilinx platforms are selected.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add boolean input argument @no_map to helper function
fdtdec_add_reserved_memory() to add or not "no-map" property
for an added reserved memory node.
Property no-map is used by the Linux kernel to not not map memory
in its static memory mapping. It is needed for example for the|
consistency of system non-cached memory and to prevent speculative
accesses to some firewalled memory.
No functional change. A later change will update to OPTEE library to
add no-map property to OP-TEE reserved memory nodes.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present 64-bit sunxi boards use the Makefile to create a FIT, using
USE_SPL_FIT_GENERATOR. This is deprecated.
Update sunxi to use binman instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Linking a U-Boot larger than 1MB fails with PIE enabled:
u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
defined in .bss_start section in u-boot.
This extends the supported range by using adrp & add to load symbols
early while starting up.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
PIE requires a 4K aligned load address. If this is not met, trap
the startup sequence in a WFI loop rather than running into obscure
failures.
Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: André Przywara <andre.przywara@arm.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mention the requirement of 4K aligned load addresses in the
help section for the POSITION_INDEPENDENT option.
Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a missing memset to acpi_create_spcr().
The other acpi_create_xxxx() functions perform a memset on their
structures, acpi_create_spcr() does not and as a result the contents of
this table are partly uninitialized (and thus random after every reset).
Fixes: b288cd9600 ("x86: acpi: Generate SPCR table")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix the tags format in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Currently, the calculation for the length of the DSDT table includes any
bytes that are added for alignment, but those bytes are not initialized.
This is because the DSDT length is calculated after a call to
acpi_inc_align(). Split this up into the following sequence:
* acpi_inc()
* Calculate DSDT length
* acpi_align()
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The term eMMC is used inconsistently within the FSP devicetree
bindings (e-mmc and emmc), especially for "emmc-host-max-speed"
documentation and code disagree.
Change all eMMC instances within the FSP bindings to consistently
use "emmc". The term "emmc" is already used a lot within U-Boot,
while "e-mmc" is only used in the FSP bindings.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Since we have a driver for the reset controller, lets add the necessary node.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
There is already existing driver for SMEM so lets enable it for IPQ40xx as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.
Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16
Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK
was wrongly set.
Reported-by: Coverity 10045172
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1
The target interface CCM root index ranges [0,124], so the number
should be 125.
Reported-by: Coverity 18045
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
enable DTS support for keymile mpc83xx based boards.
get rid of compile warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Therefore done:
- add DTS for all mpc83xx based boards from keymile
mainly they are not mainlined to linux.
- add u-boot specific dtsi
- add stdout-path
- add missing ucc4 par_io definitions, which were
in board code, but not in linux DTS
- remove not used ethernet nodes
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Series-to: u-boot
Series-version: 3
Series-changes: 3
- rebase patchset to current mainline commit
c0192950df
- update defconfig files
Series-changes: 2
- add patch which fixes Codingstyle errors in drivers/qe
- add patch which converts the mpc83xx based boards from
keymile to DM_ETH
Cover-letter:
powerpc, mpc83xx: add DM_ETH support
This patch series adds DM ethernet support for mpc83xx based
keymile boards.
Travis build:
END
add DM support for parallel I/O ports on QUICC Engine Block
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Series-changes: 2
- remove RFC
- fixed Codingstyle errors, therefore new patch
powerpc, mpc83xx: fix codingstyle issues for qe_io.c
- moved DM part to drivers/pinctrl
Commit-notes:
Open questions / discussion:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This should be removed if all boards are converted to
DM/DTS.
- Unfortunately linux DTS does not use "pinctrl-"
properties, instead "pio-handle" properties.
Even worser old U-Boot code initializes all pins
defined in "const qe_iop_conf_t qe_iop_conf_tab[]"
table in board code. As linux does the same I decided
to also scan through all subnodes containing "pio-map"
property and initialize them too.
The proper solution would be to check for "pio-handle"
when a device is probed.
END
The following bugs are fixed:
* unaligned access in br_i32_decode()
* missing restore of global data pointer in UEFI selftest
* missing restore of global data pointer on RISC-V in UEfI subsystem
* efi_var_mem_notify_exit_boot_services() should not be __efi_runtime
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Merge tag 'efi-2020-10-rc5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5
The following bugs are fixed:
* unaligned access in br_i32_decode()
* missing restore of global data pointer in UEFI selftest
* missing restore of global data pointer on RISC-V in UEfI subsystem
* efi_var_mem_notify_exit_boot_services() should not be __efi_runtime
The linker sometimes creates PT_LOAD segments with length (p_filesz) zero
as described in https://man7.org/linux/man-pages/man5/elf.5.html. This
leads to build failures. We should ignore empty segments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add a generic fs_loader node to the K3 J7200 R5 common board dts
file and use it as the chosen firmware-loader so that it can be
used for loading various firmwares from a boot media/filesystem
in R5 SPL on K3 J7200 EVM.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.
The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.
Signed-off-by: Suman Anna <s-anna@ti.com>
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
