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https://github.com/AsahiLinux/u-boot
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x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
4d0c5762ad
commit
d9434a17e5
8 changed files with 443 additions and 5 deletions
108
arch/x86/include/asm/acpi/chromeos.asl
Normal file
108
arch/x86/include/asm/acpi/chromeos.asl
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@ -0,0 +1,108 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*/
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#ifdef CONFIG_CHROMEOS
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#define CONFIG_VBOOT_VBNV_OFFSET 0x26
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#include <asm/acpi/vbnv_layout.h>
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/* GPIO package generated at run time. */
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External (OIPG)
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Device (CRHW)
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{
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Name(_HID, EISAID("GGL0001"))
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Method(_STA, 0, Serialized)
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{
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Return (0xb)
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}
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Method(CHSW, 0, Serialized)
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{
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Name (WSHC, Package() { VBT3 })
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Return (WSHC)
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}
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Method(FWID, 0, Serialized)
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{
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Name (DIW1, "")
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ToString(VBT5, 63, DIW1)
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Name (DIWF, Package() { DIW1 })
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Return(DIWF)
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}
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Method(FRID, 0, Serialized)
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{
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Name (DIR1, "")
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ToString(VBT6, 63, DIR1)
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Name (DIRF, Package() { DIR1 })
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Return (DIRF)
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}
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Method(HWID, 0, Serialized)
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{
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Name (DIW0, "")
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ToString(VBT4, 255, DIW0)
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Name (DIWH, Package() { DIW0 })
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Return (DIWH)
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}
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Method(BINF, 0, Serialized)
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{
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Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
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Return (FNIB)
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}
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Method(GPIO, 0, Serialized)
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{
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Return (OIPG)
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}
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Method(VBNV, 0, Serialized)
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{
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Name(VNBV, Package() {
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// See src/vendorcode/google/chromeos/Kconfig
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// for the definition of these:
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CONFIG_VBOOT_VBNV_OFFSET,
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VBOOT_VBNV_BLOCK_SIZE
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})
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Return(VNBV)
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}
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Method(VDAT, 0, Serialized)
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{
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Name(TAD0,"")
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ToBuffer(CHVD, TAD0)
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Name (TADV, Package() { TAD0 })
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Return (TADV)
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}
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Method(FMAP, 0, Serialized)
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{
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Name(PAMF, Package() { VBT9 })
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Return(PAMF)
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}
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Method(MECK, 0, Serialized)
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{
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Name(HASH, Package() { MEHH })
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Return(HASH)
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}
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Method(MLST, 0, Serialized)
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{
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Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
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"GPIO", "VBNV", "VDAT", "FMAP", "MECK"
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})
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Return (TSLM)
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}
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}
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#include "ramoops.asl"
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#endif
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25
arch/x86/include/asm/acpi/cpu.asl
Normal file
25
arch/x86/include/asm/acpi/cpu.asl
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@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 Google LLC
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*/
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/* These come from the dynamically created CPU SSDT */
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External (\_PR.CNOT, MethodObj)
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/* Notify OS to re-read CPU tables */
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Method (PNOT)
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{
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\_PR.CNOT (0x81)
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}
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/* Notify OS to re-read CPU _PPC limit */
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Method (PPCN)
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{
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\_PR.CNOT (0x80)
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}
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/* Notify OS to re-read Throttle Limit tables */
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Method (TNOT)
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{
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\_PR.CNOT (0x82)
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}
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29
arch/x86/include/asm/acpi/cros_gnvs.asl
Normal file
29
arch/x86/include/asm/acpi/cros_gnvs.asl
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 Google LLC
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*/
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/* This is the ChromeOS specific ACPI information needed by
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* the mainboard's chromeos.asl
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*/
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VBT0, 32, // 0x000 - Boot Reason
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VBT1, 32, // 0x004 - Active Main Firmware
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VBT2, 32, // 0x008 - Active EC Firmware
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VBT3, 16, // 0x00c - CHSW
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VBT4, 2048, // 0x00e - HWID
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VBT5, 512, // 0x10e - FWID
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VBT6, 512, // 0x14e - FRID
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VBT7, 32, // 0x18e - active main firmware type
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VBT8, 32, // 0x192 - Recovery Reason
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VBT9, 32, // 0x196 - FMAP base address
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CHVD, 24576, // 0x19a - VDAT space filled by verified boot
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VBTA, 32, // 0xd9a - pointer to smbios FWID
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MEHH, 256, // 0xd9e - Management Engine Hash
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RMOB, 32, // 0xdbe - RAM oops base address
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RMOL, 32, // 0xdc2 - RAM oops length
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ROVP, 32, // 0xdc6 - pointer to RO_VPD
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ROVL, 32, // 0xdca - size of RO_VPD
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RWVP, 32, // 0xdce - pointer to RW_VPD
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RWVL, 32, // 0xdd2 - size of RW_VPD
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// 0xdd6
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141
arch/x86/include/asm/acpi/lpc.asl
Normal file
141
arch/x86/include/asm/acpi/lpc.asl
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@ -0,0 +1,141 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*/
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/* Intel LPC/eSPI Bus Device - 0:1f.0 */
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#include <asm/arch/iomap.h>
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Device (LPCB)
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{
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Name (_ADR, 0x001f0000)
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Name (_DDN, "LPC Bus Device")
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/* DMA Controller */
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Device (DMAC)
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{
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Name (_HID, EISAID("PNP0200"))
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x00, 0x00, 0x01, 0x20)
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IO (Decode16, 0x81, 0x81, 0x01, 0x11)
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IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
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IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
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DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
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})
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}
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/* Firmware Hub */
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Device (FWH)
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{
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Name (_HID, EISAID ("INT0800"))
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Name (_DDN, "Firmware Hub")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
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})
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}
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/* High Precision Event Timer */
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Device (HPET)
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{
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Name (_HID, EISAID ("PNP0103"))
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Name (_CID, 0x010CD041)
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Name (_DDN, "High Precision Event Timer")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
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})
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Method (_STA, 0)
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{
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Return (0xF)
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}
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}
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/* FPU */
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Device(MATH)
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{
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Name (_HID, EISAID("PNP0C04"))
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
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IRQNoFlags() { 13 }
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})
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}
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/* AT Interrupt Controller */
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Device (PIC)
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{
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Name (_HID, EISAID ("PNP0000"))
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Name (_DDN, "8259 Interrupt Controller")
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x20, 0x20, 0x01, 0x02)
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IO (Decode16, 0x24, 0x24, 0x01, 0x02)
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IO (Decode16, 0x28, 0x28, 0x01, 0x02)
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IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
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IO (Decode16, 0x30, 0x30, 0x01, 0x02)
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IO (Decode16, 0x34, 0x34, 0x01, 0x02)
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IO (Decode16, 0x38, 0x38, 0x01, 0x02)
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IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
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IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
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IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
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IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
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IO (Decode16, 0xac, 0xac, 0x01, 0x02)
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IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
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IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
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IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
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IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
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IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
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IRQNoFlags () { 2 }
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})
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}
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/* LPC device: Resource consumption */
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Device (LDRC)
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{
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 2)
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Name (_DDN, "Legacy Device Resources")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
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IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
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IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
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IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
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IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
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IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
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0x1, 0xff)
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})
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}
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/* Real Time Clock Device */
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Device (RTC)
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{
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Name (_HID, EISAID ("PNP0B00"))
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Name (_DDN, "Real Time Clock")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x70, 0x70, 1, 8)
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})
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}
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/* Timer */
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Device (TIMR)
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{
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Name (_HID, EISAID ("PNP0100"))
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Name (_DDN, "8254 Timer")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x40, 0x40, 0x01, 0x04)
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IO (Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags () {0}
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})
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}
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}
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21
arch/x86/include/asm/acpi/pci_osc.asl
Normal file
21
arch/x86/include/asm/acpi/pci_osc.asl
Normal file
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 Intel Corp.
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*/
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#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766"
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Scope (\_SB.PCI0) {
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Method (_OSC, 4) {
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/* Check for proper GUID */
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If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) {
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/* Let OS control everything */
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Return (Arg3)
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} Else {
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/* Unrecognized UUID */
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CreateDWordField (Arg3, 0, CDW1)
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Or (CDW1, 4, CDW1)
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Return (Arg3)
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}
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}
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}
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80
arch/x86/include/asm/acpi/pcr.asl
Normal file
80
arch/x86/include/asm/acpi/pcr.asl
Normal file
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@ -0,0 +1,80 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2018 Intel Corporation.
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*/
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#include <intelblocks/pcr.h>
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/*
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* Calculate PCR register base at specified PID
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* Arg0 - PCR Port ID
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*/
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Method (PCRB, 1, NotSerialized)
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{
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Return (Add (IOMAP_P2SB_BAR,
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ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
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}
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/*
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* Read a PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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*/
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Method (PCRR, 2, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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Return (DATA)
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}
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/*
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* AND a value with PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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* Arg2 - Value to AND
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*/
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Method (PCRA, 3, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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And (DATA, Arg2, DATA)
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/*
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* After every write one needs to read an innocuous register
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* to ensure the writes are completed for certain ports. This is done
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* for all ports so that the callers don't need the per-port knowledge
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* for each transaction.
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*/
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PCRR (Arg0, Arg1)
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}
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/*
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* OR a value with PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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* Arg2 - Value to OR
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*/
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Method (PCRO, 3, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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Or (DATA, Arg2, DATA)
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/*
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* After every write one needs to read an innocuous register
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* to ensure the writes are completed for certain ports. This is done
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* for all ports so that the callers don't need the per-port knowledge
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* for each transaction.
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*/
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PCRR (Arg0, Arg1)
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}
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32
arch/x86/include/asm/acpi/ramoops.asl
Normal file
32
arch/x86/include/asm/acpi/ramoops.asl
Normal file
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
|
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* Copyright (C) 2014 Google Inc.
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*/
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Scope (\_SB)
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{
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Device(RMOP)
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{
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Name (_HID, "GOOG9999")
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Name (_CID, "GOOG9999")
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Name (_UID, 1)
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Name (RBUF, ResourceTemplate()
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{
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Memory32Fixed (ReadWrite, 0, 0, MRES)
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})
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Method (_CRS)
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{
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CreateDwordField (^RBUF, ^MRES._BAS, RBAS)
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CreateDwordField (^RBUF, ^MRES._LEN, RLEN)
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Store (\RMOB, RBAS)
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Store (\RMOL, RLEN)
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Return (^RBUF)
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}
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Method(_STA, 0)
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{
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Return (0xB)
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}
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}
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}
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@ -6,9 +6,11 @@
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* Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
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*/
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Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
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#ifdef CONFIG_HAVE_ACPI_RESUME
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Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
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Name(\_S0, Package(){0x0,0x0,0x0,0x0})
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#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
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Name(\_S1, Package(){0x1,0x0,0x0,0x0})
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#else
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Name(\_S3, Package(){0x5,0x0,0x0,0x0})
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#endif
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Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
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Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
|
||||
Name(\_S4, Package(){0x6,0x0,0x0,0x0})
|
||||
Name(\_S5, Package(){0x7,0x0,0x0,0x0})
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue