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dts: powerpc: p1020rdb: Add eTSEC DT nodes

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P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Hou Zhiqiang 2020-09-21 14:59:05 +05:30 committed by Tom Rini
parent 993c104dbe
commit 247921f966
11 changed files with 273 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
arch/powerpc/dts/p1020-post.dtsi
View file

@ -53,10 +53,26 @@
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
};
/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {
};
};
/include/ "pq3-etsec2-grp2-0.dtsi"
/include/ "pq3-etsec2-grp2-1.dtsi"
/include/ "pq3-etsec2-grp2-2.dtsi"
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";

1
arch/powerpc/dts/p1020rdb-pc.dts
View file

@ -36,6 +36,7 @@
};
};
/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
&espi0 {

55
arch/powerpc/dts/p1020rdb-pc.dtsi Normal file
View file

@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&soc {
mdio@24000 {
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x1>;
};
tbi0: tbi-phy@11 {
device_type = "tbi-phy";
reg = <0x11>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};

1
arch/powerpc/dts/p1020rdb-pc_36b.dts
View file

@ -36,6 +36,7 @@
};
};
/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
&espi0 {

45
arch/powerpc/dts/p1020rdb-pd.dts
View file

@ -17,6 +17,51 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};
pci1: pcie@ffe09000 {

35
arch/powerpc/dts/pq3-etsec2-0.dtsi Normal file
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@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
};
ethernet@b0000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
reg = <0xb0000 0x1000>;
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
queue-group@b0000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000 0x1000>;
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
};
};

35
arch/powerpc/dts/pq3-etsec2-1.dtsi Normal file
View file

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x25000 0x1000 0xb1030 0x4>;
};
ethernet@b1000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
reg = <0xb1000 0x1000>;
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
queue-group@b1000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb1000 0x1000>;
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
};
};

35
arch/powerpc/dts/pq3-etsec2-2.dtsi Normal file
View file

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
mdio@26000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x26000 0x1000 0xb1030 0x4>;
};
ethernet@b2000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
reg = <0xb2000 0x1000>;
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
queue-group@b2000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb2000 0x1000>;
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
};
};

16
arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&enet0_grp2 {
queue-group@b4000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb4000 0x1000>;
interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
};
};

16
arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&enet1_grp2 {
queue-group@b5000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb5000 0x1000>;
interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
};
};

16
arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&enet2_grp2 {
queue-group@b6000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb6000 0x1000>;
interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
};
};