mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 07:04:28 +00:00
mpc83xx, keymile boards: enable DM_ETH and add DTS
enable DTS support for keymile mpc83xx based boards.
get rid of compile warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Therefore done:
- add DTS for all mpc83xx based boards from keymile
mainly they are not mainlined to linux.
- add u-boot specific dtsi
- add stdout-path
- add missing ucc4 par_io definitions, which were
in board code, but not in linux DTS
- remove not used ethernet nodes
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Series-to: u-boot
Series-version: 3
Series-changes: 3
- rebase patchset to current mainline commit
c0192950df
- update defconfig files
Series-changes: 2
- add patch which fixes Codingstyle errors in drivers/qe
- add patch which converts the mpc83xx based boards from
keymile to DM_ETH
Cover-letter:
powerpc, mpc83xx: add DM_ETH support
This patch series adds DM ethernet support for mpc83xx based
keymile boards.
Travis build:
END
This commit is contained in:
Heiko Schocher
parent
6e31c62a17
commit
7bdfe85929
32 changed files with 2694 additions and 139 deletions
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@ -101,34 +101,42 @@ config TARGET_IDS8313
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config TARGET_KMETER1
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bool "Support kmeter1"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_KMCOGE5NE
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bool "Support kmcoge5ne"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_KMTEGR1
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bool "Support kmtegr1"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_TUXX1
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bool "Support tuxx1"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_KMSUPX5
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bool "Support kmsupx5"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_TUGE1
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bool "Support tuge1"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_KMOPTI2
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bool "Support kmopti2"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_KMTEPR2
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bool "Support kmtepr2"
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select VENDOR_KM
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select KM_ENABLE_FULL_DM_DTS_SUPPORT
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config TARGET_TQM834X
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bool "Support TQM834x"
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@ -1,5 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
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dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
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dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
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dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
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dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
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dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
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dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
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dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
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dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
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@ -16,6 +22,8 @@ dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
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dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
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dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
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dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
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dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
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dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
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dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
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dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
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33
arch/powerpc/dts/km8309-uboot.dtsi
Normal file
33
arch/powerpc/dts/km8309-uboot.dtsi
Normal file
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@ -0,0 +1,33 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ABB PGGA 8309 U-Boot specific Device Tree Source parts
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*
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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*
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*/
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/ {
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cpus {
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u-boot,dm-pre-reloc;
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PowerPC,8309@0 {
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u-boot,dm-pre-reloc;
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};
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};
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chosen {
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stdout-path = &serial0;
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};
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};
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&qe {
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compatible = "fsl,qe", "simple-bus";
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};
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&soc {
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u-boot,dm-pre-reloc;
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};
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&serial0 {
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clock-frequency = <132000000>;
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u-boot,dm-pre-reloc;
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};
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67
arch/powerpc/dts/km8321-uboot.dtsi
Normal file
67
arch/powerpc/dts/km8321-uboot.dtsi
Normal file
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@ -0,0 +1,67 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ABB PGGA 8321 U-Boot specific Device Tree Source parts
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*
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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*
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*/
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/ {
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cpus {
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u-boot,dm-pre-reloc;
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PowerPC,8321@0 {
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u-boot,dm-pre-reloc;
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};
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};
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chosen {
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stdout-path = &serial0;
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};
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};
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&enet_piggy2 {
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status = "okay";
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};
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&qe {
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compatible = "fsl,qe", "simple-bus";
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};
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&serial0 {
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clock-frequency = <132000000>;
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u-boot,dm-pre-reloc;
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};
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&soc {
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u-boot,dm-pre-reloc;
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par_io@1400 {
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compatible = "fsl,mpc8360-par_io";
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u-boot,dm-pre-reloc;
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serial_pin@0 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@0 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@1 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@3 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@4 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@5 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@6 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@7 {
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u-boot,dm-pre-reloc;
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};
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};
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};
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220
arch/powerpc/dts/km8321.dtsi
Normal file
220
arch/powerpc/dts/km8321.dtsi
Normal file
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@ -0,0 +1,220 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ABB PGGA km8321 common ports Device Tree Source
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*
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8321@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <16384>; // L1, 16K
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i-cache-size = <16384>; // L1, 16K
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timebase-frequency = <66000000>;
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bus-frequency = <264000000>;
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clock-frequency = <528000000>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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soc: soc8321@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <264000000>;
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i2c0: i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,mpc8313-i2c","fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <100000>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <264000000>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8321-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8321-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8321-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8321-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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ipic: pic@700 {
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "fsl,pq2pro-pic", "fsl,ipic";
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interrupt-controller;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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par_io: par_io@1400 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1400 0x100>;
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ranges;
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device_type = "par_io";
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num-ports = <7>;
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qe_pio_d: gpio-controller@48 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x1448 0x18>;
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gpio-controller;
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};
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};
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};
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qe: qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0100000 0x00100000>;
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reg = <0xe0100000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <396000000>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x00010000 0x00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x4000>;
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};
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};
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/* Piggy2 (UCC4, MDIO 0x00, RMII) */
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enet_piggy2: ucc@3200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <4>;
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reg = <0x3200 0x200>;
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interrupts = <35>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk17";
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phy-handle = <&phy_piggy2>;
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phy-connection-type = "rmii";
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pio-handle = <&pio_ucc4>;
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};
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mdio: mdio@3320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3320 0x18>;
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compatible = "fsl,ucc-mdio";
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/* Piggy2 (UCC4, MDIO 0x00, RMII) */
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phy_piggy2: ethernet-phy@00 {
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <32 8 33 8>;
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interrupt-parent = <&ipic>;
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};
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bootcount@0x13ff8 {
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device_type = "bootcount";
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compatible = "u-boot,bootcount";
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reg = <0x13ff8 0x08>;
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};
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spi0: spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x4c0 0x40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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mode = "qe";
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#address-cells = <1>;
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#size-cells = <0>;
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pio-handle = <&pio_spi>;
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};
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};
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localbus: localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
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"simple-bus";
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reg = <0xe0005000 0xd8>;
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};
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};
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#include "km8321-uboot.dtsi"
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61
arch/powerpc/dts/km836x-uboot.dtsi
Normal file
61
arch/powerpc/dts/km836x-uboot.dtsi
Normal file
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@ -0,0 +1,61 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ABB PGGA km836x U-Boot specific Device Tree Source parts
|
||||
*
|
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
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*
|
||||
*/
|
||||
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/ {
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cpus {
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u-boot,dm-pre-reloc;
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PowerPC,8360@0 {
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u-boot,dm-pre-reloc;
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};
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};
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chosen {
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stdout-path = &serial0;
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};
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};
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&qe {
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compatible = "fsl,qe", "simple-bus";
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};
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&soc {
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u-boot,dm-pre-reloc;
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par_io@1400 {
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u-boot,dm-pre-reloc;
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serial_pin@0 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@0 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@1 {
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u-boot,dm-pre-reloc;
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};
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ucc_pin@3 {
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u-boot,dm-pre-reloc;
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||||
};
|
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ucc_pin@4 {
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u-boot,dm-pre-reloc;
|
||||
};
|
||||
ucc_pin@5 {
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u-boot,dm-pre-reloc;
|
||||
};
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ucc_pin@6 {
|
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u-boot,dm-pre-reloc;
|
||||
};
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||||
ucc_pin@7 {
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||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&serial0 {
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u-boot,dm-pre-reloc;
|
||||
};
|
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182
arch/powerpc/dts/km836x.dtsi
Normal file
182
arch/powerpc/dts/km836x.dtsi
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA km836x common ports Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8360@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; /* 32 bytes */
|
||||
i-cache-line-size = <32>; /* 32 bytes */
|
||||
d-cache-size = <32768>; /* L1, 32K */
|
||||
i-cache-size = <32768>; /* L1, 32K */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
bus-frequency = <0>; /* Filled in by U-Boot */
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
soc: soc8360@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8360-immr", "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00200000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;/* Filled in by U-Boot */
|
||||
|
||||
/* power management control module*/
|
||||
pmc: power@b00 {
|
||||
compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
|
||||
reg = <0xb00 0x100 0xa00 0x100>;
|
||||
interrupts = <80 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
i2c0: i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8313-i2c","fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <264000000>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,pq2pro-pic", "fsl,ipic";
|
||||
interrupt-controller;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
|
||||
par_io: par_io@1400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x1400 0x100>;
|
||||
ranges;
|
||||
compatible = "fsl,mpc8360-par_io";
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
|
||||
qe_pio_c: gpio-controller@30 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1430 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
qe: qe@100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0x100000 0x100000>;
|
||||
reg = <0x100000 0x480>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
brg-frequency = <0>; /* Filled in by U-Boot */
|
||||
bus-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x0000c000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0xc000>;
|
||||
};
|
||||
};
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <
|
||||
32 0x8 /* ucc1 */
|
||||
33 0x8 /* ucc2 */
|
||||
34 0x8 /* ucc3 */
|
||||
35 0x8 /* ucc4 */
|
||||
40 0x8 /* ucc1 */
|
||||
>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
spi0: spi@4c0 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "qe";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pio-handle = <&pio_spi>;
|
||||
};
|
||||
|
||||
bootcount@0x1bff8 {
|
||||
device_type = "bootcount";
|
||||
compatible = "u-boot,bootcount";
|
||||
reg = <0x1bff8 0x08>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus: localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "km836x-uboot.dtsi"
|
||||
22
arch/powerpc/dts/kmcoge5ne-uboot.dtsi
Normal file
22
arch/powerpc/dts/kmcoge5ne-uboot.dtsi
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
/delete-property/ ethernet1;
|
||||
/delete-property/ ethernet2;
|
||||
};
|
||||
};
|
||||
|
||||
&enet_switch {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&enet_mate {
|
||||
status = "disabled";
|
||||
};
|
||||
320
arch/powerpc/dts/kmcoge5ne.dts
Normal file
320
arch/powerpc/dts/kmcoge5ne.dts
Normal file
|
|
@ -0,0 +1,320 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA KMCOGE5ne Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km836x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "kmcoge5ne";
|
||||
compatible = "ABB,kmcoge5ne";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_admin;
|
||||
ethernet1 = &enet_mate;
|
||||
ethernet2 = &enet_switch;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
/* brg for hdlc clk */
|
||||
brg@0 {
|
||||
compatible = "fsl,mpc-brg";
|
||||
brg-name = "brg16";
|
||||
brg-frequency = <20000000>; /* 20 MHz */
|
||||
pio-handle = <&pio_brg>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the unit itself */
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the fan unit */
|
||||
fanu-ivm@50 {
|
||||
label = "FANUV";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
/* fan unit (GPIOs and so on) */
|
||||
fanu@20 {
|
||||
label = "FANUV_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
backplane@50 {
|
||||
label = "BP_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&par_io {
|
||||
pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
|
||||
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
|
||||
|
||||
0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */
|
||||
0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */
|
||||
0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */
|
||||
0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */
|
||||
0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */
|
||||
0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */
|
||||
0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */
|
||||
0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */
|
||||
0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */
|
||||
0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */
|
||||
0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */
|
||||
2 9 1 0 3 0 /* GTX_CLK (CLK10) */
|
||||
2 8 2 0 1 0 /* GTX125 (CLK9) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc4: ucc_pin@3 { /* RMII, admin front port */
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
|
||||
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
|
||||
|
||||
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
|
||||
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
|
||||
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
|
||||
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
|
||||
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
|
||||
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
|
||||
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
|
||||
|
||||
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
|
||||
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
|
||||
|
||||
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
|
||||
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
|
||||
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
|
||||
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
|
||||
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
|
||||
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
|
||||
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
|
||||
|
||||
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */
|
||||
4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */
|
||||
4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_brg: brg_pin@0 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 25 1 0 1 0 /* BRG (PC25, out, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_tdm: tdm_pin@00 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
/* TDMa */
|
||||
0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
|
||||
0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
|
||||
0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
|
||||
2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
|
||||
/* TDMb */
|
||||
0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
|
||||
0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
|
||||
0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
|
||||
2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
|
||||
/* TDMc */
|
||||
1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
|
||||
1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
|
||||
1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
|
||||
2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
|
||||
/* TDMd */
|
||||
1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
|
||||
1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
|
||||
1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
|
||||
2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
|
||||
/* TDMe */
|
||||
3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
|
||||
3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
|
||||
3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
|
||||
2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
|
||||
/* TDMf */
|
||||
3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
|
||||
3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
|
||||
3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
|
||||
2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
|
||||
/* TDMg */
|
||||
4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
|
||||
4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
|
||||
4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
|
||||
2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
|
||||
/* TDMh */
|
||||
4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
|
||||
4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
|
||||
4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
|
||||
2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
|
||||
/* RxTxClk0/1 */
|
||||
2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
|
||||
2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
|
||||
/* RxTxSync0/1 */
|
||||
2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
|
||||
2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
/* mng-switch port (UCC1, MDIO 0x10, RGMII) */
|
||||
enet_switch: ethernet@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk9";
|
||||
/*id=0, full-dup, 1G, no-pause, no-asym_p*/
|
||||
fixed-link = <0 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc1>;
|
||||
};
|
||||
|
||||
/* admin and debug port (UCC4, MDIO 0x00, RMII) */
|
||||
enet_admin: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk17";
|
||||
phy-handle = <&phy_admin>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc4>;
|
||||
};
|
||||
|
||||
/* mate backplane port (UCC5, MDIO 0x08, RMII) */
|
||||
enet_mate: ucc@2400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <5>;
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_mate>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc5>;
|
||||
};
|
||||
|
||||
mdio@3320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3320 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
/* admin front port (UCC4, MDIO 0x00, RMII) */
|
||||
phy_admin: ethernet-phy@00 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
/* mate bp port (UCC5, MDIO 0x08, RMII) */
|
||||
phy_mate: ethernet-phy@08 {
|
||||
reg = <0x08>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000
|
||||
1 0 0xe8000000 0x01000000
|
||||
3 0 0xa0000000 0x10000000
|
||||
4 0 0xb0000000 0x10000000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x04000000>;
|
||||
nornand = "nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xC0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xE0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "kmcoge5ne-uboot.dtsi"
|
||||
42
arch/powerpc/dts/kmeter1-uboot.dtsi
Normal file
42
arch/powerpc/dts/kmeter1-uboot.dtsi
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA kmeter1 U-Boot specific Device Tree Source parts
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
/delete-property/ ethernet1;
|
||||
/delete-property/ ethernet2;
|
||||
/delete-property/ ethernet3;
|
||||
/delete-property/ ethernet4;
|
||||
/delete-property/ ethernet5;
|
||||
/delete-property/ ethernet6;
|
||||
};
|
||||
};
|
||||
|
||||
&enet_estar1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&enet_estar2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&enet_eth1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&enet_eth2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&enet_eth3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&enet_eth4 {
|
||||
status = "disabled";
|
||||
};
|
||||
480
arch/powerpc/dts/kmeter1.dts
Normal file
480
arch/powerpc/dts/kmeter1.dts
Normal file
|
|
@ -0,0 +1,480 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA KMETER1 Device Tree Source
|
||||
*
|
||||
* 2008-2011 DENX Software Engineering GmbH
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km836x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "KMETER1";
|
||||
compatible = "ABB,KMETER1";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
ethernet1 = &enet_estar1;
|
||||
ethernet2 = &enet_estar2;
|
||||
ethernet3 = &enet_eth1;
|
||||
ethernet4 = &enet_eth2;
|
||||
ethernet5 = &enet_eth3;
|
||||
ethernet6 = &enet_eth4;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the unit itself */
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Temperature sensors */
|
||||
temp@48 {
|
||||
label = "Top";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp@49 {
|
||||
label = "Control";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
temp@4a {
|
||||
label = "Power";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
|
||||
temp@4b {
|
||||
label = "Front";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&par_io {
|
||||
pio_ucc1: ucc_pin@0 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
0 3 1 0 1 0 /* TxD0 */
|
||||
0 4 1 0 1 0 /* TxD1 */
|
||||
0 5 1 0 1 0 /* TxD2 */
|
||||
0 6 1 0 1 0 /* TxD3 */
|
||||
0 9 2 0 1 0 /* RxD0 */
|
||||
0 10 2 0 1 0 /* RxD1 */
|
||||
0 11 2 0 1 0 /* RxD2 */
|
||||
0 12 2 0 1 0 /* RxD3 */
|
||||
0 7 1 0 1 0 /* TX_EN */
|
||||
0 8 1 0 1 0 /* TX_ER */
|
||||
0 15 2 0 1 0 /* RX_DV */
|
||||
0 16 2 0 1 0 /* RX_ER */
|
||||
0 0 2 0 1 0 /* RX_CLK */
|
||||
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
|
||||
2 8 2 0 1 0 /* GTX125 - CLK9 */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc2: ucc_pin@1 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
0 17 1 0 1 0 /* TxD0 */
|
||||
0 18 1 0 1 0 /* TxD1 */
|
||||
0 19 1 0 1 0 /* TxD2 */
|
||||
0 20 1 0 1 0 /* TxD3 */
|
||||
0 23 2 0 1 0 /* RxD0 */
|
||||
0 24 2 0 1 0 /* RxD1 */
|
||||
0 25 2 0 1 0 /* RxD2 */
|
||||
0 26 2 0 1 0 /* RxD3 */
|
||||
0 21 1 0 1 0 /* TX_EN */
|
||||
0 22 1 0 1 0 /* TX_ER */
|
||||
0 29 2 0 1 0 /* RX_DV */
|
||||
0 30 2 0 1 0 /* RX_ER */
|
||||
0 31 2 0 1 0 /* RX_CLK */
|
||||
2 2 1 0 2 0 /* GTX_CLK - CLK3 */
|
||||
2 3 2 0 1 0 /* GTX125 - CLK4 */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc4: ucc_pin@3 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
|
||||
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
|
||||
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
|
||||
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
|
||||
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
|
||||
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
|
||||
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
|
||||
|
||||
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc5: ucc_pin@4 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
|
||||
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
|
||||
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
|
||||
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
|
||||
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
|
||||
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
|
||||
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc6: ucc_pin@5 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
|
||||
3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
|
||||
3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
|
||||
3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
|
||||
3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
|
||||
3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
|
||||
3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc7: ucc_pin@6 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
|
||||
4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
|
||||
4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
|
||||
4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
|
||||
4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
|
||||
4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
|
||||
4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc8: ucc_pin@7 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
|
||||
4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
|
||||
4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
|
||||
4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
|
||||
4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
|
||||
4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
|
||||
4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
|
||||
|
||||
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */
|
||||
4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC3 as HDLC controller for ICN */
|
||||
pio5: ucc_pin@02 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
1 0 1 0 1 0 /* TxD0 */
|
||||
1 6 2 0 1 0 /* RxD0 */
|
||||
1 12 2 0 1 0 /* CTS */
|
||||
2 11 2 0 1 0 /* TX-CLK12 */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_tdm: tdm_pin@00 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
/* TDMa */
|
||||
0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
|
||||
0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
|
||||
0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
|
||||
2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
|
||||
/* TDMb */
|
||||
0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
|
||||
0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
|
||||
0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
|
||||
2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
|
||||
/* TDMc */
|
||||
1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
|
||||
1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
|
||||
1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
|
||||
2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
|
||||
/* TDMd */
|
||||
1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
|
||||
1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
|
||||
1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
|
||||
2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
|
||||
/* TDMe */
|
||||
3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
|
||||
3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
|
||||
3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
|
||||
2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
|
||||
/* TDMf */
|
||||
3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
|
||||
3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
|
||||
3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
|
||||
2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
|
||||
/* TDMg */
|
||||
4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
|
||||
4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
|
||||
4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
|
||||
2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
|
||||
/* TDMh */
|
||||
4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
|
||||
4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
|
||||
4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
|
||||
2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
|
||||
/* RxTxClk0/1 */
|
||||
2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
|
||||
2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
|
||||
/* RxTxSync0/1 */
|
||||
2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
|
||||
2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
|
||||
enet_estar1: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk9";
|
||||
phy-handle = <&phy_estar1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc1>;
|
||||
};
|
||||
|
||||
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
|
||||
enet_estar2: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk4";
|
||||
phy-handle = <&phy_estar2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc2>;
|
||||
};
|
||||
|
||||
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
|
||||
enet_piggy2: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk17";
|
||||
phy-handle = <&phy_piggy2>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc4>;
|
||||
};
|
||||
|
||||
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
|
||||
enet_eth1: ucc@2400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <5>;
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth1>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc5>;
|
||||
};
|
||||
|
||||
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
|
||||
enet_eth2: ucc@3400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth2>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc6>;
|
||||
};
|
||||
|
||||
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
|
||||
enet_eth3: ucc@2600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <7>;
|
||||
reg = <0x2600 0x200>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth3>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc7>;
|
||||
};
|
||||
|
||||
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
|
||||
enet_eth4: ucc@3600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth4>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc8>;
|
||||
};
|
||||
|
||||
mdio@3320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3320 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
|
||||
phy_piggy2: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
|
||||
phy_eth1: ethernet-phy@8 {
|
||||
reg = <0x08>;
|
||||
};
|
||||
|
||||
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
|
||||
phy_eth2: ethernet-phy@9 {
|
||||
reg = <0x09>;
|
||||
};
|
||||
|
||||
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
|
||||
phy_eth3: ethernet-phy@a {
|
||||
reg = <0x0a>;
|
||||
};
|
||||
|
||||
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
|
||||
phy_eth4: ethernet-phy@b {
|
||||
reg = <0x0b>;
|
||||
};
|
||||
|
||||
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
|
||||
phy_estar1: ethernet-phy@10 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x10>;
|
||||
};
|
||||
|
||||
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
|
||||
phy_estar2: ethernet-phy@11 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 */
|
||||
3 0 0xa0000000 0x10000000>; /* LB 3 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xC0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xE0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "kmeter1-uboot.dtsi"
|
||||
161
arch/powerpc/dts/kmopti2.dts
Normal file
161
arch/powerpc/dts/kmopti2.dts
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA OPTI2 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km8321.dtsi"
|
||||
|
||||
/ {
|
||||
model = "KMOPTI2";
|
||||
compatible = "ABB,kmpbec8321";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the unit itself */
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Temperature sensors */
|
||||
temp@49 {
|
||||
label = "board";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
temp@4a {
|
||||
label = "power";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@6 {
|
||||
reg = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
reg = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
reg = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&par_io {
|
||||
/* UCC5 as HDLC controller for ICN */
|
||||
pio_ucc5: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 0 1 0 2 0 /* TxD0 */
|
||||
2 8 2 0 2 0 /* RxD0 */
|
||||
2 29 2 0 2 0 /* CTS */
|
||||
3 30 2 0 1 0 /* ICN CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC4 Piggy Ethernet */
|
||||
pio_ucc4: ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0 /* CRS */
|
||||
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
|
||||
3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
|
||||
3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
|
||||
2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
|
||||
3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
use-advanced-sector-protection;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
139
arch/powerpc/dts/kmsupc5.dts
Normal file
139
arch/powerpc/dts/kmsupc5.dts
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA SUPC5 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km8321.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SUPC5";
|
||||
compatible = "ABB,kmpbec8321";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the unit itself */
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Temperature sensors */
|
||||
temp@49 {
|
||||
label = "board";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&par_io {
|
||||
/* UCC5 as HDLC controller for ICN */
|
||||
pio_ucc5: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 0 1 0 2 0 /* TxD0 */
|
||||
2 8 2 0 2 0 /* RxD0 */
|
||||
2 29 2 0 2 0 /* CTS */
|
||||
3 30 2 0 1 0 /* ICN CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC4 Piggy Ethernet */
|
||||
pio_ucc4: ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0 /* CRS */
|
||||
/* UCC4_RMII_CLK (CLK17) */
|
||||
3 10 2 0 3 0
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/*
|
||||
* port pin dir open_drain assignment has_irq
|
||||
* SPI_MOSI (PD0, bi, f3)
|
||||
*/
|
||||
3 0 3 0 1 0
|
||||
/* SPI_MISO (PD1, bi, f3) */
|
||||
3 1 3 0 1 0
|
||||
/* SPI_CLK (PD2, bi, f3) */
|
||||
3 2 3 0 1 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pio-handle = <&pio_spi>;
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
|
||||
2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
129
arch/powerpc/dts/kmsupm5.dts
Normal file
129
arch/powerpc/dts/kmsupm5.dts
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA SUPM5 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km8321.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SUPM5";
|
||||
compatible = "ABB,kmpbec8321";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the unit itself */
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Temperature sensors */
|
||||
temp@49 {
|
||||
label = "board";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&par_io {
|
||||
/* UCC5 as HDLC controller for ICN */
|
||||
pio_ucc5: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 0 1 0 2 0 /* TxD0 */
|
||||
2 8 2 0 2 0 /* RxD0 */
|
||||
2 29 2 0 2 0 /* CTS */
|
||||
3 30 2 0 1 0 /* ICN CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC4 Piggy Ethernet */
|
||||
pio_ucc4: ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0 /* CRS */
|
||||
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
|
||||
3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
|
||||
3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
|
||||
2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
392
arch/powerpc/dts/kmtegr1.dts
Normal file
392
arch/powerpc/dts/kmtegr1.dts
Normal file
|
|
@ -0,0 +1,392 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA TEGR1 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "KMTEGR1";
|
||||
compatible = "ABB,kmpbec8309";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_zynq;
|
||||
ethernet1 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8309@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <16384>; // L1, 16K
|
||||
i-cache-size = <16384>; // L1, 16K
|
||||
timebase-frequency = <66000000>;
|
||||
bus-frequency = <264000000>;
|
||||
clock-frequency = <264000000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc: soc8309@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <264000000>;
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8313-i2c","fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* Inventory EEPROM of the
|
||||
* unit itself
|
||||
*/
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Temperature sensors */
|
||||
temp@48 {
|
||||
label = "front";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp@49 {
|
||||
label = "board";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
temp@4a {
|
||||
label = "power";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
|
||||
temp@4b {
|
||||
label = "bottom";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@6 {
|
||||
reg = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
reg = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
reg = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <264000000>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8309-dma-channel",
|
||||
"fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8309-dma-channel",
|
||||
"fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8309-dma-channel",
|
||||
"fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8309-dma-channel",
|
||||
"fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,pq2pro-pic", "fsl,ipic";
|
||||
interrupt-controller;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@c00 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xc00 0x100>;
|
||||
interrupts = <75 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio-controller@d00 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xd00 0x100>;
|
||||
interrupts = <75 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* GPIO_15 chipselect for ZYNQ flash */
|
||||
gpios = <&gpio1 15 0>;
|
||||
|
||||
zynq_flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <4000000>;
|
||||
m25p,fast-read;
|
||||
partition@0 {
|
||||
label = "bootloader";
|
||||
reg = <0x0 0x01000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qe: qe@e0100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0xe0100000 0x00100000>;
|
||||
reg = <0xe0100000 0x480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <396000000>;
|
||||
fsl,qe-num-snums = <32>;
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x00004000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ZYNQ (UCC1, MDIO 0x10, MII) */
|
||||
enet_zynq: ethernet@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
/*id=0, full-dup, 100M, no-pause, no-asym_p*/
|
||||
fixed-link = <0 1 100 0 0>;
|
||||
rx-clock-name = "clk9";
|
||||
tx-clock-name = "clk10";
|
||||
phy-connection-type = "mii";
|
||||
};
|
||||
|
||||
/* Piggy2 (UCC3, MDIO 0x00, RMII) */
|
||||
enet_piggy2: ucc@2200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk12";
|
||||
phy-handle = <&phy_piggy2>;
|
||||
phy-connection-type = "rmii";
|
||||
};
|
||||
|
||||
mdio@2320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2320 0x38>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
/* Piggy2 (UCC3, MDIO 0x00, RMII) */
|
||||
phy_piggy2: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
||||
/* Explicitly set the tbi-phy to a non-zero address
|
||||
* so that it does not conflict with phy_piggy2 that
|
||||
* is unfortunately at address 0
|
||||
*/
|
||||
tbi1: tbi-phy@1 {
|
||||
reg = <0x1>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <32 8 33 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
bootcount@0x13ff8 {
|
||||
device_type = "bootcount";
|
||||
compatible = "u-boot,bootcount";
|
||||
reg = <0x13ff8 0x08>;
|
||||
};
|
||||
|
||||
};
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
ranges = <0 0 0xf0000000 0x04000000
|
||||
1 0 0xe8000000 0x01000000
|
||||
2 0 0xe0000000 0x10000000
|
||||
3 0 0xb0000000 0x10000000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
nornand = "nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
use-advanced-sector-protection;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xc0000>;
|
||||
};
|
||||
partition@c0000 { /* 256KB */
|
||||
label = "qe-fw";
|
||||
reg = <0xc0000 0x40000>;
|
||||
};
|
||||
partition@100000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0x100000 0x20000>;
|
||||
};
|
||||
partition@120000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0x120000 0x20000>;
|
||||
};
|
||||
partition@140000 { /* 64256KB */
|
||||
label = "ubi0";
|
||||
reg = <0x140000 0x3EC0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "km8309-uboot.dtsi"
|
||||
142
arch/powerpc/dts/kmtepr2.dts
Normal file
142
arch/powerpc/dts/kmtepr2.dts
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA TEPR2 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km8321.dtsi"
|
||||
|
||||
/ {
|
||||
model = "KMTEPR2";
|
||||
compatible = "ABB,kmpbec8321";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
mux@70 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Inventory EEPROM of the unit itself */
|
||||
ivm@50 {
|
||||
label = "MAIN_CTRL";
|
||||
compatible = "dummy";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Temperature sensors */
|
||||
temp@49 {
|
||||
label = "board";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
temp@4a {
|
||||
label = "power";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&par_io {
|
||||
/* UCC5 as HDLC controller for ICN */
|
||||
pio_ucc5: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 0 1 0 2 0 /* TxD0 */
|
||||
2 8 2 0 2 0 /* RxD0 */
|
||||
2 29 2 0 2 0 /* CTS */
|
||||
3 30 2 0 1 0 /* ICN CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC4 Piggy Ethernet */
|
||||
pio_ucc4: ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0 /* CRS */
|
||||
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/*
|
||||
*port pin dir open_drain assignment has_irq
|
||||
* SPI_MOSI (PD0, bi, f3)
|
||||
*/
|
||||
3 0 3 0 1 0
|
||||
/* SPI_MISO (PD1, bi, f3) */
|
||||
3 1 3 0 1 0
|
||||
/* SPI_CLK (PD2, bi, f3) */
|
||||
3 2 3 0 1 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
|
||||
2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */
|
||||
3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
use-advanced-sector-protection;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
100
arch/powerpc/dts/kmtuge1.dts
Normal file
100
arch/powerpc/dts/kmtuge1.dts
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA TUGE1 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km8321.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TUGE1";
|
||||
compatible = "ABB,kmpbec8321";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&par_io {
|
||||
/* UCC5 as HDLC controller for ICN */
|
||||
pio_ucc5: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 0 1 0 2 0 /* TxD0 */
|
||||
2 8 2 0 2 0 /* RxD0 */
|
||||
2 29 2 0 2 0 /* CTS */
|
||||
3 30 2 0 1 0 /* ICN CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC4 Piggy Ethernet */
|
||||
pio_ucc4: ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0 /* CRS */
|
||||
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/*
|
||||
*port pin dir open_drain assignment has_irq
|
||||
* SPI_MOSI (PD0, bi, f3)
|
||||
*/
|
||||
3 0 3 0 1 0
|
||||
/* SPI_MISO (PD1, bi, f3) */
|
||||
3 1 3 0 1 0
|
||||
/* SPI_CLK (PD2, bi, f3) */
|
||||
3 2 3 0 1 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
|
||||
2 0 0xa0000000 0x10000000>; /* LB 2 PAXI */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
100
arch/powerpc/dts/kmtuxa1.dts
Normal file
100
arch/powerpc/dts/kmtuxa1.dts
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* ABB PGGA TUXA1 Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "km8321.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TUXA1";
|
||||
compatible = "ABB,kmpbec8321";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet_piggy2;
|
||||
serial0 = &serial0;
|
||||
};
|
||||
};
|
||||
|
||||
&par_io {
|
||||
/* UCC5 as HDLC controller for ICN */
|
||||
pio_ucc5: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
2 0 1 0 2 0 /* TxD0 */
|
||||
2 8 2 0 2 0 /* RxD0 */
|
||||
2 29 2 0 2 0 /* CTS */
|
||||
3 30 2 0 1 0 /* ICN CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
/* UCC4 Piggy Ethernet */
|
||||
pio_ucc4: ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0 /* CRS */
|
||||
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_spi: spi_pin@01 {
|
||||
pio-map = <
|
||||
/*
|
||||
*port pin dir open_drain assignment has_irq
|
||||
* SPI_MOSI (PD0, bi, f3)
|
||||
*/
|
||||
3 0 3 0 1 0
|
||||
/* SPI_MISO (PD1, bi, f3) */
|
||||
3 1 3 0 1 0
|
||||
/* SPI_CLK (PD2, bi, f3) */
|
||||
3 2 3 0 1 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
|
||||
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
|
||||
2 0 0xa0000000 0x10000000 /* LB 2 LPXF */
|
||||
3 0 0xb0000000 0x10000000>; /* LB 3 PINC2 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 { /* 768KB */
|
||||
label = "u-boot";
|
||||
reg = <0 0xC0000>;
|
||||
};
|
||||
partition@c0000 { /* 128KB */
|
||||
label = "env";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
partition@e0000 { /* 128KB */
|
||||
label = "envred";
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
partition@100000 { /* 64512KB */
|
||||
label = "ubi0";
|
||||
reg = <0x100000 0x3F00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,3 +1,20 @@
|
|||
menu "KM 83xx Options"
|
||||
depends on MPC83xx
|
||||
|
||||
config KM_ENABLE_FULL_DM_DTS_SUPPORT
|
||||
bool "enable full DM/DTS support for KM 83xx boards"
|
||||
default y
|
||||
select CMD_DM
|
||||
select DM
|
||||
select DM_ETH
|
||||
select DM_MDIO
|
||||
select DM_SERIAL
|
||||
select OF_CONTROL
|
||||
select PINCTRL
|
||||
select PINCTRL_QE
|
||||
select PHYLIB
|
||||
endmenu
|
||||
|
||||
if TARGET_KMETER1
|
||||
|
||||
config SYS_BOARD
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
KM83XX BOARD
|
||||
M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
|
||||
M: Heiko Schocher <hs@denx.de>
|
||||
S: Maintained
|
||||
F: board/keymile/km83xx/
|
||||
F: include/configs/km8360.h
|
||||
|
|
@ -7,12 +8,24 @@ F: configs/kmcoge5ne_defconfig
|
|||
F: configs/kmeter1_defconfig
|
||||
F: include/configs/tuxx1.h
|
||||
F: configs/kmopti2_defconfig
|
||||
F: configs/kmsupx5_defconfig
|
||||
F: configs/kmtepr2_defconfig
|
||||
F: configs/kmtegr1_defconfig
|
||||
F: configs/tuge1_defconfig
|
||||
F: configs/tuxx1_defconfig
|
||||
|
||||
KMSUPX5 BOARD
|
||||
M: Heiko Schocher <hs@denx.de>
|
||||
S: Maintained
|
||||
F: configs/kmsupx5_defconfig
|
||||
F: arch/powerpc/dts/km8309-uboot.dtsi
|
||||
F: arch/powerpc/dts/km8321-uboot.dtsi
|
||||
F: arch/powerpc/dts/km8321.dtsi
|
||||
F: arch/powerpc/dts/km836x-uboot.dtsi
|
||||
F: arch/powerpc/dts/km836x.dtsi
|
||||
F: arch/powerpc/dts/kmcoge5ne-uboot.dtsi
|
||||
F: arch/powerpc/dts/kmcoge5ne.dts
|
||||
F: arch/powerpc/dts/kmeter1-uboot.dtsi
|
||||
F: arch/powerpc/dts/kmeter1.dts
|
||||
F: arch/powerpc/dts/kmopti2.dts
|
||||
F: arch/powerpc/dts/kmsupc5.dts
|
||||
F: arch/powerpc/dts/kmsupm5.dts
|
||||
F: arch/powerpc/dts/kmtegr1.dts
|
||||
F: arch/powerpc/dts/kmtepr2.dts
|
||||
F: arch/powerpc/dts/kmtuge1.dts
|
||||
F: arch/powerpc/dts/kmtuxa1.dts
|
||||
|
|
|
|||
|
|
@ -36,70 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
|
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
/* port pin dir open_drain assign */
|
||||
#if defined(CONFIG_ARCH_MPC8360)
|
||||
/* MDIO */
|
||||
{0, 1, 3, 0, 2}, /* MDIO */
|
||||
{0, 2, 1, 0, 1}, /* MDC */
|
||||
|
||||
/* UCC4 - UEC */
|
||||
{1, 14, 1, 0, 1}, /* TxD0 */
|
||||
{1, 15, 1, 0, 1}, /* TxD1 */
|
||||
{1, 20, 2, 0, 1}, /* RxD0 */
|
||||
{1, 21, 2, 0, 1}, /* RxD1 */
|
||||
{1, 18, 1, 0, 1}, /* TX_EN */
|
||||
{1, 26, 2, 0, 1}, /* RX_DV */
|
||||
{1, 27, 2, 0, 1}, /* RX_ER */
|
||||
{1, 24, 2, 0, 1}, /* COL */
|
||||
{1, 25, 2, 0, 1}, /* CRS */
|
||||
{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
|
||||
{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
|
||||
|
||||
/* DUART - UART2 */
|
||||
{5, 0, 1, 0, 2}, /* UART2_SOUT */
|
||||
{5, 2, 1, 0, 1}, /* UART2_RTS */
|
||||
{5, 3, 2, 0, 2}, /* UART2_SIN */
|
||||
{5, 1, 2, 0, 3}, /* UART2_CTS */
|
||||
#elif !defined(CONFIG_ARCH_MPC8309)
|
||||
/* Local Bus */
|
||||
{0, 16, 1, 0, 3}, /* LA00 */
|
||||
{0, 17, 1, 0, 3}, /* LA01 */
|
||||
{0, 18, 1, 0, 3}, /* LA02 */
|
||||
{0, 19, 1, 0, 3}, /* LA03 */
|
||||
{0, 20, 1, 0, 3}, /* LA04 */
|
||||
{0, 21, 1, 0, 3}, /* LA05 */
|
||||
{0, 22, 1, 0, 3}, /* LA06 */
|
||||
{0, 23, 1, 0, 3}, /* LA07 */
|
||||
{0, 24, 1, 0, 3}, /* LA08 */
|
||||
{0, 25, 1, 0, 3}, /* LA09 */
|
||||
{0, 26, 1, 0, 3}, /* LA10 */
|
||||
{0, 27, 1, 0, 3}, /* LA11 */
|
||||
{0, 28, 1, 0, 3}, /* LA12 */
|
||||
{0, 29, 1, 0, 3}, /* LA13 */
|
||||
{0, 30, 1, 0, 3}, /* LA14 */
|
||||
{0, 31, 1, 0, 3}, /* LA15 */
|
||||
|
||||
/* MDIO */
|
||||
{3, 4, 3, 0, 2}, /* MDIO */
|
||||
{3, 5, 1, 0, 2}, /* MDC */
|
||||
|
||||
/* UCC4 - UEC */
|
||||
{1, 18, 1, 0, 1}, /* TxD0 */
|
||||
{1, 19, 1, 0, 1}, /* TxD1 */
|
||||
{1, 22, 2, 0, 1}, /* RxD0 */
|
||||
{1, 23, 2, 0, 1}, /* RxD1 */
|
||||
{1, 26, 2, 0, 1}, /* RxER */
|
||||
{1, 28, 2, 0, 1}, /* Rx_DV */
|
||||
{1, 30, 1, 0, 1}, /* TxEN */
|
||||
{1, 31, 2, 0, 1}, /* CRS */
|
||||
{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
|
||||
#endif
|
||||
|
||||
/* END of table */
|
||||
{0, 0, 0, 0, QE_IOP_TAB_END},
|
||||
};
|
||||
|
||||
static int piggy_present(void)
|
||||
{
|
||||
struct km_bec_fpga __iomem *base =
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth1"
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmcoge5ne"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_KMCOGE5NE=y
|
||||
|
|
@ -156,7 +156,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
|||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
||||
CONFIG_LCRR_EADC_2=y
|
||||
CONFIG_LCRR_CLKDIV_4=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -173,6 +172,7 @@ CONFIG_CMD_GREPENV=y
|
|||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
|
|
@ -186,8 +186,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -197,8 +198,10 @@ CONFIG_FLASH_CFI_MTD=y
|
|||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_BCH=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth2"
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmeter1"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_KMETER1=y
|
||||
|
|
@ -120,7 +120,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
|||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
||||
CONFIG_LCRR_EADC_2=y
|
||||
CONFIG_LCRR_CLKDIV_4=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -136,6 +135,7 @@ CONFIG_CMD_ASKENV=y
|
|||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
|
|
@ -149,8 +149,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -159,7 +160,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmopti2"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_KMOPTI2=y
|
||||
|
|
@ -139,7 +139,6 @@ CONFIG_ACR_APARK_MASTER=y
|
|||
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -155,6 +154,7 @@ CONFIG_CMD_ASKENV=y
|
|||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
|
|
@ -168,8 +168,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -178,7 +179,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmsupm5"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_KMSUPX5=y
|
||||
|
|
@ -119,7 +119,6 @@ CONFIG_ACR_APARK_MASTER=y
|
|||
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -148,8 +147,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -158,7 +158,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth1"
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmtegr1"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_KMTEGR1=y
|
||||
|
|
@ -118,7 +118,6 @@ CONFIG_ACR_APARK_MASTER=y
|
|||
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
|
||||
|
|
@ -150,8 +149,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF0100000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF0120000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -161,9 +161,13 @@ CONFIG_FLASH_CFI_MTD=y
|
|||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_BCH=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmtepr2"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_KMTEPR2=y
|
||||
|
|
@ -139,7 +139,6 @@ CONFIG_ACR_APARK_MASTER=y
|
|||
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -168,8 +167,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -178,7 +178,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmtuge1"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_TUGE1=y
|
||||
|
|
@ -119,7 +119,6 @@ CONFIG_ACR_APARK_MASTER=y
|
|||
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -148,8 +147,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -158,7 +158,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
|
|||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kmtuxa1"
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_TUXX1=y
|
||||
|
|
@ -141,7 +141,6 @@ CONFIG_ACR_APARK_MASTER=y
|
|||
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
|
||||
CONFIG_LCRR_EADC_1=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -170,8 +169,9 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xF00C0000
|
||||
CONFIG_ENV_ADDR_REDUND=0xF00E0000
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_BOOTCOUNT=y
|
||||
CONFIG_BOOTCOUNT_MEM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -180,7 +180,10 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_QE_UEC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -10,20 +10,6 @@
|
|||
#define CONFIG_SYS_CLK_FREQ 66000000
|
||||
#define CONFIG_83XX_PCICLK 66000000
|
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */
|
||||
#define UEC_VERBOSE_DEBUG 1
|
||||
|
||||
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
|
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
|
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -6,20 +6,6 @@
|
|||
* High Level Configuration Options
|
||||
*/
|
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */
|
||||
#define UEC_VERBOSE_DEBUG 1
|
||||
|
||||
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
|
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
|
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
||||
|
||||
/*
|
||||
* System IO Setup
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -61,16 +61,6 @@
|
|||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_NUM_I2C_BUSES 4
|
||||
|
|
|
|||
Loading…
Reference in a new issue