Commit graph

791 commits

Author SHA1 Message Date
Marek Vasut
3a96ad851f PXA: Align stack to 8 bytes
Part of this patch is by: Mikhail Kshevetskiy.

Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD
instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour
is undefined.

The issue was observed when working with the NAND code, which was rendered
disfunctional. Also, the vsprintf() function had serious problems with printing
64bit wide long longs. After aligning the stack, this wrong behaviour is no
longer present.

Tested on:
	Marvell Littleton PXA310 board
	Toradex Colibri PXA320 board
	Aeronix Zipit Z2 PXA270 handheld
	Voipac PXA270 board

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-06-13 13:39:02 +02:00
Sudhakar Rajashekhara
89b765c7f6 TI: DaVinci: Add board specific code for da850 EVM
Provides initial support for TI OMAP-L138/DA850 SoC devices on
a Logic PD EVM board.

Provides:
Initial boot and configuration.
Support for i2c.
UART support (console).

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Acked-by: Ben Gardiner <bengardiner@nanometrics.ca>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-10 12:04:42 -04:00
Vaibhav Hiremath
1a5038ca68 AM35x: Add support for EMIF4
This patch adds support for the EMIF4 interface
available in the AM35x processors.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:19 -05:00
Vaibhav Hiremath
cae377b59a omap3: Consolidate SDRC related operations
Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:18 -05:00
Vaibhav Hiremath
d11212e377 omap3: Calculate CS1 size only when SDRC is
initialized for CS1

From: Vaibhav Hiremath <hvaibhav@ti.com>

The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:18 -05:00
Cyril Chemparathy
3712367c48 ARM1176: TI: TNETV107X soc initial support
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals.  This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:17 -05:00
Cyril Chemparathy
678e008c3a ARM1176: Coexist with other ARM1176 platforms
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture.  The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.

Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.

1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.

2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM.  Added support for this capability in ARM1176 architecture.

3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.

4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include.  The presence
of this include prevents builds on other ARM1176 archs.

5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:17 -05:00
Vaibhav Hiremath
05ee415e31 AM35x: Add support for EMIF4
This patch adds support for the EMIF4 interface
available in the AM35x processors.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 15:20:53 -04:00
Vaibhav Hiremath
8aa5c7cdc4 omap3: Consolidate SDRC related operations
Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 15:20:34 -04:00
Vaibhav Hiremath
16807ee411 omap3: Calculate CS1 size only when SDRC is
initialized for CS1

From: Vaibhav Hiremath <hvaibhav@ti.com>

The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 15:20:29 -04:00
Cyril Chemparathy
da1ec42aaf ARM1176: TI: TNETV107X soc initial support
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals.  This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 14:13:32 -04:00
Cyril Chemparathy
b87996d24a ARM1176: Coexist with other ARM1176 platforms
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture.  The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.

Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.

1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.

2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM.  Added support for this capability in ARM1176 architecture.

3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.

4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include.  The presence
of this include prevents builds on other ARM1176 archs.

5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 14:13:27 -04:00
George G. Davis
409a07c9d7 ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
instruction which means "Invalidate Both Caches" when in fact the intent
is to clean and invalidate all caches.  So add an "mcr p15, 0, %0, c7,
c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
Both Caches" instruction to insure that memory is consistent with any
dirty cache lines.

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.

Signed-off-by: George G. Davis <gdavis@mvista.com>
2010-06-01 06:44:09 -05:00
Wolfgang Denk
9bb3b3d440 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-05-30 21:44:07 +02:00
Wolfgang Denk
a81cd434b9 Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-05-30 21:43:05 +02:00
Timur Tabi
6e37a04407 fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of
struct ccsr_gur.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-30 11:10:32 -05:00
Wolfgang Denk
bd7bb6f8a3 Merge branch 'next' of git://git.denx.de/u-boot-nios 2010-05-28 20:34:39 +02:00
Tom
39c209546a ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 3defb2476166445982a90c12d33f8947e75476c4

Signed-off-by: Tom <Tom@bumblecow.com>
2010-05-28 13:23:16 -05:00
Tom
551bd947bd ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 257dab81413b31b8648becfe11586b3a41e5c29a

Signed-off-by: Tom <Tom@bumblecow.com>
2010-05-28 11:49:42 -05:00
Thomas Chou
1117cbf2ad nios: remove nios-32 arch
The nios-32 arch is obsolete and broken. So it is removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2010-05-28 10:56:04 -04:00
Thomas Chou
6803336c9f nios2: allow STANDALONE_LOAD_ADDR overriding
This patch allows users to override default STANDALONE_LOAD_ADDR.
The gcclibdir path was duplicated in the standalone Makefile and
can be removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:04 -04:00
Thomas Chou
8d52ea6db4 nios2: fix div64 issue for gcc4
This patch fixes the run-time error on div64 when built with
gcc4, which was reported by jhwu0625 on nios forum. It merges
math support from libgcc of gcc4. This patch is copied from
nios2-linux.

It works with both gcc3 and gcc4. The old mult.c, divmod.c and
math.h are removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Thomas Chou
0df01fd3d7 nios2: fix r15 issue for gcc4
The "-ffixed-r15" option doesn't work well for gcc4. Since we
don't use gp for small data with option "-G0", we can use gp
as global data pointer. This allows compiler to use r15. It
is necessary for gcc4 to work properly.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Thomas Chou
cedd341d55 nios2: add gpio support
This patch adds driver for a trivial gpio core, which is described
in http://nioswiki.com/GPIO. It is used for gpio led and nand flash
interface in u-boot.

When CONFIG_SYS_GPIO_BASE is not defined, board may provide
its own driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tested-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Wolfgang Wegner
adf55679af add CONFIG_SYS_FEC_FULL_MII for MCF5445x
This patch adds support for full MII interface on MCF5445x (in contrast
to RMII as used on the evaluation boards).

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-05-28 02:15:57 -05:00
Wolfgang Wegner
ae49099755 add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x
This patch adds the possibility to handle seperate PHYs to MCF5445x.
Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the
linux kernel.

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-05-28 02:15:55 -05:00
Wolfgang Wegner
e9b43cae1a add missing PCS3 for MCF5445x
This patch adds the code for handling PCS3 (DSPI chip select 3) in
cpu_init.c and m5445x.h

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-05-28 02:15:51 -05:00
Wolfgang Denk
c4976807cb Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-05-26 23:51:22 +02:00
Wolfgang Denk
45b728cdee Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-26 22:36:32 +02:00
Kumar Gala
6ece2550d1 Convert Makefiles from COBJS-${} to COBJS-$()
Match style we use almost everywhere else

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-26 22:27:38 +02:00
Michael Weiss
59dde44acb powerpc/bootcount: Fix endianness problem
For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-05-26 22:26:32 +02:00
Wolfgang Denk
40792d675a a320evb: fix udelay / __udelay confusion
Fix the following compiler problems:

arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay':
/home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay'
lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here
lib/libgeneric.a(time.o): In function `udelay':
time.c:(.text+0x1c): undefined reference to `__udelay'

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-05-21 23:14:53 +02:00
Wolfgang Denk
92381c41c7 ARM: */timer.c: fix spelling and vertical alignment
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-05-21 23:13:18 +02:00
Kim Phillips
71bd860cce mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c
commit c7190f028f "mpc83xx:
retain POR values of non-configured ACR, SPCR, SCCR, and LCRR
bitfields" incorrectly shifted <register>_<bitfield> (e.g.
ACR_PIPE_DEP) values that were preshifted by their
definition in mpc83xx.h.

this patch removes the unnecessary shifting for the newly
utilized mask values in cpu_init.c, and prevents seemingly
unrelated symptoms such as an mpc8379erdb board from
locking up whilst performing a networking operation,
e.g. a tftp.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-21 15:22:39 -05:00
Horst Kronstorfer
f6970d0c54 Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S.
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-21 15:22:36 -05:00
Wolfgang Denk
8a452c2c17 Merge branch 'master' of git://git.denx.de/u-boot-imx 2010-05-21 22:22:23 +02:00
Wolfgang Denk
568278e336 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-17 23:16:08 +02:00
Wolfgang Denk
1a1e6bf12b Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-05-17 23:11:21 +02:00
Kim Phillips
a4bfc4cc46 mpc83xx: fix NAND bootstrap too big error
commit 167cdad137 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.

this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31 "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-17 14:44:25 -05:00
Wolfgang Denk
cd4b02be1b ARM: add __aeabi_unwind_cpp_pr0() function to avoid linker complaints
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested-by: Thomas Weber <weber@corscience.de>
2010-05-15 19:50:36 +02:00
York Sun
bcb6c2bb84 Enabled support for Rev 1.3 SPD for DDR2 DIMMs
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not verified on hardware for CL7 at this moment.

This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
spec, the lower nibble is optionally used to determine which additinal bytes
or attribute bits have been defined. Software can safely use defaults. However,
the upper nibble should always be checked.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:54:30 -05:00
Kumar Gala
f54fe87ace 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.

Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:51 -05:00
Kumar Gala
54648985e2 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the
PCI specific code.  Use it instead as we convert away from the
is_fsl_pci_cfg() code.

Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:51 -05:00
Kumar Gala
6ab4011b79 85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:50 -05:00
Wolfgang Denk
ab92d0fd9a Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-09 01:16:51 +02:00
Ron Madrid
3b439792b0 mpc83xx: Add UPMA configuration to SIMPC8313
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-07 12:19:52 -05:00
Mike Frysinger
f745817e74 update include/asm/ gitignore after move
With the cpu include paths moved, the gitignore paths need updating.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Tom Rix <tom@bumblecow.com>
2010-05-07 00:17:30 +02:00
Stefan Roese
e4a95d112e powerpc: Consolidate bootcount_{store|load} for PowerPC
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now used by all PowerPC variants that currently have these
functions implemented.

The functions now use the proper IO-accessor functions to read/write the
values.

This code also supports two different bootcount versions:

a) Use 2 separate words (2 * 32bit) to store the bootcounter
b) Use only 1 word (2 * 16bit) to store the bootcounter

Version b) was already used by MPC5xxx.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
          for 83xx parts
Cc: Michael Zaidman <michael.zaidman@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-05-06 23:28:48 +02:00
Graeme Russ
1f9f3cf6cc sc520: Fix minor DRAM Controller Setup bug
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:20:56 +02:00
Graeme Russ
d20053efdf sc520: Update to new AMD Copyright
AMD recently changed the licensing of the RAM sizing code to the
GPLv2 (or at your option any later version)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:20:44 +02:00
Graeme Russ
21e67e796b sc520: Board Specific PCI Init
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:18:52 +02:00
Graeme Russ
0278216b76 sc520: Move PCI defines to PCI include file
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:18:41 +02:00
Graeme Russ
5204566e53 sc520: Allow boards to override udelay
If the board has a high precision mico-second timer, it maked sense to use
it instead of the on-chip one

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:17:37 +02:00
Graeme Russ
95ffaba390 x86: Fix support for booting bzImage
Add support for newer (up to 2.6.33) kernels

Add zboot command which takes the address of a bzImage as its first
argument and (optionally) the size of the bzImage as the second argument
(the second argument is needed for older kernels which do not include
the bzImage size in the header)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:17:01 +02:00
Graeme Russ
79ea6b8701 x86: Provide weak PC/AT compatibility setup function
It is possibly to setup x86 boards to use non-PC/AT configurations. For
example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals.
This function allows the board to set itself up for maximum PC/AT
compatibility just before booting the Linux kernel (the Linux kernel
'just works' if everything is PC/AT compliant)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:16:54 +02:00
Graeme Russ
bf16500f79 x86: Use CONFIG_SERIAL_MULTI
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:16:46 +02:00
Graeme Russ
153c2d9f23 x86: Fix copying of Real-Mode code into RAM
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:58 +02:00
Graeme Russ
2fb1bc4f53 x86: Pass relocation offset into Global Data
In order to locate the 16-bit BIOS code, we need to know the reloaction
offset.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:51 +02:00
Graeme Russ
c14a3669b2 x86: Move GDT to a safe location in RAM
Currently, the GDT is either located in FLASH or in the non-relocated
U-Boot image in RAM. Both of these locations are unsafe as those
locations can be erased during a U-Boot update. Move the GDT into the
highest available memory location and relocate U-Boot to just below it

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:43 +02:00
Graeme Russ
077e1958ca x86: Add RAM bootstrap functionality
Add a parameter to the 32-bit entry to indicate if entry is from Real
Mode or not. If entry is from Real Mode, execute the destructive 'sizer'
routine to determine memory size as we are booting cold and running in
Flash. If not entering from Real Mode, we are executing a U-Boot image
from RAM and therefore the memory size is already known (and running
'sizer' will destroy the running image)

There are now two 32-bit entry points. The first is the 'in RAM' entry
point which exists at the start of the U-Boot binary image. As such,
you can load u-boot.bin in RAM and jump directly to the load address
without needing to calculate any offsets. The second entry point is
used by the real-to-protected mode switch

This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load
the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot
prompt

Hopefully a later patch will completely elliminate any dependency on
TEXT_BASE like a relocatable linux kernel (perfect world)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:31 +02:00
Graeme Russ
759598f82f x86: Split sc520 memory sizing versus reporting
This patch allows the low-level assembler boot-strap to obtain the RAM
size without calling the destructive 'sizer' routine. This allows
boot-strapping from a U-Boot image loaded in RAM

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:44 +02:00
Graeme Russ
4dba333b3c x86: Fix sc520 memory size reporting
There is an error in how the assembler version of the sc520 memory size
reporting code works. As a result, it will only ever report at most the
size of one bank of RAM

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:32 +02:00
Graeme Russ
9e08efcfee x86: Fix do_go_exec()
This was broken a long time ago by a49864593e
which munged the NIOS and x86 do_go_exec()

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:08 +02:00
Graeme Russ
433ff2bdbc x86: Add register dump to crash handlers
Shamelessly steal the Linux x86 crash handling code and shove it into
U-Boot (cool - it fits). Be sure to include suitable attribution to
Linus

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:00 +02:00
Graeme Russ
64a0a4995e x86: Fix MMCR Access
Change sc520 MMCR Access to use memory accessor functions

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:13:48 +02:00
Graeme Russ
535ad2db06 x86: #ifdef out getenv_IPaddr()
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:13:34 +02:00
Graeme Russ
721c36705a x86: Add unaligned.h
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:13:08 +02:00
Norbert van Bolhuis
3882d7a5a5 ppc: unused memory region too close to current stack pointer
This avoids a possible overwrite of the (end of) ramdisk by u-boot.
The unused memory region for ppc boot currently starts 1k below the
do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since
do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may
very well use more than 1k stack space.

Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
2010-05-05 23:55:02 +02:00
Fabio Estevam
60381d6878 MX51: Fix MX51 CPU detect message
Fix MX51 CPU detect message.

Original string was:
CPU:   Freescale i.MX51 family 3.0V at 800 MHz

which can be misinterpreted as  3.0 Volts instead of the silicon revision.

,change it to:
CPU:   Freescale i.MX51 family rev3.0 at 800 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2010-05-05 09:48:41 +02:00
Wolfgang Denk
679ec15462 Merge branch 'master' of git://git.denx.de/u-boot-net 2010-05-04 22:57:37 +02:00
Detlev Zundel
6f5f89f011 Remove unused "local_crc32" function.
For code archeologists, this is a nice example of copy and paste history.

Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-05-03 14:52:48 -07:00
Asen Dimov
d6b91e30d3 at91: define matrix registers bit fields
Signed-off-by: Asen Dimov <dimov@ronetix.at>
2010-04-30 05:23:26 -05:00
Stefano Babic
eab40f819d MX31: Support 128MB RAM on QONG module
The QONG module can be downsized and delivered
with 128MB instead of 256MB. The patch adds
run time support for the two different memory
configurations.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:26 -05:00
Stefano Babic
efb9591069 MX31: add pin definitions for NAND controller
Add pin definitions ralted to the NAND controller to be used
to set up the pin multiplexer.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:25 -05:00
Stefano Babic
7d27cd08b4 MX31: add accessor function to get a gpio
The patch adds an accessor function to get the value of a gpio.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:25 -05:00
John Rigby
34196b0a8b MX25 print arm clock instead of mpllclk on boot
Replace call to imx_get_mpllclk with imx_get_armclk
to show frequency of ARM core instead of mpll internal
bus in print_cpuinfo.

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:24 -05:00
Stefano Babic
5e1fe88fe3 Moved board specific values in config file
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:24 -05:00
Heiko Schocher
1e65c2beb5 arm, mx27: add support for SDHC1 pin init
Signed-off-by: Heiko Schocher <hs@denx.de>
2010-04-30 05:23:23 -05:00
Minkyu Kang
3bb6b037e8 SAMSUNG: make s5p common gpio functions
Because of s5pc1xx gpio is same as s5p seires SoC,
move gpio functions to drvier/gpio/
and modify structure's name from s5pc1xx_ to s5p_.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-04-30 05:23:23 -05:00
Minkyu Kang
46a3b5c8df SAMSUNG: serial: modify name from s5pc1xx to s5p
Because of other s5p series SoC will use these serial functions,
modify function's name and structure's name.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-04-30 05:23:23 -05:00
Alexander Holler
47eb08a97e at91: add defines for RTT and GPBR
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
2010-04-30 05:23:22 -05:00
trix
7bc8768039 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 85b3cce880a19e78286570d5fd004cc3cac06f57

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-04-30 05:23:21 -05:00
Wolfgang Denk
d03f4230a6 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-04-28 00:09:53 +02:00
Wolfgang Denk
8e98f5f70b Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2010-04-27 23:02:12 +02:00
Wolfgang Denk
c303176aa0 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-04-27 22:57:41 +02:00
Wolfgang Denk
c88d6ab19f Merge branch 'next' of git://git.denx.de/u-boot-nios 2010-04-27 22:53:04 +02:00
Kumar Gala
7e1afb62a7 ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-26 22:37:57 -05:00
Lan Chunhe
3f0202ed13 mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:56 -05:00
Dave Liu
0c955dafab 85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:56 -05:00
Kumar Gala
9ce3c22827 85xx: Fix compile warning
cpu.c: In function 'checkcpu':
cpu.c:47: warning: unused variable 'gur'

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:55 -05:00
Kumar Gala
4db9708b94 85xx: Convert cpu_init_f code to use out_be32 for LBC registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:55 -05:00
Dave Liu
99bac479dd fsl-ddr: Add extra cycle to turnaround times
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Dave Liu
f8d05e5e58 fsl-ddr: add the macro for Rtt_Nom definition
add the macro definition for Rtt_Nom termination value for DDR3

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Kumar Gala
1231c498e0 ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines
Added some needed fines and some misc additional defines
used by p4080 initialization.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:52 -05:00
Dave Liu
17d90f31a8 ppc/p4080: Extend the GUTS memory map
Extend pin control and clock control to GUTS memory map

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:52 -05:00
Srikanth Srinivasan
ab48ca1a66 ppc/p4080: Fix synchronous frequency calculations
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency.  It should be synchronous with the platform
frequency.  CPU frequency is based on platform frequency in synchronous
mode.

Also fix:

* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:51 -05:00
Thomas Chou
441cac10d8 nios2: fix no flash, add nand and mmc init in board.c
This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization, which should go before
env initialization.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:23 -04:00
Thomas Chou
fd2712d0b1 nios2: consolidate reset initialization
Global interrupt should be disabled from the beginning.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:23 -04:00
Thomas Chou
7e812f2e9c nios2: add dma_alloc_coherent
This function return cache-line aligned allocation which is mapped
to uncached io region.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:22 -04:00
Thomas Chou
0dc1c7f692 nios2: add 64 bits swab support
This patch adds 64 bits swab support. Most 32 bits processors use
this. We need 64 bits swab for UBI.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:22 -04:00
Thomas Chou
dd168ef5b8 nios2: allow link script overriding from boards
This patch allow boards to override the default link script.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:22 -04:00
Anatolij Gustschin
2ebdb9a9d7 mpc5121: add common post_word_load/store code
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:39 +02:00
Anatolij Gustschin
a3921eefa1 mpc5121: add support for PDM360NG board
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:37 +02:00
Anatolij Gustschin
b9947bbb08 mpc5121: determine RAM size using get_ram_size()
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:35 +02:00
Anatolij Gustschin
5d937e8b59 mpc512x: make MEM IO Control configuration a board config option
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:34 +02:00
Anatolij Gustschin
8e234e33bf mpc5121: add PSC serial communication routines
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:32 +02:00
Anatolij Gustschin
e3b28e6732 mpc512x: add multi serial PSC support
Extend mpc512x serial driver to support multiple PSC ports.

Subsequent patches for PDM360NG board support make use of this
functionality by defining CONFIG_SERIAL_MULTI in the board config
file. Additionally the used PSC devices are specified by defining
e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6.

Support for PSC devices other than 1, 3, 4 and 6 is not added
by this patch because these aren't used currently. In the future
it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and
INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c.
Additionally you have to add code for registering added
devices in serial_initialize() in common/serial.c.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:30 +02:00
Anatolij Gustschin
fbb0030e38 serial: struct serial_device: add uninit() entry for drivers
Subsequent patch extends mpc512x serial driver to support
multiple PSC ports. The driver will provide an uninit()
function to stop the serial controller and to disable the
controller's clock. Adding uninit() entry to struct serial_device
allows disabling the serial controller after usage of
a stdio serial device.

This patch adds uninit() entry to the struct serial_device
and fixes initialization of this structure in the code
accordingly.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 21:34:07 +02:00
Wolfgang Denk
a77034a8df Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-04-24 21:16:57 +02:00
Wolfgang Denk
500fbae204 Merge branch 'master' of git://git.denx.de/u-boot-microblaze 2010-04-24 21:13:31 +02:00
Kim Phillips
1a2e203b31 mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:

        column1 is elapsed time since first message
        column2 is elapsed time since previous message
        column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA:  Configured for compact flash
0.032 0.000: I2C:   ready
0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
2.652 0.011:         00  10  1095  3114  0180  00
2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
2.652 0.000: In:    serial
2.652 0.000: Out:   serial
2.652 0.000: Err:   serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE:   Bus 0: .** Timeout **

after, MPC8349ITX boots u-boot in 3.0sec:

0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA:  Configured for compact flash
0.038 0.000: I2C:   ready
0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
1.390 0.000:         00  10  1095  3114  0180  00
1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
1.400 0.010: In:    serial
1.400 0.000: Out:   serial
1.400 0.000: Err:   serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE:   Bus 0: .** Timeout **

also tested on these boards (albeit with a less accurate
boottime measurement method):

seconds: before  after
8349MDS  ~2.6    ~2.2
8360MDS  ~2.8    ~2.6
8313RDB  ~2.5    ~2.3 #nand boot
837xRDB  ~3.1    ~2.3

also tested on an 8323ERDB.

v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:44:56 -05:00
Kim Phillips
dfe812c744 mpc83xx: use "A" nomenclature only on mpc834x and mpc836x families
marketing didn't extend their postpend-with-an-A naming strategy
on rev.2's and higher beyond the first two 83xx families.  This
patch stops us from misreporting we're running e.g., on an MPC8313EA,
when such a name doesn't exist.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:34:49 -05:00
Rini van Zetten
27ef578df7 mpc83xx: Use CONFIG_FSL_ESDHC to enable sdhc clk
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define
instead of a platform define. This will enable all the 83xx
platforms to use sdhc_clk based on CONFIG_FSL_ESDHC.  It's
the same patch as commit 6b9ea08c50
for the ppc/85xx.

Signed-off-by: Rini <rini@arvoo.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:34:22 -05:00
Stefan Roese
a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00
Stefan Roese
cf6eb6da43 ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.

Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-19 15:29:03 +02:00
Scott McNutt
254ab7bd46 nios2: Move individual board linker scripts to common script in cpu tree.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-16 16:12:39 -04:00
Michal Simek
8ff972c6e9 microblaze: Consolidate cache code
Merge cpu and lib cache code.
Flush cache before disabling.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:56:33 +02:00
Michal Simek
9b4d905690 microblaze: Flush cache before jumping to kernel
There is used max cache size on system which doesn't define
cache size.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:16:04 +02:00
Michal Simek
70524883b0 microblaze: Support system with WB cache
WB cache use different instruction that WT cache but the major code
is that same. That means that wdc.flush on system with WT cache
do the same thing as before.

You need newer toolchain with wdc.flush support.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:16:02 +02:00
Michal Simek
9769b73f60 microblaze: Change initialization sequence
env_relocation should be called first.
Added stdio_init too.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:56 +02:00
Michal Simek
e6177b36b8 microblaze: Change cache report messages
It is more accurate to show that caches are OFF instead of FAIL.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:36 +02:00
Michal Simek
8125c980cc microblaze: Fix interrupt handler code
It is better to read ivr and react on it than do long parsing from
two regs. Interrupt controller returs actual irq number.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:34 +02:00
Michal Simek
b26640971a microblaze: Move FSL initialization to board.c
Move FSL out of interrupt controller.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:33 +02:00
Michal Simek
5bbcb6cf22 microblaze: Move timer initialization to board.c
I would like to handle case where system doesn't contain
intc that's why I need timer initialization out of intc code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:31 +02:00
Michal Simek
cc53690e05 microblaze: Fix irq.S code
It is ancient code. There is possible to save several instructions
just if we use offset instead of addik

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:30 +02:00
Arun Bhanu
398b1d57a6 microblaze: Add FDT support
This patch adds FDT (flattened device tree) support to microblaze arch.

Tested with Linux arch/microblaze kernels with and without compiled in
FDT on Xilinx ML506 board.

Signed-off-by: Arun Bhanu <arun@bhanu.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:13 +02:00
Stefan Roese
2a72e9ed18 ppc4xx: Add option for PPC440SPe ports without old Rev. A support
The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 10:27:39 +02:00
Peter Tyser
37e4dafaae nios2: Move cpu/nios2/* to arch/nios2/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:27 +02:00
Peter Tyser
6a8a2b7058 nios: Move cpu/nios/* to arch/nios/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:27 +02:00
Peter Tyser
1e9c26578e sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23]
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
e9a882803e i386: Move cpu/i386/* to arch/i386/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
6260fb0458 microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
8a15c2d10b avr32: Move cpu/at32ap/* to arch/avr32/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
1e3827d9cf mips: Move cpu/mips/* to arch/mips/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
c6fb83d217 blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
a414553485 m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:24 +02:00
Peter Tyser
84ad688473 arm: Move cpu/$CPU to arch/arm/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:24 +02:00
Peter Tyser
8f0fec74ac sh: Move cpu/$CPU to arch/sh/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:17 +02:00
Peter Tyser
8d1f268204 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:16 +02:00
Peter Tyser
819833af39 Move architecture-specific includes to arch/$ARCH/include/asm
This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:12 +02:00
Peter Tyser
ea0364f1bb Move lib_$ARCH directories to arch/$ARCH/lib
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk

This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:03 +02:00