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707 commits

Author SHA1 Message Date
Andre Przywara
081b160aa3 exynos: fix header inclusion guard
It seems like the header inclusion guard for the Exynos pinctrl header
was misspelled.

Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-31 12:31:47 -04:00
Peng Fan
99ac6c769f imx: move imx8 sci header file to include/firmware/imx
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21 16:54:32 +02:00
Ralph Siemsen
e4aea57fa7 pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.

This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Daniel Golle
bcfb23ec7e pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded
Commit dafe0fbfb0 ("pinctrl: mediatek: rewrite mtk_pinconf_set and
related functions") changed the logic deciding to set R0 and R1
registers for V1 devices.

Before:
	/* Also set PUPD/R0/R1 if the pin has them */
	err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
	if (err != -EINVAL) {
		mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
		mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
	}

After:
	/* try pupd_r1_r0 if pullen_pullsel return error */
	err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
						  val);
	if (err)
		return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
						       pullup, val);

Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function
always either returns 0 in case of success or -EINVAL in case any error
has occurred. Hence the logic responsible of the decision to program R0
and R1 has been inverted.

This leads to problems on BananaPi R2 (MT7623N) when booting from
SDMMC, it turns out accessing eMMC no longer works since
U-Boot 2022.07:

MT7623> mmc dev 0
Card did not respond to voltage select! : -110

The problem wasn't detected for a long time as both eMMC and SDMMC work
fine if they are used to boot from, and hence R0 and R1 were already
setup by the bootrom and/or preloader.

Fix the logic to restore the originally intended and correct behavior
and also change the descriptive comment accordingly.

Fixes: dafe0fbfb0 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Tested-By: Frank Wunderlich <frank-w@public-files.de>
2023-05-03 09:05:24 -04:00
Samuel Holland
7a85585fbc pinctrl: sunxi: Add NAND pinmuxes
NAND is always at function 2 on port C.

Pin lists and mux values were taken from the Linux drivers.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28 01:06:57 +01:00
Tom Rini
328fdeb9c9 Merge tag 'u-boot-rockchip-20230421' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
2023-04-23 12:15:56 -04:00
Tom Rini
802132c48a Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture
2023-04-22 18:31:46 -04:00
Jonas Karlman
518fa3441e pinctrl: rockchip: Fix IO mux selection on RK3568
IO mux selection is not working correctly for all pins. Sync mux route
data from linux to add any missing and update wrong trigger pins to fix
this. Also apply the pull-up fix needed for GPIO0 D3-D6.

Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:01 +08:00
Jianqun Xu
4f51064533 pinctrl: rockchip: support rk3588 pinctrl
Add support for Rockchip rk3588 variant of pinctrl.

The driver is adapted from the Linux driver.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[eugen.hristev@collabora.com:
port to latest U-boot, bring more changes from Linux
use translated pull values table]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:00 +08:00
Kuan Lim Lee
732f01aabf pinctrl: starfive: Add StarFive JH7110 driver
Add pinctrl driver for StarFive JH7110 SoC.

Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20 16:08:44 +08:00
Patrice Chotard
bff0d846c7 pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
For debug purpose, it should be useful to indicate the slew rate for
each pins.
Add ospeed register information for pins which are configured in
either alternate function or gpio output.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19 09:50:32 +02:00
Hai Pham
de4c777e3e pinctrl: renesas: Add R8A779G0 V4H PFC tables
Add pinctrl tables for R8A779G0 V4H SoC.

Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, sort sh_pfc_pinconf_set voltage args]
2023-04-07 17:13:28 +02:00
LUU HOAI
1b1834c037 pinctrl: renesas: Add R8A779F0 S4 PFC tables
Add pinctrl tables for R8A779F0 S4 SoC.

Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
2023-04-07 17:13:28 +02:00
Quanyang Wang
d0bb00adcc pinctrl: fix pinctrl_gpio_get_pinctrl_and_offset for gpio-ranges array
Sometimes a multi-element array is used for "gpio-ranges" property in
dts file:

    qe_pio_e: gpio-controller@1460 {
        ......
        gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
        ......
    };

But the function pinctrl_gpio_get_pinctrl_and_offset can't handle this
case because the "index" argument passed to dev_read_phandle_with_args
is fixed to be "0". Use a loop to traverse the array to fix it.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
2023-04-03 06:53:53 +12:00
Marek Vasut
ce46817215 pinctrl: renesas: Drop non-existent PFC info table entries
Remove PFC info table entries which are never instantiated,
since there are no drivers for those. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:46:09 +01:00
Robert Marko
1de76a4535 arm64: a37xx: pinctrl: probe after binding
Currently, pinctrl drivers are getting probed during post-bind, however
that is being reverted, and on A37XX pinctrl driver is the one that
registers the GPIO driver during the probe.

So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.

This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.

So, lets just add a flag only to A37XX driver to probe after binding
in order for the GPIO driver to always get registered.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01 11:22:27 -07:00
Jagan Teki
1977d746aa rockchip: rk3568: add rk3568 pinctrl driver
Add driver supporting pin multiplexing on rk3568 platform.

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Simon Glass
42a13b21dc Correct SPL use of ATMEL_PIO4
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ATMEL_PIO4 defined in Kconfig

Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 08:22:52 -05:00
Simon Glass
68be8d95de Correct SPL uses of OF_BOARD
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_OF_BOARD defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
2023-02-10 07:41:41 -05:00
Simon Glass
ef746bfd2c Correct SPL use of SANDBOX
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SANDBOX defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Hai Pham
eaa4a7d411 pinctrl: renesas: r8a7796: Add R8A77961 PFC support
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960),
which allows for both SoCs to share a driver.

Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add
R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796:
Optimize pinctrl image size for R8A774A1")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-02-02 01:49:20 +01:00
Marek Vasut
8a9e8ba9ae pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
37fb54b6e6 pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
a22eba36a9 pinctrl: renesas: Synchronize R8A77990 E3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77990 E3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
3bf4933555 pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.1.7
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
84d7588cc6 pinctrl: renesas: Synchronize R8A77970 V3M PFC tables with Linux 6.1.7
Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
50970e8c2d pinctrl: renesas: Synchronize R8A77965 M3-N PFC tables with Linux 6.1.7
Synchronize R-Car R8A77965 M3-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
0a57a382af pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to
PINCTRL_PFC_R8A77960 .

Also note that a new Kconfig option has been added to enable support
for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
9916e8bfc6 pinctrl: renesas: Synchronize R8A7795 H3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7795 H3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7795 to
PINCTRL_PFC_R8A77951 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
f46776cce0 pinctrl: renesas: Synchronize R8A7794 E2 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7794 E2 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
f36c55fc6d pinctrl: renesas: Synchronize R8A7792 V2H PFC tables with Linux 6.1.7
Synchronize R-Car R8A7792 V2H PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
9a955714a1 pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
f8ea2a6779 pinctrl: renesas: Synchronize R8A7790 H2 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7790 H2 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
3e81242160 pinctrl: renesas: Synchronize PFC core with Linux 6.1.7
Synchronize R-Car PFC core with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Parts picked from
pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3
- Add pin groups for the green and high8 subsets of the Video IN pins
- Add MediaLB pins
- Add bias support for various SoCs
- Share more pin group data, to reduce size and ease review
- Miscellaneous cleanups, fixes and improvements.

This contains port of Linux kernel commit
6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields")
to handle negative entries in GROUP() macros correctly.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Michael Walle
e71505fc98 pinctrl: fix docstring
Fix the copy and paste error.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-27 12:51:26 -05:00
Michael Walle
75013fa724 pinctrl: get rid of some ifdeffery
Don't define an empty version for pinconfig_post_bind(). Just guard the
call and let the linker garbage collection do the rest. This way, we
also don't have to do any guesswork.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-27 12:51:26 -05:00
Michael Walle
72b8c6d1eb pinctrl: don't fall back to pinctrl_select_state_simple()
If CONFIG_PINCTRL_FULL is enabled, never fall back to the simple
implementation. pinctrl_select_state() is called for each device and it
is expected to fail. A fallback to the simple imeplementation doesn't
make much sense.

To keep the return code consistent, we need to change the -EINVAL (which
was ignored before) to -ENOSYS.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-27 12:51:26 -05:00
Tom Rini
6e7df1d151 global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-20 12:27:24 -05:00
Simon Glass
85d87112cb dm: pinctrl: Revert "pinctrl: probe pinctrl drivers during post-bind"
This breaks chromebook_coral and it is also not how things should work. If
a board needs to bind GPIOs as part of a pinctrl driver this can be done
during the bind step, if needed.

We cannot probe pinctrl devices when binding as a rule, since it cannot be
supported on some platforms.

The bind and probe steps are separate in U-Boot and they should remain
separate.

This reverts commit f9ec791b5e.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:13 -07:00
Jagan Teki
8430a87502 pinctrl: rockchip: Add rv1126 support
Add pinctrl driver for Rockchip RV1126.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
32b2ea9818 pinctrl: rockchip: Add pinctrl route types
Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.

Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jim Liu
7ee1c4d1d1 pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-01-10 15:39:06 -05:00
Dai Okamura
ef75d482aa pinctrl: uniphier: add ethernet TX pin data for PXs3
PXs3 Ref boards need to change the strength of ethernet ports
for stability, like LD20's one.

This adds the table data and fixes the boot issue on PXs3 Ref board.

Fixes: 0852033309 ("ARM: uniphier: sync with Linux 5.8-rc4")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 14:10:23 -05:00
Dai Okamura
1e91a0ea32 pinctrl: uniphier: add check if pins are valid
The pinctrl datas of uniphier SoCs are the minimal subsets of kernel's one,
and some tables has no data to save the footprint size.
If the board dts tries to match a pin name on no pins defined SoC,
the footprint magic code causes "Synchronous Abort".

This checks if the 'pins' data is valid,
and if empty, avoids the abort with the warning as follows:

  WARNING at drivers/pinctrl/uniphier/pinctrl-uniphier-core.c:36/uniphier_pinctrl_get_pins_count()!
  pinctrl_select_state_full: pinctrl_config_one: err=-38

Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 14:10:23 -05:00
Samuel Holland
6cad8bea4f pinctrl: sunxi: Add P2WI and RSB pinmuxes
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-13 20:33:37 +00:00
Michal Simek
716527299a Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance"
This reverts commit 123462e5e5.

On systems with older PMUFW using these pinctrl properties can cause system
hang because there is missing feature autodetection.
When it is implemented support for these two properties should go back.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Chris Packham
c249938214 pinctrl: mvebu: Add AlleyCat5 support
This uses the same IP block as the Armada-8K SoCs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:46:28 +01:00
Jim Liu
1c1036499f pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-11-02 13:31:40 -04:00
Andre Przywara
843ed983a0 suniv: add UART1 support
Some boards with the Allwinner F1C100s family SoCs use UART1 for its
debug UART, so define the pins for the SPL and the pinmux name and mux
value for U-Boot proper.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19 14:15:02 +01:00
John Keeping
7eda1a9533 pinctrl: fix buffer size for pinctrl_generic_set_state_prefix()
This buffer has the concatenated prefix and name written into it, so it
must be large enough to cover both strings plus the terminating NUL.

Fixes: 92c4a95ec7 ("pinctrl: Add new function pinctrl_generic_set_state_prefix()")
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-11 15:40:48 -04:00
Jim Liu
45455e8ff5 pinctrl: nuvoton: fix set persist error
CA9C is cortex A9 watchdog reset control bit.
if device set persist mode, it shouldn't set this bit.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-11 15:40:48 -04:00
Weijie Gao
59acdf8afe pinctrl: mediatek: add pinctrl driver for MT7986 SoC
This patch adds pinctrl and gpio support for MT7986 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
ace67d1097 pinctrl: mediatek: add pinctrl driver for MT7981 SoC
This patch adds pinctrl and gpio support for MT7981 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Sergiu Moga
7086defa04 pinctrl: at91-pio4: Add support for pinctrl config subnodes
Previously, in order for the `pinctrl-*` DT node properties
to be properly processed, the pinctrl's subnodes were limited
to only having the `pinmux` property as well as other additional
properties (slew-rate, bias-disable, etc.). Now, with this patch
the pinctrl driver is made to work similarly to the one from Linux.
It can now distinguish between one subnode and a subnode with multiple
subnodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2022-09-19 09:51:04 +03:00
Sergiu Moga
2ed96a87d2 pinctrl: at91-pio4: Bind GPIO driver to the pinctrl DT node
This has been done in order to align the DT of U-Boot with the DT
of Linux. In Linux, a phandle from a '-gpio' DT property is linked
to the pinctrl driver, a single driver that handles both pinctrl
settings and offers GPIO API to callers. On the other hand,
U-Boot redirects such phandle to a corresponding UCLASS_GPIO
driver, because U-Boot offers two different types of drivers
in this case: UCLASS_PINCTRL which handles pin functions and
UCLASS_GPIO which handles gpio requests as a gpio provider.
Due to this, we have two drivers in Uboot, but the Devicetree
has a single node. Thus, just one of the drivers can be probed
for the DT node during platform initialization, before relocation.

Our previous solution in U-Boot was to have a different devicetree:
the gpio node has a subnode for the pinctrl driver, which
is not compliant with Linux ABI. Furthermore, our documentation
for this type of nodes mentions no such gpio compatible.

After this patch, we can no longer add nodes with a gpio
compatible in the DT. Thus, in order to link the pinctrl driver to
the gpio one, a hook to the bind method of the former in U-Boot has
been added and the GPIO related compatibles have been removed to
avoid conflict when compatibles are enumerated and bound to drivers
during platform start before relocation. The bind method will attach
the GPIO driver to the pinctrl DT node so that every phandle coming
from '-gpio' DT properties will be redirected to a valid driver
attached to the pinctrl DT node.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2022-09-19 09:51:04 +03:00
Patrice Chotard
2c38f7c318 pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name
Populate uc_priv->name[] with pinmux node's name in order to indicate
the pinmuxing's name in case GPIO is configured in alternate.

For example, for STM32 SoC's based platform, "gpio status" command
output :

  before
    Bank GPIOZ:
      GPIOZ0: unused : 0 [ ]
      GPIOZ1: unused : 0 [ ]
      GPIOZ2: unused : 0 [ ]
      GPIOZ3: unused : 0 [ ]
      GPIOZ4: func
      GPIOZ5: func
      GPIOZ6: unused : 0 [ ]
      GPIOZ7: unused : 0 [ ]
      GPIOZ8: unknown
      GPIOZ9: unknown
      GPIOZ10: unknown
      GPIOZ11: unknown
      GPIOZ12: unknown
      GPIOZ13: unknown
      GPIOZ14: unknown
      GPIOZ15: unknown

  After
    Bank GPIOZ:
      GPIOZ0: unused : 0 [ ]
      GPIOZ1: unused : 0 [ ]
      GPIOZ2: unused : 0 [ ]
      GPIOZ3: unused : 0 [ ]
      GPIOZ4: func i2c4-0
      GPIOZ5: func i2c4-0
      GPIOZ6: unused : 0 [ ]
      GPIOZ7: unused : 0 [ ]
      GPIOZ8: unknown
      GPIOZ9: unknown
      GPIOZ10: unknown
      GPIOZ11: unknown
      GPIOZ12: unknown
      GPIOZ13: unknown
      GPIOZ14: unknown
      GPIOZ15: unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-15 09:55:30 -04:00
Chin-Ting Kuo
cf2051ac4c pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13 12:08:40 -04:00
Pali Rohár
019090647c arm64: a37xx: pinctrl: Improve description for pinmux command
In more cases group name consist of function name followed by function
number. So if function name is just prefix of group name, show group name.

So in 'pinmux status -a' command output would be visible also extended
function number, which is useful for debugging.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Pali Rohár
361cf5c7e1 arm64: a37xx: pinctrl: Remove unused macro PIN_GRP()
Macro PIN_GRP() is not used, remove it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Pali Rohár
7a1c071173 arm64: a37xx: pinctrl: Fix definitions for MPP pins 20-22
All 3 MPP pins (20, 21 and 22) can be configured individually and also can
be configured to GPIO functions. Fix definitions for these MPP pins in
existing pin groups. After this change GPIO function can be enabled just
for one of these 3 pins.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Konstantin Porotchkin
ef6fcab85f mvebu: pinctrl: apply SDHCI PHY config for A7K
Current pin control driver applies SDHCI PHY MUX selection
when board DT calls for eMMC function on MPP wires.
However, for CP side eMMC, only the "armada-8k-cpm-pinctrl"
compatibility string is taken into account, which causes
CP-SDHCI on Armada-7K boards to fail.
This patch adds "armada-7k-pinctrl" compatibility string
handling for the CP-SDHCI PHY configuration case.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
e34d8afd72 arm64: a37xx: pinctrl: Implement get_pins_count, get_pin_name and get_pin_muxing functions
These functions are required for 'pinmux status -a' command to print
current configuration of each MPP pin.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
140ebcdb9a arm64: a37xx: pinctrl: Implement gpio_request_enable for gpio functionality
To automatically enable GPIO functionality of some MPP pin, it is required
to implement .gpio_request_enable and .gpio_disable_free callbacks in
pinctrl driver and set .request and .rfree callbacks in GPIO driver to
pinctrl_gpio_request / pinctrl_gpio_free functions.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
3d98071dbb arm64: a37xx: pinctrl: Add missing pinmuxes into the list
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
ffab049520 arm64: a37xx: pinctrl: Mark all functions and structures as static
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
33893e5278 arm64: a37xx: pinctrl: Remove duplicate info->groups and info->ngroups fields
They are available in pin_data structure.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
bd913a7233 arm64: a37xx: pinctrl: Remove unused grp->pins fields
grp->pins is just filled and never used. Remove it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
a1de1035b2 pinctrl: Add third argument label for pinctrl_gpio_request() function
This change allows to use pinctrl_gpio_request() function as a direct
pointer for dm_gpio_ops's .request callback.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-28 15:17:45 +02:00
Pali Rohár
35c50a709e mvebu: pinctrl: Add Armada 38x driver
This new Armada 38x driver is based on Linux kernel driver. It can set any
pin to any valid function specified in DT like Linux kernel, it provides
support for 'pinmux status -a' command and also for pinctrl_gpio_request().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-28 08:41:44 +02:00
Pali Rohár
92c4a95ec7 pinctrl: Add new function pinctrl_generic_set_state_prefix()
This new function pinctrl_generic_set_state_prefix() behaves like
pinctrl_generic_set_state() but it takes third string argument which is
used as the prefix for each device tree string property.

This is needed for Marvell pinctrl drivers, becase Linux device tree files
have pinmux properties prefixed by "marvell," string.

This change allows to use generic U-Boot pinctrl functions for Armada 38x
pinctrl driver without need to copy+paste of the majority U-Boot pinctrl
code.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-28 08:41:44 +02:00
Peng Fan
07110c6f53 imx: pinctrl: add pinctrl and pinfunc file for i.MX93
Add the pinctrl driver and pinfunc header file to support iMX93

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Weijie Gao
4d30111cea pinctrl: mtmips: add support for MediaTek MT7621 SoC
This patch adds pinctrl support for MediaTek MT7621 SoC.
The MT7621 SoC supports pinconf, but it is not the same as mt7628.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-13 23:03:37 +02:00
Tom Rini
c316ee674f Xilinx changes for v2022.10
cpu:
 - Add driver for microblaze cpu
 
 net:
 - Add support for DM_ETH_PHY to AXI emac and emaclite
 
 xilinx:
 - Switch platforms to DM_ETH_PHY
 - DT chagnes in ZynqMP and Zynq
 - Enable support for SquashFS
 
 zynqmp:
 - Add support for KR260 boards
 - Move BSS from address 0
 - Move platform identification from board code to soc driver
 - Improve zynqmp_psu_init_minimize
 
 versal:
 - Enable loading app at EL1
 
 serial:
 - Setup default address and clock rates for DEBUG uarts
 
 pinctrl:
 - Add support for tri state and output enable properties
 
 relocate-rela:
 - Clean relocate-rela implementation for ARM64
 - Add support for Microblaze
 
 microblaze:
 - Add support for runtime relocation
 - Rework cache handling (wiring, Kconfig) based on cpuinfo
 - Remove interrupt support
 
 timer:
 - Extract axi timer driver from Microblaze to generic location
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Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
2022-06-27 10:15:50 -04:00
Ashok Reddy Soma
123462e5e5 pinctrl: zynqmp: Add support for output-enable and bias-high-impedance
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. DT property output-enable brings out the pins from
tri-state, whereas bias-high-impedance changes the pins state to
tri-state.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1a02cd41d183d397ebce23c497178281c7286692.1655286745.git.michal.simek@amd.com
2022-06-24 14:14:29 +02:00
Patrick Delaunay
eae488b779 stm32mp1: fix reference for STMicroelectronics
Replace reference to the correct name STMicroelectronics

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 14:12:27 +02:00
Patrick Delaunay
cf1d0fd4c1 pinctrl: stm32: add support of STM32MP135
Add support for "st,stm32mp135-pinctrl" for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Jim Liu
f49d616bea pinctrl: nuvoton: Add NPCM7xx pinctrl driver
Add Nuvoton BMC NPCM750 Pinmux and Pinconf support.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-10 13:37:32 -04:00
Robert Marko
f9ec791b5e pinctrl: probe pinctrl drivers during post-bind
Currently, pinctrl drivers only get probed if pinconf is actually being
used, however on SoC-s like Armada 3720 pinctrl driver is a also the GPIO
driver.

So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.

This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.

So, probe the pinctrl drivers using DM_FLAG_PROBE_AFTER_BIND like LED
uclass does.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Patrice Chotard
427f452cb9 gpio: stm32_gpio: Rework GPIO hole management
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
  If GPIO bank have 16 GPIO pins [0-15].
  In particular SoC's package case, some GPIO bank can have less GPIO pins:
    - [0-10] => 11 pins;
    - [2-7] => 6 pins.

Commit dbf928dd26 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.

To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.

stm32_offset_to_index() is no more needed and removed.

This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:

Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0          : unknown
GPIOI1          : unknown
GPIOI2          : analog
GPIOI3          : analog
GPIOI4          : alt function 0 push-pull pull-down
GPIOI5          : alt function 0 push-pull pull-down
GPIOI6          : alt function 0 push-pull pull-down
GPIOI7          : analog
GPIOI8          : unknown
GPIOI9          : unknown
GPIOI10         : unknown
GPIOI11         : unknown
GPIOI12         : unknown
GPIOI13         : unknown
GPIOI14         : unknown
GPIOI15         : unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:54:48 +02:00
Patrice Chotard
234b03f3a9 pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins
GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
that a pin is not mapped.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:54:48 +02:00
Patrice Chotard
4382e55c42 pinctrl: pinctrl_stm32: Update pinmux_mode definition
pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
So reuse the same gpio_func_t enum value

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:54:48 +02:00
Sam Shih
1a80ef5520 pinctrl: mediatek: add support for different types of IO pins
There are many pins in an SoC, and register usage may vary by pins.
This patch introduces a concept of "io type" and "io type group"
to mediatek pinctrl drivers. This can provide different pinconf
handlers implementation (eg: "bias-pull-up/down", "driving" and
"input-enable") for IO pins that belong to different types.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05 09:29:58 -04:00
Sam Shih
10334e0bc8 pinctrl: mediatek: introduce multiple memory bases support
Pinctrl design of some mediatek SoC need to access registers that
distribute in multiple memory base address. this patch introduce new
mechanism in mediatek pinctrl driver to support the chips which have
the new design.

This patch add a member 'base_calc' in pinctrl private data, and changed
original 'base' private data to an array of *iomem.

When 'base_calc' attribute is set, it will requests multiplue regs base
from the DT, if 'base_calc' attribute is not set, it only use legacy way
to request single reg resource from the DT.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05 09:29:58 -04:00
Sam Shih
dafe0fbfb0 pinctrl: mediatek: rewrite mtk_pinconf_set and related functions
There are many pins in a SoCs, and different pin may belong
to different "io_type", For example: some pins of MT7622 belongs
to "io_type A", the other belongs to "io_type B", and pinctrl "V0"
means handle pinconf via "io_type A" or "io_type B", so SoCs that
contain "io_type A" and "io_type B" pins, use "V0" in pinctrl driver.

This patch separates the implementation of register operations
(e.g: "bias-pull-up/down", "driving" and "input-enable") into
different functions, and lets the original V0/V1
ops to call the new functions.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05 09:29:57 -04:00
Simon Glass
747093dd40 vpl: Add Kconfig options for VPL
Add VPL versions of commonly used Kconfig options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-05-02 09:58:13 -04:00
Paweł Jarosz
086863c982 rockchip: rk3066: add rk3066 pinctrl driver
Add driver supporting pin multiplexing on rk3066 platform.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Angus Ainslie
9eb5e7d9ab pinctrl: nxp: don't automatically select DEVRES
If we select DEVRES here then it breaks building an imx8m SPL without
DEVRES support.

Signed-off-by: Angus Ainslie <angus@akkea.ca>
2022-04-12 15:36:17 +02:00
Tom Rini
4de720e98d Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-05 08:33:32 -04:00
Samuel Holland
77834dcc5b pinctrl: sunxi: Add SPI0 pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
aa4823ce48 pinctrl: sunxi: Add the A64 PWM pinmux
This is the only possible mux setting for the A64's PWM peripheral.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
7570c54e46 pinctrl: sunxi: Add MMC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
4c8f11d4af pinctrl: sunxi: Add I2C pinmuxes
Where multiple options were available, the one matching board.c and the
device trees was chosen.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fixup H5 I2C1 pinmux]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
37b3de432f pinctrl: sunxi: Add sun8i EMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
7a93644c69 pinctrl: sunxi: Add sunxi GMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
fcdbbd68d3 pinctrl: sunxi: Add sun4i EMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
470a7bdb61 pinctrl: sunxi: Add UART pinmuxes
This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
50c195ee85 sunxi: pinctrl: Implement pin configuration
The sunxi pinctrl hardware has bias and drive control. Add driver
support for configuring those options.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:01 +01:00
Samuel Holland
d4b388244a sunxi: pinctrl: Implement get_pin_muxing function
The pinmux command uses this function to display pinmux status.

Since the driver cannot map pin numbers to a list of supported
functions, only functions which are common across all pins can be
reported by name.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:01 +01:00
Samuel Holland
29babfd92b sunxi: pinctrl: Implement pin muxing functions
Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.

We assume all pins associated with a function use the same mux value for
that function. This is generally true within a group of pins on a single
port, but generally false when some peripheral can be muxed to multiple
ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
But all of the port D pins use the same mux value, and so do all of the
port H pins. This applies even when the pins for some function are not
contiguous, and when the lower-numbered mux values are unused. A good
example of both of these cases is SPI0 on most SoCs.

This strategy saves a lot of space (which is especially important for
SPL), but where the mux value for a certain function differs across
ports, it forces us to choose a single port for that function at build
time. Since almost all boards use the default (i.e. reference design)
pin muxes[1], this is unlikely to be a problem.

[1]: See commit dda9fa734f ("sunxi: Simplify MMC pinmux selection")

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: add comment summarising the commit message]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:01 +01:00
Samuel Holland
b799eabc7e sunxi: pinctrl: Create the driver skeleton
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:23:50 +01:00