Commit graph

11917 commits

Author SHA1 Message Date
Rick Chen
1a9db640b4 nds32: ftsdc010: fix wait status error coding.
Bit of DATA_END and DATA_CRC_OK shall be checked for
returning pass or fail of a request.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 10:04:30 +08:00
Rick Chen
252185f224 nds32: ftsdc010: Support ftsdc010 DM.
ftsdc010 support device tree flow.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 10:01:50 +08:00
Rick Chen
9f678ab139 nds32: mmc: Support ftsdc010 DM.
Add nds32_mmc to support ftsdc010 dm flow.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 09:59:09 +08:00
Rick Chen
6720e4ae7a cosmetic: atcspi200: Rename function name as atcspi200
Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 09:45:21 +08:00
Rick Chen
41bbb8b333 spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 09:44:09 +08:00
Rick Chen
0f4a395f78 atcpit100: timer: Remove arch dependency.
ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 09:39:31 +08:00
Rick Chen
c6c85dc87d cosmetic: atcpit100_timer: Use device api to get platdata
Use dev_get_platdata to get private platdata.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 09:39:07 +08:00
Rick Chen
033d408102 cosmetic: atcpit100_timer: Rename function name as atcpit100
Integrate function and struct name as atcpit100 will be
more reasonable.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 09:39:01 +08:00
Rick Chen
fa3e354b2b ae3xx: timer: Rename AE3XX to ATCPIT100
ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 09:38:54 +08:00
Rick Chen
0e920ef052 ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.
It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 09:38:21 +08:00
Marek Vasut
52c8034bb4 gpio: rmobile: Set GPIO mode in GPSR when requested
When requesting a GPIO, set the PFC GPSR register to GPIO mode,
otherwise the GPIO cannot work.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:21 +01:00
Marek Vasut
f6e545a73f pfc: rmobile: Add hook to configure pin as GPIO
Add hook into the PFC driver to allow the GPIO driver to toggle
GPSR registers into GPIO mode when GPIO is requested.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:21 +01:00
Marek Vasut
2489bb54a5 pinctrl: rmobile: Add support for setting single pins
Add code to handle single pins nodes from DT in addition to already
support groups handling.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:34:21 +01:00
Marek Vasut
90997cda76 net: ravb: Fix reset GPIO handling
Fix handling of the reset GPIO. Drop the _nodev() suffix from the
gpio_request_by_name() call as there is now a proper DM capable
GPIO driver. Also check if the GPIO is valid before freeing it in
remove path, otherwise U-Boot will crash.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:34 +01:00
Marek Vasut
9e75ea46d5 i2c: rcar_iic: Add RCar IIC driver
Add driver for the RCar IIC or DVFS I2C controller. This driver is based
on the SH I2C driver, but supports DM and DT probing as well as modern
I2C framework API.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:34 +01:00
Marek Vasut
167ee838df serial: sh: Unify R8A7795 and R8A7796 as Gen3
Unify the CONFIG_R8A7795 and CONFIG_R8A7796 as CONFIG_RCAR_GEN3
so that every time we add a new SoC, we won't have to add more
stuff to this list.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:34 +01:00
Marek Vasut
033b611989 clk: rmobile: Add R8A7796 xHCI clock
Add xHCI entry into the clock tables, so that the xHCI USB driver
can enable the clock for the xHCI block via clock framework.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:33 +01:00
Marek Vasut
18cac5afc2 clk: rmobile: Move preboot clock shutdown to the driver
The MSTP registers were poked in boards/renesas/rcar-common/common.c
in arch_preboot_os hook thus far to shut down the clock before Linux
takes over. With DM, this is no longer needed and we can do the same
in the clock driver .remove callback. This patch adds such a .remove
callback for R8A7795 and R8A7796.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:33 +01:00
Tom Rini
b06c46de63 Xilinx changes for v2018.1
Zynq:
 - Add support for Syzygy and cc108 boards
 - Add support for mini u-boot configurations (cse)
 - dts updates
 - config/defconfig updates in connection to Kconfig changes
 - Fix psu_init handling
 
 ZynqMP:
 - SPL fixes
 - Remove slcr.c
 - Fixing r5 startup sequence
 - Add support for external pmufw
 - Add support for new ZynqMP chips
 - dts updates
 - Add support for zcu102 rev1.0 board
 
 Drivers:
 - nand: Support external timing setting and board init
 - ahci: Fix wording
 - axi_emac: Wait for bit, non processor mode, readl/write conversion
 - zynq_gem: Fix SGMII/PCS support
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Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
2017-11-29 08:26:07 -05:00
Siva Durga Prasad Paladugu
a04a5daae2 net: xilinx_axi_emac: Use readl and writel for io ops
This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Siva Durga Prasad Paladugu
dd12a27ce2 net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Joe Hershberger
6d3fa0dfdd mtd: nand: zynq: Add support for the NAND lock/unlock operation
Zynq NAND driver is not support for NAND lock or unlock operation.
Hence, accidentally write into the critical NAND region might cause
data corruption to occur.

This commit is to add NAND lock/unlock command into NAND SMC register
set for NAND lock/unlock operaion.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Wilson Lee
310995d9f9 mtd: zynq: nand: Move board_nand_init() function to board.c
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.

This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Siva Durga Prasad Paladugu
89ce5a9dbe net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesn't have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2017-11-29 08:02:33 +01:00
Tom Rini
fcc8250c2f Merge git://git.denx.de/u-boot-mips 2017-11-28 16:54:30 -05:00
Tom Rini
74a4818415 Merge git://git.denx.de/u-boot-uniphier 2017-11-28 16:54:09 -05:00
Paul Burton
c5bf161fac Update Paul Burton's email address
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Masahiro Yamada
e9986a4fa7 gpio: uniphier: import dt-binginds header from Linux
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
350d052dab mtd: nand: denali: sync with Linux 4.15-rc1
I largely reworked the Denali NAND controller driver in Linux.
This commit imports the improvements from Linux.  The code is
almost synced with Linux 4.15-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
e6001371d1 mtd: nand: introduce NAND_ROW_ADDR_3 flag
Several drivers check ->chipsize to see if the third row address cycle
is needed.  Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up.  Since
nand_scan_ident() knows well about the device, it can handle this
properly.  The flag is set if the row address bit width is greater
than 16.

Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
2017-11-29 00:28:59 +09:00
Masahiro Yamada
470c29d1c2 mtd: nand: add generic helpers to check, match, maximize ECC settings
Driver are responsible for setting up ECC parameters correctly.
Those include:
  - Check if ECC parameters specified (usually by DT) are valid
  - Meet the chip's ECC requirement
  - Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set

The logic can be generalized by factoring out common code.

This commit adds 3 helpers to the NAND framework:
nand_check_ecc_caps - Check if preset step_size and strength are valid
nand_match_ecc_req - Match the chip's requirement
nand_maximize_ecc - Maximize the ECC strength

To use the helpers above, a driver needs to provide:
  - Data array of supported ECC step size and strength
  - A hook that calculates ECC bytes from the combination of
    step_size and strength.

By using those helpers, code duplication among drivers will be
reduced.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 2c8f8afa7f92acb07641bf95b940d384ed1d0294]
2017-11-29 00:28:59 +09:00
Boris Brezillon
52cde35b96 mtd: nand: Pass the CS line to ->setup_data_interface()
Some NAND controllers can assign different NAND timings to different
CS lines. Pass the CS line information to ->setup_data_interface() so
that the NAND controller driver knows which CS line is concerned by
the setup_data_interface() request.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 104e442a67cfba4d0cc982384761befb917fb6a1]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
436fb2b84d mtd: nand: allow drivers to request minimum alignment for passed buffer
In some cases, nand_do_{read,write}_ops is passed with unaligned
ops->datbuf.  Drivers using DMA will be unhappy about unaligned
buffer.

The new struct member, buf_align, represents the minimum alignment
the driver require for the buffer.  If the buffer passed from the
upper MTD layer does not have enough alignment, nand_do_*_ops will
use bufpoi.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 477544c62a84d3bacd9f90ba75ffc16c04d78071]
2017-11-29 00:28:59 +09:00
Boris Brezillon
c7c553f249 mtd: nand: Wait for PAGEPROG to finish in drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the
full read/write page sequence, and waiting for a page to actually be
programmed is part of this write-page sequence.
This is also what is done in ->write_oob_xxx() hooks, so let's do that in
->write_page_xxx() as well to make it consistent.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 41145649f4acb30249b636b945053db50c9331c5]
[masahiro:
 There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot.
 No driver is affected by this change.]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
94b50a8aae mtd: nand: Drop the ->errstat() hook
The ->errstat() hook is no longer implemented NAND controller drivers.
Get rid of it before someone starts abusing it.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 7d135bcced20be2b50128432c5426a7278ec4f6d]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
4d75596e6d mtd: nand: Drop unused cached programming support
Cached programming is always skipped, so drop the associated code until
we decide to really support it.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 0b4773fd1649e0d418275557723a7ef54f769dc9]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
13f3b04f61 mtd: add mtd_ooblayout_xxx() helper functions
In order to make the ecclayout definition completely dynamic we need to
rework the way the OOB layout are defined and iterated.

Create a few mtd_ooblayout_xxx() helpers to ease OOB bytes manipulation
and hide ecclayout internals to their users.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 75eb2cec251fda33c9bb716ecc372819abb9278a]
[masahiro:
 cherry-pick more code from adbbc3bc827eb1f43a932d783f09ba55c8ec8379]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Marc Gonzalez
1fb87de83d mtd: nand: Support controllers with custom page
If your controller already sends the required NAND commands when
reading or writing a page, then the framework is not supposed to
send READ0 and SEQIN/PAGEPROG respectively.

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 3371d663bb4579f1b2003a92162edd6d90edd089]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
6f84b26b53 mtd: nand: Add a few more timings to nand_sdr_timings
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the
nand_sdr_timings struct.
Assign default/safe values for the statically defined timings, and
extract them from the ONFI parameter table if the NAND is ONFI
compliant.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[Linux commit: 204e7ecd47e26cc12d9e8e8a7e7a2eeb9573f0ba
 Fixup commit: 6d29231000bbe0fb9e4893a9c68151ffdd3b5469]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
3d841b3214 mtd: nand: Fix data interface configuration logic
When changing from one data interface setting to another, one has to
ensure a specific sequence which is described in the ONFI spec.

One of these constraints is that the CE line has go high after a reset
before a command can be sent with the new data interface setting, which
is not guaranteed by the current implementation.

Rework the nand_reset() function and all the call sites to make sure the
CE line is asserted and released when required.

Also make sure to actually apply the new data interface setting on the
first die.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: d8e725dd8311 ("mtd: nand: automate NAND timings selection")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[Linux commit: 73f907fd5fa56b0066d199bdd7126bbd04f6cd7b]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
27c4792cd2 mtd: nand: automate NAND timings selection
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.

Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.

NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[Linux commit: d8e725dd831186a3595036b2b1df9f68cbc6efa3]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Sascha Hauer
b893e83330 mtd: nand: Expose data interface for ONFI mode 0
The nand layer will need ONFI mode 0 to use it as timing mode
before and right after reset.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 6e1f9708dbf3c50a8da93c1952a01a7a2acb5e66]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Sascha Hauer
46deff57da mtd: nand: convert ONFI mode into data interface
struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: b1dd3ca203fccd111926c3f6ac59bf903ec62b05]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Sascha Hauer
1728eb577d mtd: nand: Create a NAND reset function
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 2f94abfe35b210e7711af9202a3dcfc9e779219a]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Boris Brezillon
19d30ded88 mtd: nand: Add an option to maximize the ECC strength
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.

In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).

Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82]
[masahiro: of_property_read_bool -> fdt_getprop for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Masahiro Yamada
ed3986ca30 bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places.  Collect them into
include/linux/bitops.h like Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Siva Durga Prasad Paladugu
dc1fcc423c net: xilinx_axi_emac: Read dma address using fdtdec_get_addr
Read dma address using fdtdec_get_addr as it checks for
address cells and size cells and reads the address
properly. fdtdec_get_int always assume address is of int
size which goes wrong if using it on 64-bit architecture.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:27 +01:00
Siva Durga Prasad Paladugu
d02a0b1fdf net: xilinx_axi_emac: Use wait_for_bit instead of while loop
Use wait_for_bit instead while loop during init

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2017-11-28 16:09:27 +01:00
Michal Simek
e81589ea44 ata: Fix ahci wording
s/achi_/ahci_/g

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 16:08:52 +01:00
Michal Simek
809704eb4f arm: zynq: Move ZYNQ_SERIAL to Kconfig
Move cadence/zynq serial driver via Kconfig

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 16:08:45 +01:00
Jeff Westfahl
8000d6ea3f mtd: nand: zynq: Add a config option to use 1st stage bootloader timing
In legacy method, 1st stage bootloader was used to configure the HW
setting such as NAND timing. Hence, adding a config option in Zynq
NAND driver for the compatibility of device that using 1st stage
bootloder instead of U-boot SPL.

This commit is to add config option
CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use
timing values set by the 1st stage bootloader, instead of the hard-coded
values in the Zynq NAND driver.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Tom Rini
65972a0b62 Merge git://git.denx.de/u-boot-socfpga 2017-11-28 09:30:36 -05:00
Tom Rini
53fe692652 Merge git://git.denx.de/u-boot-usb 2017-11-28 09:30:27 -05:00
Chris Brandt
11f4678962 usb: r8a66597: Add support for RZ/A series
While the USB HW in the RZ/A is basically the same, there are some
differences from the original versions that were in the SH SoCs.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2017-11-28 04:06:40 +01:00
Tom Rini
6e6cf015e7 Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-27 07:22:11 -05:00
Jagan Teki
bb0297ccbd pinctrl: imx6ul: Fix pinctrl data overlapped with DT area
before relocation pinctrl data BSS is overlapping DT area,
when .data is using uninitialized global variable,
imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID
to prevent BSS overlap

Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-27 10:36:40 +01:00
Tien Fong Chee
bd08ce8f5e arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes
Existing FPGA program write is always assume RBF data >= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size >= 4 bytes.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2017-11-26 02:34:10 +01:00
Vincent Prince
8171dac00d Trigger watchdog before calling usb_gadget_handle_interrupts
This prevents board resets when calling sdp command on boards which have a watchdog.

Signed-off-by: Vincent Prince <vincent.prince.fr@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2017-11-26 02:22:36 +01:00
Marek Vasut
a8c402f45c usb: gadget: storage: Increase FSG_BUFLEN
Increase the buffer length to be just above maximum permissible value
of 128 kiB . This increases the performance of the UMS and alike by a
factor of 2 - 2.5 as the buffers are less fragmented.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
2017-11-26 02:22:36 +01:00
Dirk Behme
b3cbcd902d usb: ehci: do not invalidate a NULL buffer
Its a valid use case to call ehci_submit_async() with a NULL buffer
with length 0. E.g. from usb_set_configuration().

As invalidate_dcache_range() isn't able to judge if the address
NULL is valid or not (depending on the SoC hardware configuration it
might be valid) do the check in ehci_submit_async() as here we know
that we don't have to invalidate such a buffer.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
2017-11-26 02:22:36 +01:00
Heinrich Schuchardt
45157d2764 dm: usb: ehci: avoid possible NULL dereference
Currently we check in ehci_shutdown() if ctrl is NULL after
dereferencing it.

Before this we have already dereferenced ctrl, ctrl->hccr,
and ctrl->hcor in ehci_get_portsc_register(), ehci_submit_root(),
and hci_common_init().

A better approach is to already check ctrl, ctrl->hccr, and ctrl->hcor
during the initialization in ehci_register() and usb_lowlevel_init()
and signal an error here via the return code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-26 02:22:36 +01:00
Marek Vasut
e1cc60c0d6 usb: xhci: Add Renesas R-Car xHCI driver
Add firmware V3, firmware loader and XHCI glue for the Renesas R-Car
Gen3 SoCs XHCI controller. Thus far only the R-Car Gen3 R8A7795 ES2.0+
and R8A7796 are supported.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2017-11-26 02:22:36 +01:00
Alexey Brodkin
9829ce2ff2 usb: ehci: Fix accessors for big-endian platforms and descriptors
Commit 9000eddbae ("drivers/usb/ehci: Use platform-specific accessors")
broke USB 2.0 on big-endian platforms because for them writel/readl()
does automatic conversion of BE data to LE.

Proper implementation requires to use "raw" variant of these accessors
which read/write data without messing with endianess.

While at it replace cpu_to_be32() to be32_to_cpu() in readl() to
keep sane semantics.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Reported-by: Vladimir Boroda <boroda@yahoo.com>
2017-11-26 02:22:36 +01:00
Philipp Tomsich
8c2bb589e2 rockchip: pinctrl: rk3399: add support for I2C8
The RK3399 has a total of 9 I2C controllers.  To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.

For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-26 00:39:08 +01:00
Philipp Tomsich
a8ee98df18 rockchip: clk: rk3399: change extract_bits to bitfield_extract
The RK3399 clk driver still has a left-over use of extract_bits, which
can be replaced by using bitfield_extract from include/bitfield.h.
This rewrites the invocation to use the shared function.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-26 00:39:08 +01:00
Eugeniy Paltsev
3194c3cddf ARC: HSDK: introduce CREG GPIO driver
The HSDK can manage some pins via CREG registers block.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-11-24 19:37:56 +03:00
Heinrich Schuchardt
11f12c17d7 rockchip: spi: the symbol for Hertz is Hz
fix typo

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Kever Yang
f24e36dac3 rockchip: clock: update sysreset driver binding
Using priv for new sysreset driver binding.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Philipp Tomsich
f9ee57261f rockchip: sysreset: update Makefile to work with merged sysreset driver
After applying the merged sysreset driver, there are build failures
due to an out-of-sync Makefile. This updates drivers/sysreset/Makefile
to address these build failures.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Kever Yang
6ba54058ed rockchip: sysreset: merge into one common driver
Use a common driver for all Rockchip SOC instead of one for each SoC.
Use driver_data for reg offset.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Sean Nyekjaer
b4fbcbc5a5 mtd/spi: add support for is25lq040b
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-21 19:24:47 +05:30
Faiz Abbas
8502f9f6d7 thermal: ti-bandgap: Add support for temperature sensor
The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-21 08:03:38 -05:00
Heinrich Schuchardt
042de609ed omap3: spi: the symbol for Hertz is Hz
fix typo

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-20 20:18:40 -05:00
Tom Rini
69d3226530 Merge git://git.denx.de/u-boot-ubi 2017-11-20 11:46:08 -05:00
Tom Rini
56d5a10f3a Merge git://git.denx.de/u-boot-i2c 2017-11-20 10:51:11 -05:00
Heinrich Schuchardt
cd5f33e5fc ubi: no NULL check needed before kmem_cache_destroy
kmem_cache_destroy calls free which checks for NULL.

Problem was indicated by coccinelle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-20 10:13:42 +01:00
Beniamino Galvani
f8d9ca1833 i2c: add Amlogic Meson driver
Add a driver for the I2C controller available on Amlogic Meson SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-20 10:11:34 +01:00
Nandor Han
da5337a61c rtc: add support for s35392a
Add support for S35392A RTC. The driver supports both U-Boot driver
models.

Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Heiko Schocher <hs@denx.de>
2017-11-20 09:58:31 +01:00
Ian Ray
f31dac4e6e bootcount: add support for bootcounter on EXT filesystem
Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
2017-11-20 09:58:31 +01:00
Martyn Welch
065a1ece7a pwm: imx: Enable PWM support on i.MX53
Add missing parts for i.MX53 PWM support

Acked-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-11-20 09:58:31 +01:00
Nandor Han
2feec4eafd imx: mxc_i2c: tweak the i2c transfer method
Tweak the i2c transfer to work for devices that want to read data
without addressing a register.

Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-11-20 09:58:31 +01:00
Tom Rini
29c4992256 Merge git://git.denx.de/u-boot-dm 2017-11-19 20:35:45 -05:00
Minghuan Lian
3977dcd559 dm: pci: change bus number register setting compliant with Linux
This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-17 10:53:45 -05:00
Wilson Lee
b12907f279 serial: nulldev: Implement "pending" function to fix tstc return "true"
In U-boot, serial_tstc was use to determine is there have a character in
serial console that pending for read. If there is no "pending" function
implemented in serial driver, the serial-uclass will return "true(1)"
to indicate there have a character pending to read.

Thus, read a character from nulldev serial will result in continuous
getting -EAGAIN return which might lead system to hang.

This commit is to fix a bug in nulldev serial which implement "pending"
function in nulldev serial to always indicate there is no character in
console that pending for read.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
2017-11-17 07:44:13 -05:00
Patrice Chotard
1543bf794f clk: clk_stm32f7: fix PLL clock division factor
Fix clock division factor initialization for RCC_PLLCFGR
registers.

PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17 07:44:13 -05:00
Patrice Chotard
5829fe2d59 mmc: arm_pl180_mmci: add .getcd callback
Add .getcd callback to check is MMC card is present

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17 07:44:13 -05:00
Patrice Chotard
5f256fe71d mmc: arm_pl180_mmci: add clock support
Allow to get and enable MMC related clock

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17 07:44:13 -05:00
Patrice Chotard
9035bb7432 mmc: arm_pl180_mmci: add bus_width DT property support
Allow to get "bus-width" property from device tree

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17 07:44:13 -05:00
Patrice Chotard
3c0dbed232 mmc: arm_pl180_mmci: adapt driver to DM usage
Convert this driver to driver model.
This driver is also used by VEXPRESS platforms which doesn't
use driver model.

Tested on STM32F746 and STM32F769 platforms.

Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17 07:44:13 -05:00
Patrice Chotard
cb0060e836 mmc: arm_pl180_mmci: update arm_pl180_mmci_init() prototype
Update arm_pl180_mmci_init() prototype by adding struct mmc**
param. This is needed before converting this driver to driver model
in order to use arm_pl180_mmci_init() in driver model and in none
driver model implementation

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17 07:44:13 -05:00
Tom Rini
39e709611d omap2: nand: Make NAND_OMAP_GPMC_PREFETCH default
This option provides better performance and should really always be
enabled.  Make this be default y.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2017-11-17 07:44:13 -05:00
Neil Armstrong
8995a96d1d net: phy: Add Amlogic Meson GXL Internal PHY support
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY.

The PHY acts as a generic PHY but needs a slight configuration right
before it's configuration.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-17 07:44:13 -05:00
Neil Armstrong
16ec5ebdf8 pinctrl: meson: Add GXL Support
Add the Amlogic Meson GXL pinctrl support based on the GXBB driver and
the synchronized DTS from Linux 4.13.5

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
2017-11-17 07:43:32 -05:00
Simon Glass
8ccc2db6e8 dm: core: Correct address cast in dev_read_addr_ptr()
This currently causes a warning in sandbox and will not do the right
thing:

drivers/core/read.c: In function ‘dev_read_addr_ptr’:
drivers/core/read.c:64:44: warning: cast to pointer from integer of
	different size [-Wint-to-pointer-cast]
  return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;

Use map_sysmem() which is the correct way to convert an address to a
pointer.

Fixes: c131c8bca8 (dm: core: add dev_read_addr_ptr())
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-16 18:45:05 -07:00
Tom Rini
ebca2083d3 Merge git://www.denx.de/git/u-boot-marvell 2017-11-16 09:32:04 -05:00
Jon Nettleton
d3d036af8c mvebu: usb: xhci: a38x support
This makes the initial changes need to support the
a38x series of SOCs.  It adds the device-tree identifier
as well as changing the board_support function to take
the IO address designated by device-tree.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: use fdt_addr_t; update 37xx and 8K implementations]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-16 11:45:20 +01:00
VlaoMao
49b23e035d pci: mvebu: Increase size of PCIe default mapping
Increase size PCI memory mapping from 32MiB to 128MiB.

Signed-off-by: VlaoMao <vlaomao@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-16 11:43:15 +01:00
Prabhakar Kushwaha
f53e12d80a driver: net: fsl-mc: Use base 16 in simple_strtoul
Value provided in MC_MEM_SIZE_ENV_VAR is in hex. Use 16 as base
in simple_strtoul.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-15 10:53:15 -08:00
Kurt Kanzenbach
99145c488f mtd: nand: fsl-ifc: fix support of multiple NAND devices
Currently the chipselect used to identify the corresponding NAND chip
is stored at the controller and only set during fsl_ifc_chip_init().
This way, only the last NAND chip is working, as the previous value
of cs_nand gets overwritten.

In order to solve this issue the chipselect is computed on demand by
evaluating the bank variable. Thus, the correct chipselect for each
NAND chip operation is used.

Tested on hardware with two NAND chips connected to the IFC
controller.

Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Acked-by: Scott Wood <oss@buserror.net>
[YS: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-14 08:33:20 -08:00
Ashish Kumar
5e9445da28 drivers: net: ldpaa_eth: Correct error handler for qbman_swp_acquire()
The zero value returned from qbman_swp_acquire() is an error
condition meaning no free buffer for allocation.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kushwaha Prabhakar <prabhakar@freescale.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-14 08:33:20 -08:00
Chen-Yu Tsai
13ae2a40e7 net: sun8i_emac: Fix build for non-H3/H5 SoCs
Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.

Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-10 19:10:33 +05:30
Tom Rini
1c4043e532 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-11-09 08:11:40 -05:00
Artturi Alm
6270a3f035 sunxi: restore PHYLIB for CONFIG_SUN4I_EMAC users
due misnaming of CONFIG_SUN4I_EMAC in include/configs/sunxi-common.h,
likely missed in:
	commit 3146f0c017 ("Move PHYLIB to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:30 +05:30
Artturi Alm
e286fada9d sunxi: fix CONFIG_SUNXI_EMAC references
fixes CONFIG_SUNXI_EMAC references from drivers/net/Makefile and
include/configs/sunxi-common.h likely forgotten in:
	commit abc3e4df59 ("sunxi: Convert SUNXI_EMAC to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:09 +05:30
Benoît Thébaudeau
bcfb365375 mmc: fsl_esdhc: Fix PIO timeout
The following error has been observed on i.MX25 with a high-speed SDSC
card:
    Data Write Failed in PIO Mode.

It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
because this bit takes 15 ms to be set after writing the first block to
DATPORT with this card. Without this timeout, all the blocks are
properly written.

This timeout was implemented by decrementing a variable, so it was
depending on the CPU frequency. Fix this issue by setting this timeout
to a long enough absolute duration (500 ms).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-07 10:26:27 +01:00
Patrice Chotard
05cd11948e tpm: st33zp24: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights header

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
3bc599c956 stm32: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Patrice Chotard
fb48bc448c sti: fix STMicroelectronics copyright
Uniformize all STMicroelectronics copyrights headers for STi
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
Icenowy Zheng
460b15adc9 video: sunxi: de2: fix SimpleFB node creation when HDMI not initialized
When HDMI is not initialized (e.g. no monitor is plugged), the current
SimpleFB code will still create a broken SimpleFB node.

Detect whether HDMI is initialized when creating SimpleFB node.

Fixes: be5b96f0e4 ("sunxi: setup simplefb for Allwinner DE2")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-11-06 13:43:28 +05:30
Michal Simek
cba64a2a73 scsi: ceva: Start port in probe
The patch:
"dm: ahci: Unwind the confusing init code"
(sha1: 7cf1afce7f)
introduce bug for ceva sata because port didn't start.
On the other hand the dwc_ahci.c was fixed correctly.
Do the same change for ceva too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
2017-11-03 09:31:27 +01:00
Kever Yang
9f636a249c rockchip: rk3399: init CPU clock when rkclk_init()
Init the CPU and its buses to speed up the boot time.
Move rkclk_init() to a place after rk3399_configure_cpu has defined
at the same time, or else there will be a warning.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Fabio Estevam
41b93679fd net: fec_mxc: Change "error frame" message to debug level
As reported by Jonathan Gray:

"After the recent changes to add SimpleNetworkProtocol to efi_loader
when booting off mmc via an efi payload that doesn't use
SimpleNetworkProtocol U-Boot's fec_mxc driver will now display
various "error frame" messages.
....
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Scanning disks on sata...
Found 6 disks
reading efi/boot/bootarm.efi
67372 bytes read in 32 ms (2 MiB/s)
## Starting EFI application at 12000000 ...
>> OpenBSD/armv7 BOOTARM 1.0
error frame: 0x8f57ec40 0x00003d74
error frame: 0x8f57ec40 0x00007079
error frame: 0x8f57ec40 0x00006964
error frame: 0x8f57ec40 0x00006f6f
error frame: 0x8f57ec40 0x0000726f
error frame: 0x8f57ec40 0x00002074
error frame: 0x8f57ec40 0x00006f6f"

Heinrich Schuchardt explains:

"A receive FIFO overrun can be expected if network packages are not
processed.
With the network patches we check if a package is available quite often."

Move the "error frame" messages to debug level so that a clean output
log can be seen.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-30 18:57:42 +01:00
Tom Rini
2d5e6b4aac Merge git://git.denx.de/u-boot-video 2017-10-29 10:11:08 -04:00
Dongjin Kim
9b73bcc6c3 exynos: video: fix typo in DisplayPort driver
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
CC: Simon Glass <sjg@chromium.org>
CC: Minkyu Kang <mk7.kang@samsung.com>
2017-10-29 14:33:55 +01:00
Niko Mauno
963be68937 video/da8xx-fb: Cache-align memory allocations
Resort to malloc_cache_aligned() rather than malloc() which also removes
'CACHE: Misaligned operation at range' warnings.

Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2017-10-29 14:33:24 +01:00
Tom Rini
bb3d9ed3a9 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-27 21:59:10 -04:00
Ran Wang
420b0eba3c usb: host: Move CONFIG_XHCI_FSL to Kconfig
use Kconfig to select xhci accordingly.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:44:06 -07:00
Ashish Kumar
2af1b08a1a armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit 05b29aa0cb
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:41:12 -07:00
Prabhakar Kushwaha
a572fb6bdd driver: fsl-mc: use calloc instead malloc
Memory allocated via malloc is not guaranteed to be zeroized.
So explicitly use calloc instead of malloc.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:38:29 -07:00
Masahiro Yamada
af6715bfb4 i2c: fti2c010: remove unused/unmaintained driver
CONFIG_SYS_I2C_FTI2C010 is not enabled by anyone.

Commit 2852709676 ("dm: i2c: Add a note to I2C drivers which need
conversion") prompted to convert this driver to DM before June 2017,
but not converted yet.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-10-27 08:52:22 -04:00
Masahiro Yamada
1d14cbdcd8 i2c: adi_i2c: remove left-over Blackfin I2C driver
This driver was used by Blackfin boards, but Blackfin support is
gone.  There is no user of this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-10-27 08:52:22 -04:00
Tom Rini
ae6ac0a06e Merge git://git.denx.de/u-boot-x86 2017-10-27 08:50:16 -04:00
Vasily Khoruzhick
1d7eef3f3f sunxi: video: add LCD support to DE2 driver
Extend DE2 driver with LCD support. Tested on Pinebook which is based
on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: rebased v5 on u-boot-video/master]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-27 09:44:48 +02:00
Vasily Khoruzhick
79f285ddeb sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-27 09:39:19 +02:00
Bin Meng
ab20107468 spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Vasily Khoruzhick
491041c749 video: add anx6345 DM driver
This is a eDP bridge similar to ANX9804, it allows to connect eDP panels
to the chips that can output only parallel signal

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: fixed most checkpatch errors/warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-26 15:43:11 +02:00
Vasily Khoruzhick
24bf59d024 video: anx9804: split out registers definitions into a separate header
This header will be used in anx6345 driver

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: moved header to drivers/video]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-26 14:31:42 +02:00
Vasily Khoruzhick
fdb5525572 dm: video: bridge: add operation to read EDID
Add an operation to read EDID, since bridge may have ability to read
EDID from the panel that is connected to it, for example LCD<->eDP bridge.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-26 14:17:01 +02:00
Icenowy Zheng
be5b96f0e4 sunxi: setup simplefb for Allwinner DE2
As the support of EFI boot on Allwinner H3 is broken, we still need to
use simplefb to pass the framebuffer to Linux.

Add code to setup simplefb for Allwinner DE2 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:57:14 +02:00
Icenowy Zheng
f6bdddc92b video: add an option for video simplefb via DT
Add an option to indicate that the video driver should setup a SimpleFB
node that passes the video framebuffer initialized by U-Boot to the
operating system kernel.

Currently only the Allwinner DE driver uses this option, and the
definition of this option in the sunxi-common.h config header is
converted to an imply of this option from CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:53:39 +02:00
Icenowy Zheng
e5f92467d7 video: sunxi: extract simplefb match code to a new file
As the DE2 simplefb setup code can also benefit from the simplefb match
code, extract it to a new source file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:51:45 +02:00
Andre Przywara
a722359de4 SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXI
The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI
symbol. But despite its generic name, the actual only use case for this
is to provide SPI flash support to the SPL, which requires
CONFIG_SPL_SPI_FLASH_SUPPORT to be defined.
Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This
avoids doing this explicitly in the defconfig, and fixes SPI booting on
the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with
SPI flash).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:05 +02:00
Bin Meng
6087be2ba6 rtc: mc146818: Correct alarm message for day alarm
RTC_CONFIG_D register contains the day within the month to generate
an alarm, not the month. This corrects the printf to indicate it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-23 17:25:40 -04:00
Masahiro Yamada
3d569a807e simple-bus: remove DECLARE_GLOBAL_DATA_PTR
No global pointer is used in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-23 17:25:40 -04:00
Masahiro Yamada
166cae20dd mtd: replace MTDDEBUG() with pr_debug()
In old days, the MTD subsystem in Linux had debug facility like
DEBUG(MTD_DEBUG_LEVEL1, ...).

They were all replaced with pr_debug() until Linux 3.2.  See Linux
commit 289c05222172 ("mtd: replace DEBUG() with pr_debug()").

U-Boot still uses similar macros.  Covert all of them for easier sync.

Done with the help of Coccinelle.

The semantic patch I used is as follows:

// <smpl>
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2)
+pr_debug(e2)
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2,
+pr_debug(e2,
 ...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 14:07:26 -04:00
Adam Ford
8daec2d9d3 net: Add SMC911X driver to Kconfig, convert
We add the various SMC91XX symbols to drivers/net/Kconfig and then this
converts the following to Kconfig:
   CONFIG_SMC911X
   CONFIG_SMC911X_BASE
   CONFIG_SMC911X_16_BIT
   CONFIG_SMC911X_32_BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Apply to the rest of the tree, re-squash old and new patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 21:40:26 -04:00
Adam Ford
0a9ef45158 Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_MXC
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE
   CONFIG_SYS_NAND_BUSWIDTH_16BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
        add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 16:44:07 -04:00
Tom Rini
6b0fea3342 Merge git://git.denx.de/u-boot-i2c 2017-10-18 09:32:35 -04:00
Tom Rini
002e91087c Merge git://git.denx.de/u-boot-spi 2017-10-18 09:32:21 -04:00
Patrice Chotard
d10bd6cfd8 i2c: stm32f7_i2c: fix usage of useless local variable
Remove useless local variable "s" and use directly
function's parameter "output"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-17 11:28:41 +02:00
Christophe Kerello
81c4843763 i2c: stm32f7_i2c: fix data abort
As "v" is a local variable in stm32_i2c_choose_solution()
"v" has to be copied into "s" to avoid data abort in
stm32_i2c_compute_timing().

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-17 11:28:27 +02:00
Masahiro Yamada
c4e5990ad2 i2c: remove DECLARE_GLOBAL_DATA_PTR from i2c-uclass
No global pointer is used in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-10-17 11:27:42 +02:00
Heinrich Schuchardt
c409336dac usbtty: fix typos
Fix typos in USB tty driver.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
c68c03f52b Drop CONFIG_HAS_DATAFLASH
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-16 09:42:51 -04:00
Tuomas Tynkkynen
95688de311 spi: Drop CONFIG_ATMEL_DATAFLASH_SPI
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-10-16 09:42:51 -04:00
Christophe Kerello
6c36e97be6 mmc: stm32_sdmmc2: increase polling status register delay
MMC commands like MMC_CMD_ALL_SEND_CID or MMC_CMD_SEND_CSD can reach
500 us. This patch increases the polling status register delay to avoid
a timeout on a command.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-16 09:42:51 -04:00
Patrice Chotard
6c1bf6c442 dm: clk: fix PWR_CR3 register's bit 2 name
Fix bit 2 name of PWR_CR3 register to match with the
last STM32H7 reference manual available here :

http://www.st.com/content/st_com/en/support/resources/
resource-selector.html?querycriteria=productId=SS1951$$
resourceCategory=technical_literature$$resourceType=reference_manual

Update also comment about voltage scaling 1 values

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-16 09:42:51 -04:00
Patrice Chotard
1b4ce69dc2 dm: clk: remove CLK() macro for clk_stm32h7
CLK() macro is a residue of a previously reworked patch,
remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-10-16 09:42:51 -04:00
Masahiro Yamada
7d9927c895 clk: uniphier: add NAND controller clock
This allows the NAND driver to enable clock and get its clock rate.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
a89b9bc095 mtd: nand: denali_dt: add clock support
Enable clock in the probe hook.  The clock rate will be necessary
when setup_data_interface hook is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00