The SPR IVPR register is only present (as far as I know) for
processors with a PPC440 core.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Acked-by: Stefan Roese <sr@denx.de>
We use upper case letters for the AMCC processor defines (like
CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and
not CONFIG_440SPe. This patch fixes the last misspelled config options.
Signed-off-by: Stefan Roese <sr@denx.de>
Added OCM test to POST layer. This version runs before all other tests
but doesn't yet interrupt post sequence on failure.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Introduce the new logical option CONFIG_HAS_POST which is set when the
platform has CONFIG_POST set. Use CONFIG_HAS_POST in the post/ Makefiles
to determine should the POST libs be compiled for the selected target
platform, or not.
To avoid breaking u-boot linking process, the empty post/libpost.a file is
created for platforms which do not have POSTs.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.
This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.
Signed-off-by: Larry Johnson <lrj@acm.org>
post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch allows the ECC POST to be used for different boards with the
PPC440 Denali SDRAM controller. Modifications include skipping the test
if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization
to prevent timing errors.
Signed-off-by: Larry Johnson <lrj@acm.org>
The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.
Signed-off-by: Stefan Roese <sr@denx.de>
When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
is not done using an internal loopback connection, but by assuming
that an external loopback connector is plugged into the board.
Signed-off-by: Stefan Roese <sr@denx.de>
The patch adds support for UART POST on ppc44x-based boards with no
external serial clocks installed.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Acked-by: Stefan Roese <sr@denx.de>
- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
