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POST: Disable cache while SPR POST

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Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Anatolij Gustschin 2008-02-25 20:04:20 +01:00 • committed by Wolfgang Denk
parent c313b2c6c5
commit 60ec654c5e
1 changed files with 14 additions and 0 deletions
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14
post/cpu/ppc4xx/spr.c
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@ -43,6 +43,12 @@
#include <asm/processor.h>
#ifdef CONFIG_4xx_DCACHE
#include <asm/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
static struct {
int number;
char * name;
@ -164,6 +170,10 @@ int spr_post_test (int flags)
};
unsigned long (*get_spr) (void) = (void *) code;
#ifdef CONFIG_4xx_DCACHE
/* disable cache */
change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
#endif
for (i = 0; i < spr_test_list_size; i++) {
int num = spr_test_list[i].number;
@ -180,6 +190,10 @@ int spr_post_test (int flags)
ret = -1;
}
}
#ifdef CONFIG_4xx_DCACHE
/* enable cache */
change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
#endif
return ret;
}