The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
When setting fixed-link property to DTS, the values should be converted
with using cpu_to_fdt32 so that to have correct value on little endian
Soc.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.
dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.
Memory test start/end were changed to DDR location to let memtest still
compiled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is incorrect setting for USB which didn't work with origin
ps7_init_gpl.X files.
Use default setting for Digilent Zybo projects with HDMI in PL.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.
Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1
Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured. The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2. There was also a tIH-CA violation and this was
resolved by writing the default value in rather than what the script
here uses.
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured. The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2.
Cc: Jason Liu <jason.hui.liu@nxp.com>
Cc: Ye Li <ye.li@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set
previously inside setup_display().
We can safely remove enable_lvds() then.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC
U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.
This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Enable the TI DP83867 Giga bit phy on the
dra7 rev c board. The rx and tx internal
delays are need for this board so the usage
of RGMII_ID is required.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This moves the sniper board from the lge to lg, in order to match the devicetree
vendor prefix already defined in the kernel.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
With the previous implementation, rebooting without registering a recognized
reboot mode would end up with U-Boot checking for a valid power-on reason, which
might result in the device turning off (e.g. with no USB cable attached and no
buttons pressed).
Since this approach is not viable (breaks reboot in most cases), the validity of
the reboot reason is checked (in turn, by checking that a warm reset happened,
as there is no magic) to detect a reboot and the 'o' char is recognized to
indicate that power-off is required. Still, that might be overridden by the
detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
With the previous implementation, rebooting without registering a recognized
reboot mode (despite registering the magic) would end up with U-Boot checking
for a valid power-on reason, which might result in the device turning off (e.g.
with no USB cable attached and no buttons pressed).
This was designed to catch reboots that are actually intended to be power-off,
something that old Android kernels do, instead of properly turning the device
off using the TWL4030.
However, since this approach is not viable (breaks reboot in most cases), the
validity of the reboot mode magic is checked to detect a reboot and the 'o' char
is recognized to indicate that power-off is required. Still, that might be
overridden by the detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot for the Raspberry Pi 3.
>From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a
change in usage of the SoC UARTs. On all previous Pis, the PL011 was the
only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a
UART to connect to the SoC. By default, the PL011 is used for this purpose
since it has larger FIFOs than the other "mini" UART. However, this can
be configured via the VideoCore firmware's config.txt file. This patch
hard-codes use of the mini UART in the RPi 3 port. If your system uses the
PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot
port instead. A future change might determine which UART to use at
run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed
together.
The mini UART has some limitations. One externally visible issue in the
BCM2837 integration is that the UART divides the SoC's "core clock" to
generate the baud rate. The core clock is typically variable, and under
control of the VideoCore firmware for thermal management reasons. If the
VC FW does modify the core clock rate, UART communication will be
corrupted since the baud rate will vary from the expected value. This was
not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To
work around this, the VideoCore firmware can be told not to modify the SoC
core clock. However, the only way this can happen and be thermally safe is
to limit the core clock to a low/minimum frequency. This leaves
performance on the table for use-cases that don't care about a UART
console. Consequently, use of the mini UART console must be explicitly
requested by entering the following line into config.txt:
enable_uart=1
A recent version of the VC firmware is required to ensure that the mini
UART is fully and correctly initialized by the VC FW; at least
firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on
core clock See: https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This allows U-Boot to known the name of the board.
The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3
in 32-bit mode /if/ you have configured the firmware to use the PL011 UART
as the console UART (the default is the mini UART). This requires two
things:
a) config.txt should contain dtoverlay=pi3-miniuart-bt
b) You should run the following to tell the VC FW to process DT when
booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card
as the kernel image:
path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img
This works as of firmware.git commit 046effa13ebc "firmware: arm_loader:
emmc clock depends on core clock See:
https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
To simplify support for new SoCs, just use a constant filename
for the unknown case. In practice this case shouldn't be hit anyway, so
the filename isn't relevant, and certainly doesn't need to differentiate
between SoCs. If a user has an as-yet-unknown board, they can override
this value in the environment anyway.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
On the A64 we usually boot with ATF running in EL3. ATF as it is available
today resides in the first 16MB of RAM. So we should make sure we reserve
that space in our memory maps.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of
running AArch64 code and thus is the first of its kind for the sunxi target.
This patch adds a defconfig and device tree chunks for it.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: Change patch description]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.
Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY
on the A83T/H8.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.
Add esbh_halt() after the reset to make sure execution stops.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The MAC addresses for the PRU Ethernet ports will be available in the
board EEPROM as an address range. Populate those MAC addresses (if valid)
into the u-boot environment so that they can be passed on to the
device tree during fdt_fixup_ethernet().
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently, CONFIG_BCM2835 is defined for all BCM283x builds and _BCM2836
is defined when building for that SoC. That means there isn't a single
define that means "exactly BCM2835". This will complicate future patches
where BCM2835-vs-anything-else needs to be determined simply.
Modify the code to define one or the other of CONFIG_BCM2835/BCM2836 so
future patches are simpler.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add the pinmux data for rev C evm. This is different from previous
revisions of the platform thanks to the deltas introduced both from
silicon side and from SoC side.
Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for
SR2.0 silicon.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
DDR configuration has changes from SR1.1 based Rev-A/B version of evm
to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher
density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
Update the DDR configuration based on data from EMIF configuration
tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the
configuration.
Tested-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:
- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB
This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
VESA 1024x768 results in much more accurate timings.
Based on the patch from Soeren Moch for the tbs2910 board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
The fsl-mc node has been moved under /soc, so update
the path references accordingly. Backwards compatibility
is retained for /fsl-mc.
Delete backwards compatibility for the completely obsolete
/fsl,dprc@0.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It has been superseded in kwbimage.cfg in favor of an SPL in commit
9e30b31d20 (arm: mvebu: db-88f6820: Add
SPL support with DDR init code). Found via code review.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs
are connected to the SPI busses. This patch uses board specific write
code to program the bitstream via SPI direct write mode.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
Always select OF_BOARD_SETUP on sunxi, rather then having it in almost
all our defconfigs. This also fixes it missing from some recently
added defconfigs.
This commit also modifies our ft_board_setup() to not cause warnings
when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always
build it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There are 2 reasons for doing this:
1) The main reason for doing this is to move it outside of
board/sunxi/ahci.c, so that it can be used on boards which use
a usb<->sata chip too;
2) While doing this I realized that doing it from board_init also meant
doing it much earlier. Some printf get_timer(0) calls show that the
time between board_init() and scsi_init() is more then 600 ms,
so we can drop the mdelay(500)
While at it also drop the printf("SUNXI SCSI INIT\n") AHCI init is
noisy enough by itself.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot,
4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI,
a TRRS headphone jack for stereo out and composite out, a microphone,
an IR receiver, a CSI connector, 2 LEDs, a 3 pin UART header
and a 40-pin GPIO header.
The added dts file is identical to the one submitted to the upstream
kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD,
1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The yones toptech bs1078-v2 is a 10.1" tablet without any clear markings on
the outside, but 'YONESTOPTECH-BS1078' written on the PCB silkscreen.
It features a 16:9 1024:600 LCD, A31s SoC, 1GB RAM, 8G NAND, silead gsl3675
touchscreen and a RTL8723AS wifi chip:
https://linux-sunxi.org/Yones_Toptech_BS1078_V2
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Sinlinx A31s SDK is a A31s based module/baseboard development kit.
The core module has the SoC, PMIC, DRAM, eMMC and supporting components.
There are also pads for UART0, JTAG and I2S.
The baseboard has 100 Mbps Ethernet, 5x USB 2.0 host ports via a USB 2.0
hub chip, MMC, HDMI, SPDIF, CIR, audio jacks, 2 tablet-like volume
buttons, RS232 style UART and USB OTG (though VBUS is not connected).
Various headers are available for other addon modules, such as SDIO
WiFi, LCD display, camera sensor, UARTs, I2C, SPI and GPIOs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add defconfig for the multi board device based on the
Allwinner A20 SoC. It contains the A20 Itead Core module and a
base board for the external interfaces.
The core module comes with 4GB NAND and 1GB DDR RAM.
The base board to which the core board is connected provides
3 USB 2.0 Host ports, 1 USB 2.0 OTG, 1 uSD slot, 10/100 Ethernet
port, HDMI, IR receiver, SPDIF and a 32-pin GPIO header. This
header expands the features of core board by exposing the VGA pins,
audio In/Out pins, SATA, SPI, I2C, UARTS, USB-OTG and power..
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Cubietruck Plus is a A83T/H8 based development board. The board has
standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
WiFi, headphone out / mic in, and various GPIO headers.
The board also has an EEPROM on i2c0 which holds the MAC address.
DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20
is connected to the reset control of the PHY. EMAC is not actually
supported yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Polaroid MID2809PXE4 is a 9" tablet which is clearly marked
Polaroid MID2809PXE4 on the back. It features a 9" 16:9 800x480 LCD,
A23 Soc, 1GB RAM, 8GB NAND, gsl3670 touchscreen and esp8089 wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD,
A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at
i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and
rtl8188etv wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly
e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC,
1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41,
stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip.
The added dts is identical to the dts submitted to the upstream kernel,
note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the
upstream kernel as the added dts depends on these.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt. Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
After power cycle of a K2G EVM dhcp fails due to a auto-negotiation
timeout. This commit increases the timeout to fix the issue.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Return i2c mux to the default channel after accessing retimer.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.
Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe
Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).
The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded. In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.
Signed-off-by: Tom Rini <trini@konsulko.com>
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case change things so that we
only build the right objects for SPL or non-SPL
Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.
This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.
We could maybe in the future map U-boot environment variables to EFI variables
here.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The hikey runs with dcache disabled today. There really should be no reason
not to use caches on AArch64, so let's add MMU definitions and enable the
dcache.
Signed-off-by: Alexander Graf <agraf@suse.de>
There's no good excuse for running with caches disabled on AArch64,
so let's just move the vexpress64 target to enable the MMU and run
with caches on.
Signed-off-by: Alexander Graf <agraf@suse.de>
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reboot mode garbage is found on cold reset and might be seen as valid on the
next warm reset, thus it has to be cleared on cold reset.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Some power on reasons are not desirable (e.g. too short press on the power
button), battery plug. Thus, power off the device when one of those occurs.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the omap4 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition or fastboot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the MUSB USB dual-role controller in peripheral mode,
with configuration options for the fastboot USB gadget.
At this point, flashing the internal eMMC is support.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.
It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Boards using the TWL6030 regulator may not all use the LDOs the same way.
Some might also not use MMC1 at all, so VMMC would't have to be enabled.
This delegates TWL6030 MMC power initializations to board-specific functions,
that may still call twl6030_power_mmc_init for the default behavior.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reboot mode garbage is found on cold reset and might be seen as valid on the
next warm reset, thus it has to be cleared on cold reset.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
There is no need to set the reboot mode to a particular value prior to reboot,
since valid values will have been caught and cleared earlier.
In addition, this breaks the reboot-bootloader fastboot call, by overriding the
required value for fastboot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
All the mux configurations needs to be done as part of the IODelay
sequence to avoid glitch. Adding all the mux configuration, MANUAL/VIRTUAL
mode configuration as needed for DRA72-evm.
Also update the mux for SD card detect on DRA74-evm.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updating the memory banks properly so that DT is populated accordingly.
And updating this only after DDR is properly detected by eeprom, so that
git bisect is still maintained.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory
chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the
same.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA7 EVM revH and later EVMs have EEPROM populated that can contain board
description information such as name, revision, DDR definition, etc. Adding
support for this EEPROM format.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
