Commit graph

1342 commits

Author SHA1 Message Date
Fabio Estevam
0a11d6f29c mx6: Remove duplication of iomuxc structure
There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
registers.

The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.

So remove iomuxc_base_regs structure and use iomuxc instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
fa8cf3176c mx6sxsabresd: Add PFUZE100 PMIC support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
Shaohui Xie
e55782eccc powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
9d0456822c powerpc/mpc85xx: Check return value of find_tlb_idx
find_tlb_idx() is called in board_early_init_r() on multiple boards.
The return value is not checked before being used to disable a TLB.
In normal case the return value wouldn't be -1. In case of a mis-
configuration during porting to a new board, checking the return value
may be helpful to reveal some user errors.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
vijay rai
6666017f44 powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Lijun Pan
d0bc51407c powerpc/mpc85xx: Remove P1023 RDS support
Since P1023RDS is no longer supported/manufactured by Freescale,
we clean up P1023RDS related code.
Since P1023RDB is still supported by Freescale,
we keep P1023RDB releated code.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Masahiro Yamada
61f06b143e m68k: fix an undefined behavior warning of M5253DEMO board
The latest GCC is so clever that it reports more warnings
than old ones did:

 ------------------------------>8------------------------------

  board/freescale/m5253demo/flash.c: In function 'flash_get_offsets':
  board/freescale/m5253demo/flash.c:65:23: warning: iteration 2047u
  invokes undefined behavior [-Waggressive-loop-optimizations]
      info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
                         ^
  board/freescale/m5253demo/flash.c:64:3: note: containing loop
     for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
     ^

 ------------------------------8<------------------------------

The cause of the warning is like this:

The for statement iterates 2048 times in flash_get_offsets() func.
(Notice CONFIG_SYS_SST_SECT is defined as 2048)

The last iteration does
  info->start[2048] = info->start[2047] + CONFIG_SYS_SST_SECTSZ;
causing an undefined behavior.

(Please note the array size of info->start is 2048.
CONFIG_SYS_MAX_FLASH_SECT is defined as 2048 for this board.)

This commit fixes that so as not to overrun the info->start array.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-07-22 09:46:48 -04:00
Stefano Babic
dab5e3469d Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
	boards.cfg
2014-07-16 08:51:30 +02:00
Fabio Estevam
14a1613140 mx6sx: Add initial support for mx6sxsabresd board
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
York Sun
f749db3a75 ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-07-04 19:48:41 +02:00
Albert ARIBAUD
d6694aff56 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-06-30 23:00:34 +02:00
Albert ARIBAUD
ed1d98d801 Merge branch 'u-boot/master' into 'u-boot-arm/master' 2014-06-25 10:39:58 +02:00
Masahiro Yamada
e6af385989 freescale: m5253demo: fix unused-but-set-variable warnings
Fix the following warning messages:

In function 'flash_erase': 180:21:
warning: variable 'last' set but not used [-Wunused-but-set-variable]
In function 'write_buff':  322:10:
warning: variable 'port_width' set but not used [-Wunused-but-set-variable]

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2014-06-19 11:18:43 -04:00
Fabio Estevam
a81c90f4c8 mx28evk: Add documentation on how to boot from SPI NOR
Explain the necessary steps in order to boot from SPI NOR.

Based on a earlier submission from Mårten Wikman.

Signed-off-by: Mårten Wikman <marten.wikman@novia.fi>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-06-17 16:39:10 +02:00
Simon Glass
6469a34678 mx31ads: Fix the U-Boot binary output
Correct the binary output so that image_binary_size is really at the
end of the image.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-11 16:25:39 -04:00
Chao Fu
cb6d04d606 arm: vf610: Add QSPI support for VF610TWR
Add QSPI support for VF610TWR, such as clock and iomux.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
2014-06-09 09:18:15 +02:00
Tom Rini
3e1fa221f9 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-06-05 17:38:30 -04:00
Masahiro Yamada
26bf6d77a6 nand_spl: remove P1023RDS_NAND support
Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-06-05 17:01:58 -04:00
poonam aggrwal
fa6e742825 powerpc/B4420: Fixed incomplete handling for 0x9d serdes2
Crossbars and IDT were not getting configured for Serdes2 protocol
0x9d for B4420.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Chunhe Lan
e6c334a7a4 powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:13 -07:00
Shengzhou Liu
40483e1e1d board/t2080qds: some update for ddr
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.

Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:06 -07:00
Shaohui Xie
94752f60eb powerpc/t4qds: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:55:59 -07:00
Shengzhou Liu
9752eb6426 board/t208x: update t2080qds/t2080rdb for errata A-007186
As errata A-007186, we need to use the alternate serdes
protocol instead of those impacted protocols.

- add support for serdes protocols: 0x1b, 0x50, 0x5e,
  0x64, 0x6a, 0xd2, 0x67, 0x70.
- update t2080_rcw.cfg to adapt to new rcw_66_15 for
  t2080qds and t2080rdb.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:55:39 -07:00
Masahiro Yamada
facb6725c3 powerpc: mpc8260ads: remove orphan board
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>
2014-05-30 14:03:24 -04:00
Fabio Estevam
66ca09fc41 mx6sabred: Add PFUZE100 PMIC support
mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus.

Add support for it

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-05-28 17:35:39 +02:00
Fabio Estevam
186feb0b4d mx6sabreauto: Add the mx6dual-lite variant
Tested by booting a mainline kernel via TFTP.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-05-28 17:23:24 +02:00
Stefan Agner
56d83d1c04 arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-05-25 15:46:12 +02:00
Albert ARIBAUD
05d134b084 Merge remote-tracking branch 'u-boot/master'
Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
2014-05-20 10:05:42 +02:00
Prabhakar Kushwaha
bc2d40ca10 board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL
In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Tang Yuantian
0f1fa36fff powerpc/t104xrdb: Toggle deep sleep management signals after resume
T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Ebony Zhu
477c894ff4 board/freescale: Move CRC32 offset in NXID v1 data format
According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.

Signed-off-by: Ebony Zhu <b45385@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Albert ARIBAUD
6a2f30a03a Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-05-16 17:56:50 +02:00
Albert ARIBAUD
41623c91b0 arm: move exception handling out of start.S files
Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15 16:24:53 +02:00
Stefano Babic
e7f9350525 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-15 10:27:32 +02:00
York Sun
bffac7aef5 powerpc/freescale: Change the return value of mac_read_from_eeprom()
The return value has not been checked by its caller, until recent change
of using generic board architecture. The error of this function is not
critical enough to hang the system. Printing the warning message is enough
to catch user's attention. U-boot should continue to boot to give user
a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging
in the board_init_r().

Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-13 08:31:22 -07:00
Alexander Graf
b539534d12 PPC 85xx QEMU: Always assume 1 core
We only need u-boot to bother about a single core in the QEMU machine.
Everything that would require additional knowledge of more cores gets
handled by QEMU and passed straight into the payload we execute.

Because of this setup, it would be counterproductive to enable SMP support
in u-boot. We would have to rip CPUs out of already existing spin tables
and respin them from u-boot. It would be a pretty big mess.

So only assume we have a single core. This fixes errors about CONFIG_MP
being disabled.

Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-13 08:26:55 -07:00
Chunhe Lan
0b2e13d9cc powerpc/85xx: Add T4240RDB board support
T4240RDB board Specification
----------------------------
Memory subsystem:
   6GB DDR3
   128MB NOR flash
   2GB NAND flash

Ethernet:
   Eight 1G SGMII ports
   Four 10Gbps SFP+ ports

PCIe:
   Two PCIe slots

USB:
   Two USB2.0 Type A ports

SDHC:
   One SD-card port

SATA:
   One SATA port

UART:
   Dual RJ45 ports

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
2014-05-13 08:24:32 -07:00
Shaveta Leekha
652e29b4a0 board/b4qds: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

B4860QDS has a PowerOne ZM7300 programmable digital Power
Manager which is programmed as per the value read from
the fuses.

Reference for this code is taken from t4qds VID implementation.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-05-13 08:20:31 -07:00
Shaveta Leekha
4150f24290 board/freescale/common: ZM7300 driver
Adds Support for PowerOne ZM7300 voltage regulator.
This device is available on some Freescale Boards like B4860QDS
and has to be programmed to adjust the voltage on the board.

The device is accessible via I2C interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-05-13 08:20:31 -07:00
Fabio Estevam
694c3bc107 mx6slevk: Add SPI NOR flash support
mx6slevk has a m25p32 SPI NOR flash connected to ESCSPI port.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-04-28 14:00:16 +02:00
Shaohui Xie
b6036993eb powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Shaohui Xie
cb753850e8 powerpc/t4240: updated RCW and PBI for rev2.0
Updated the RCW for rev2.0 which uses new frequency settings as below:

Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz,
CCB:733.333 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN:  366.667 MHz
PME:   533.333 MHz

Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Shengzhou Liu
ef531c7357 board/t2080rdb: some update for t2080rdb
- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
  ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
  previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Shengzhou Liu
4d66668300 board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Shengzhou Liu
b19e288f47 board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Shaohui Xie
b0615f0bd2 powerpc/t1040rdb: added a break in switch case
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Prabhakar Kushwaha
18c0144542 board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
      - Add spl.c which defines board_init_f, board_init_r
      - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
c5dfe6ec58 board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
  - Add spl.c which defines board_init_f, board_init_r
  - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Zhao Qiang
6259e29134 T1040QDS/U-QE: Add u-qe support to t1040qds
Add u-qe support for t1040qds

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
5303a3dea9 mpc85xx: Add deep sleep support on T104xRDB
Add deep sleep support on T104xRDB platforms.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
48f6a9a2bf mpc85xx: Add deep sleep support on T1040QDS
Add deep sleep support on T1040QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Prabhakar Kushwaha
55153d6c30 board/t104xrdb: Add support of CPLD
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
c60dee03c0 mpc85xx/T1040QDS_D4: Add DDR4 support
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Prabhakar Kushwaha
6b50f62cc4 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Alexander Graf
fa08d39517 PPC 85xx: Add qemu-ppce500 machine
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Eric Benard
d84187ac75 mx6sabresd: use common detect_hdmi
Signed-off-by: Eric Bénard <eric@eukrea.com>
2014-04-15 12:23:57 +02:00
Eric Benard
053b795e30 mx6sabresd: use common board_video_skip
Signed-off-by: Eric Bénard <eric@eukrea.com>
2014-04-15 12:23:56 +02:00
Marcel Ziswiler
0883b0b58e arm: vf610: fix double iomux configuration for vf610twr board
Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-04-07 20:15:52 +02:00
Stefano Babic
1cad23c5f4 Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-04 11:35:30 +02:00
Marek Vasut
31c832f93c arm: mx5: Avoid hardcoding memory sizes on MX53QSB
The DRAM size can be easily detected at runtime on i.MX53. Implement
such detection on MX53QSB and adjust the rest of the macros accordingly
to use the detected values.

An important thing to note here is that we had to override the function
for trimming the effective DRAM address, get_effective_memsize(). That
is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of
the available DRAM and we don't have gd->bd->bi_dram[0].size set up at
the time the function is called, thus we cannot put this into the macro
CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the
size of the first DRAM block which we just detected.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-03-31 18:28:51 +02:00
Marek Vasut
e919aa23ef ARM: mx6: Add PCIe on SabreSDP
Add support for PCIe on MX6 SabreSDP board and enable the support
in the config file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Liu Ying <Ying.Liu@freescale.com>
2014-03-31 18:28:50 +02:00
Masahiro Yamada
ba650e9b52 m68k: Remove M5271EVB and idmr board support
CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).

When compiling these two boards, a warning message is displayed:

  time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
  and should not be defined by platforms" [-Wcpp]

There are no board maintainers for them so this commit just
deletes them.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-03-10 11:38:13 -04:00
Priyanka Jain
96ac18c9cc powerpc/t104xrdb: Update DDR initialization related settings
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:48 -08:00
Priyanka Jain
337b0c52b3 powerpc/t1040qds: Add Video - HDMI support
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:40 -08:00
Shengzhou Liu
8d67c3685e powerpc/t2080rdb: Add T2080PCIe-RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.

T2080PCIe-RDB Feature Overview
------------------------------
Processor:
 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
 - Single memory controller capable of supporting DDR3 and DDR3-LP devices
 - 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
 - Two 10M/100M/1G RGMII ports on-board
 - Two 10Gbps SFP+ ports on-board
 - Two 10Gbps Base-T ports on-board
Accelerator:
 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
 - SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
 - NOR:  128MB 16-bit NOR flash
 - NAND: 512MB 8-bit NAND flash
 - CPLD: for system controlling with programable header on-board
eSPI:
 - 64MB N25Q512 SPI flash
USB:
 - Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
 - One PCIe x4 gold-finger
 - One PCIe x4 connector
 - One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
 - Two SATA 2.0 ports on-board
SDHC:
 - support a TF-card on-board
I2C:
 - Four I2C controllers.
UART:
 - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:13 -08:00
Shengzhou Liu
6b7679c8d2 powerpc/t208xqds: fixup for t208xqds
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
Fix EMI2 for t2080qds, which was caused by adding t2081qds.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:41 -08:00
Shaveta Leekha
7af9a07403 powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration

Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:01 -08:00
Shaveta Leekha
c4930b1a0e B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work
Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:50:56 -08:00
poonam aggrwal
c7d506d4ee 85xx/b4860: Alternate serdes protocols for B4860/B4420
On B4860 and B4420, some serdes protocols can be used with LC VCO as
well as Ring VCO options.

Addded Alternate options with LC VCO for such protocols.
For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.

The alternate option has the same functionality as the original option;
the only difference being LC VCO rather than Ring VCO.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:50:00 -08:00
Shaveta Leekha
fb07c0a16d board/b4860qds: Add support to make PCIe SATA work on B4860QDS
1) SerDes2 Refclks have been set properly to make
     PCIe SATA to work as it work on SerDes refclk of 100MHz
  2) Mask the SerDes's device reset request before changing
     the Refclks for SerDes1 and SerDes2 for PLL locks to
     happen properly, device reset request bit unmasked
     after SerDes refclks configuration

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:49:45 -08:00
Shaveta Leekha
5e5097c110 board/b4860qds: Add support to make Aurora work on B4860QDS
1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
   CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
   lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
   Aurora, CPRI and SGMIIs to work together properly

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:49:16 -08:00
Masahiro Yamada
e0708fb539 board: config.mk: delete unused sinclude directive
config.tmp is not there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-04 12:15:31 -05:00
Alexey Brodkin
1ace402239 sizes.h - consolidate for all architectures
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
2014-03-04 12:15:01 -05:00
Tom Rini
eeb72e6761 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	arch/arm/cpu/armv7/config.mk
	board/ti/am43xx/mux.c
	include/configs/am43xx_evm.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-26 16:49:58 -05:00
Albert ARIBAUD
d0b5d9da5d arm: make _end compiler-generated
This prevents references to _end from generating absolute
relocation records.

This change is binary invariant for ARM targets.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-02-26 21:18:09 +01:00
Tom Rini
a7e8c15f71 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-25 13:55:49 -05:00
Ying Zhang
c9e1f58818 powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPL
In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:32 -08:00
Shengzhou Liu
254887a57e powerpc/t2081qds: Add T2081 QDS board support
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:01 -08:00
York Sun
e38661634b common: Add get_effective_memsize() to memsize.c
This function has been around for powerpc. It is used for systems with
memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory,
this feature can limit U-boot to one block without going over the limit.

Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-02-21 11:06:13 -05:00
Albert ARIBAUD
3e11350255 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	Makefile
	drivers/net/npe/Makefile

These two conflicts arise from commit 0b2d3f20
("ARM: NET: Remove the IXP NPE ethernet driver") and are
resolved by deleting the drivers/net/npe/Makefile file
and removing the CONFIG_IXP4XX_NPE line from Makefile.
2014-02-20 13:16:05 +01:00
Masahiro Yamada
365475e6d1 Move #ifdef(CONFIG_DISPLAY_CPUINFO) from caller to callee
- When CONFIG_DISPLAY_CPUINFO is not enabled,
   print_cpuinfo() should be defined as an empty function
   in a header, include/common.h

 - Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif
   from caller, common/board_f.c and arch/arm/lib/board.c

 - Remove redundant prototypes in arch/arm/lib/board.c,
   arch/arm/include/asm/arch-am33x/sys_proto.h and
   board/nokia/rx51/rx51.h, keeping the one in include/common.h

 - Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition
   where it is missing

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-02-19 11:10:05 -05:00
Masahiro Yamada
7c8278a866 kbuild: add dummy obj-y to create built-in.o
We are going to switch over to Kbuild in upcoming commits.

Each makefile must have non-empty obj- or obj-y
to generate built-in.o on Kbuild.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-02-19 11:07:50 -05:00
Albert ARIBAUD
e7538fee99 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-02-19 12:04:45 +01:00
Stefano Babic
17998eff90 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-02-11 12:55:32 +01:00
Fabio Estevam
4702c62dce mx6qsabreauto: Update imximage.cfg
Use the latest DDR and clock settings as the one from Freescale BSP.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-02-11 11:24:12 +01:00
Priyanka Jain
714fd406da powerpc/t104xrdb: Add basic ethernet support
This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:49 -08:00
Prabhakar Kushwaha
5b7672fc49 boards/t1040qds: Adds ethernet support for T1040
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Prabhakar Kushwaha
e7222b5f49 powerpc/mpc85xx:Fix README to show correct flash memory map
Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.

Update rootfs start address to reflect correct memory map.

Also fix minor typo in README

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Haijun.Zhang
f28bea0003 eSDHC: Calculate envaddr accroding to the address format
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-22 08:56:44 -08:00
Prabhakar Kushwaha
e222b1f36f powerpc/mpc85xx:Increase binary size for P, B & T series boards.
u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.

So, Increase the u-boot binary size to 768KB.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-21 14:06:30 -08:00
Shengzhou Liu
3fdc827ca8 t2080qds/ddr: update ddr parameters
- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
  unrelated to DDR3/3L.

Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 14:02:21 -08:00
Po Liu
eb6b458cef powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
Using the TPL/SPL method to booting from 8k page NAND flash.
	- Add 256kB size SRAM tlb for second step booting;
	- Add spl.c for TPL image boot;
	- Add spl_minimal.c for minimal SPL image;
	- Add C29XPCIE_NAND configure;
	- Modify C29XPCIE.h for nand config and enviroment;

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:42:40 -08:00
Shengzhou Liu
1576b558b9 powerpc/t2080qds: some update for t2080qds
- add more serdes protocols support.
- fix some serdes lanes route.
- fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
- correct boot location info for SD/SPI boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:37:41 -08:00
Priyanka Jain
2eb3ac7fe8 powerpc/t1040qds: Update DDR initialization related settings
Update following DDR related settings for T1040QDS
-Correct number of chip selects to two as t1040qds supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
 read at 400KHz.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:35:20 -08:00
Albert ARIBAUD
bf46e7d8d1 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-15 15:18:04 +01:00
Fabio Estevam
5f98d0b5d3 mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.

No changes are made to mx6slevk, which uses the default 50MHz fec clock.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-15 10:33:25 +01:00
Albert ARIBAUD
e6fe4bd989 Merge 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-14 11:50:54 +01:00
Fabio Estevam
12c20c0c9b mx6slevk: Return from cpu_eth_init() directly
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

In order to simplify the code, just return the value from cpu_eth_init(bis)
directly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:28 +01:00
Fabio Estevam
92c707a580 mx6sabresd: Return from cpu_eth_init() directly
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

In order to simplify the code, just return the value from cpu_eth_init(bis)
directly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:27 +01:00
Fabio Estevam
579be2f760 mx6qsabreauto: Return from cpu_eth_init() directly
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

In order to simplify the code, just return the value from cpu_eth_init(bis)
directly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:27 +01:00