Commit graph

345 commits

Author SHA1 Message Date
Siew Chin Lim
96fe4f6485 arm: socfpga: smc: Add function to get usercode
Add function to send mailbox command via SMC to get usercode from SDM.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:13 +08:00
Siew Chin Lim
404a98b0a4 arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.

This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
3aef59f280 arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
e2ffb1da1d arm: socfpga: Restructure Stratix10 and Agilex handoff code
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.

Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.

Update system_manager_soc64.c to use generic handoff
function in wrap_handoff_soc64.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
a73514a8d2 arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
Rearrange sequence of macros in handoff_soc64.h without any functionality
change. In preparation for Stratix10 and Agilex handoff function
restructuring.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
bab26535cc arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
d623e52c9f arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
Rename to common file name to used by all SOC64 devices.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
8f337f3721 arm: socfpga: Rename Stratix10 and Agilex handoff common macros
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
f86ed75059 arm: socfpga: Move Stratix10 and Agilex SPL common code
Move Stratix10 and Agilex SPL common code to spl_soc64.c.
We are in preparation for new n5x device support.
No functional change in this patch.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:11 +08:00
Tom Rini
1057b1be75 Prepare v2021.04-rc5
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Merge tag 'v2021.04-rc5' into next

Prepare v2021.04-rc5
2021-03-29 18:00:21 -04:00
Siew Chin Lim
2dbcc037cc arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabled
Check CONFIG_SOCFPGA_SECURE_VAB_AUTH before perform 'is OS booted from FIT'
checking in board_prep_linux function. And, fix typo of
CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE.

CONFIG_FIT will be enabled in both ATF and VAB boot flow, thus,
board_prep_linux function will always be called by both ATF and
VAB boot flow.

board_pre_linux function will do 'is OS booted from FIT' checking,
and it will be called before board_fit_image_post_process function.

VAB boot flow expects the OS is always booted from FIT and with VAB
signed cerfiticate because the VAB authentication is implemented in
board_fit_image_post_process function. So, VAB needs the 'is OS booted
from FIT' checking in board_pre_linux function.

However, for ATF boot flow, it is not a requirement that the OS must
always booted from FIT. The OS can be booted from individual Image and
kernel dtb file. Thus, we should not do 'if OS is booted from FIT'
checking in board_prep_linux function.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-23 14:46:35 +08:00
Tom Rini
22fc991daf Prepare v2021.04-rc4
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Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4
2021-03-15 12:15:38 -04:00
Siew Chin Lim
1025b530a9 arm: socfpga: cmd: Support 'vab' command
Support 'vab' command to perform vendor authentication.

Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-08 10:59:10 +08:00
Siew Chin Lim
1bc20897c1 arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-08 10:59:10 +08:00
Siew Chin Lim
9a5bbdfd1a arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-08 10:59:10 +08:00
Harald Seiler
35b65dd8ef reset: Remove addr parameter from reset_cpu()
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.

Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).

To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.

This transformation was done with the following coccinelle patch:

    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()

    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-02 14:03:02 -05:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Siew Chin Lim
362787eb57 arm: socfpga: soc64: Enable FIT image generation using binman
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to
generate FIT images.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang
7cfb5d85ce arm: socfpga: soc64: Skip handoff data access in SSBL
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang
3b07cec93a arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang
018d27f251 arm: socfpga: soc64: Add ATF support for Reset Manager driver
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:37 +08:00
Siew Chin Lim
2e54a1d46c arm: socfpga: Add secure register access helper functions for SoC 64bits
These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15 17:48:36 +08:00
Chee Hong Ang
0eebfab3fe arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.

smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:36 +08:00
Chee Hong Ang
dbdc1df877 arm: socfpga: Disable "spin-table" method for booting Linux
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:35 +08:00
Chee Hong Ang
ac0c1fda90 arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:35 +08:00
Chee Hong Ang
acabb2acb0 arm: socfpga: Add function for checking description from FIT image
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:34 +08:00
Simon Glass
65e25bea59 dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
In the spirit of using the same base name for all of these related macros,
rename this to have the operation at the end. This is not widely used so
the impact is fairly small.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:26:35 -07:00
Ralph Siemsen
b0b08ce0b7 arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a8 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-21 11:45:54 +08:00
Dalon Westergreen
5c0adb0a71 arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Ley Foon Tan
de84e2d8c9 arm: socfpga: mailbox: Add mailbox retry support
Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.

Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Ley Foon Tan
6a48f95c6b arm: socfpga: mailbox: Update mailbox response codes
Sync latest mailbox response codes from SDM firmware.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
f6dcf40759 arm: socfpga: mailbox: Support sending large mailbox command
Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
833230ed33 arm: socfpga: mailbox: Always read mailbox responses before returning status
Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
e3fca5072b arm: socfpga: mailbox: Refactor mailbox timeout event handling
Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chin Liang See
e2afbee50c arm: socfpga: soc64: Document down boot_scratch_cold register usage
Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
5edf94d921 arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
bd99fa59d5 arm: socfpga: agilex: Enable FPGA Full Reconfiguration support
Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
d2170168dd fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
2473e13bb8 arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
b3e2d9fccb arm: socfpga: soc64: Show reset state in SPL
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
d7a1ff40d6 arm: socfpga: soc64: Add SDM triggered warm reset bit mask
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
12cc44884b arm: socfpga: soc64: Initialize timer in SPL only
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
464ca99f8e arm: socfpga: soc64: Remove PHY interface setup from misc arch init
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:10 +08:00
Chee Hong Ang
6b6307ed22 arm: socfpga: soc64: Check FPGA Config status register before bridge reset
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-09-03 11:26:07 +08:00
Tom Rini
6ca300aec0 socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.

Cc: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Vasut <marex@denx.de>
2020-07-01 10:11:03 -04:00
Ley Foon Tan
8a204312ab arm: socfpga: misc_s10: Fix EMAC register address calculation
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.

This fixes write to invalid address.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-26 11:30:24 +08:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f09f1ecbe7 Use __ASSEMBLY__ as the assembly macros
Some places use __ASSEMBLER__ instead which does not work since the
Makefile does not define it. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00