commit 626ee1e3 "phylib: update atheros ar803x phy"
leads in failing ethernet on the pxm2 board.
Calling genphy_config() instead of ar8021_config(),
which seems for ar8021 phys not ar803x phys, make
it working again.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The prescaler value for MDC is calculated wrong for
MX6S. Implement the same logic as linux here which handles
ENET_MAC different then original FEC.
Tested on a custom board with i.MX6S and 100MBit PHY
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:
* Flush Tx/Rx buffer descriptors their modification
* Invalidate Tx/Rx buffer descriptors before reading its values
* Flush cache for data passed from CPU to GMAC
* Invalidate cache for data passed from GMAC to CPU
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
* Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
* Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
* Support of custom phy initialization is now done with existing
"board_phy_config".
Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.
For example:
* CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
* CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used
I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".
In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.
So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the
kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot.
Signed-off-by: Aaron Wu <Aaron.Wu@analog.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
This driver is no longer used, remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michael Schwingen <michael@schwingen.org>
Cc: Tom Rini <trini@ti.com>
As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'.
When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
- add more serdes protocols support.
- fix some serdes lanes route.
- fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
- correct boot location info for SD/SPI boot.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
SH7753 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
As mEMAC1 and mEMAC2 are dual-role MACs, which are used as 1G or 10G MAC.
So we update dynamically 'cell-index' to '2' and '3' for 10GEC3 and 10GEC4.
Also change 'fsl,fman-port-1g-rx' to 'fsl,fman-port-10g-rx', ditto for Tx.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
In 48ec5291, only TX path was optimized; this does the same also for RX
path. This results in huge increase of TFTP throughput on custom am3352
board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer
timeouts.
Signed-off-by: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
This chip is compatible with the existing driver, except that it uses
BAR2 instead of BAR1 for the I/O memory region. Using this patch I can
use the PCIe ethernet interface on the CompuLab Trimslice to boot from
the network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276477
Instead of directly calling the low-level invalidate_dcache_range() and
flush_cache() functions, provide thin wrappers that take into account
alignment requirements.
While at it, fix a case where the cache was flushed but should have been
invalidated, two cases where the buffer data was flushed instead of the
descriptor and a missing cache invalidation before reading the packet
data that the NIC just wrote to memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276474
Added d-cache support for zynq_gem.c,
Observed a difference of +0.8 MiB/s when downloading
a file of size of 3007944Bytes.
With d-cache OFF:
----------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
#################################################################
#################################################################
##########
1.3 MiB/s
done
Bytes transferred = 3007944 (2de5c8 hex)
With d-cache ON:
---------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
#################################################################
#################################################################
##########
2.1 MiB/s
done
Bytes transferred = 3007944 (2de5c8 hex)
Changes on zynq_gem for d-cache support:
- Tx and Rx buffers are cache-aligned
- Updated logic for invalidating Rx buffers and flushing Tx buffers.
- Tx and Rx BD's are allocated from non-cacheable region.
(When BDs are cached, we don't see a consistent link)
- Use TX BD status intead of txsr status checks.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will
come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that
gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random
(and valid) locally administered MAC address that allows the system to
network boot until a real MAC address can be configured.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
The e1000 driver expects to always have some kind of non-volatile memory
attached directly to the ethernet controller chip. This means that I would
have to add an additional separate flash chip to my custom board just to
store essentially the MAC address. Since I don't want to do that, this patch
introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables
all accesses to the NVM. I have tested the patch with a 82574 controller.
Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
The masks were ignoring the last 4 bits which didn't allow detection differences
between the ar8031 and ar8035.
Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Patch: 288018
The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
So the phy id mask of AR8031 is the same to the phy id mask
of AR8035. The right mask value is 0x4fffff.
This patch has been tested on the P1010 and P1023.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 287748
Fix the 32-bit memory access that is not "endianess safe",
i.e. not giving the desired byte layout for LE cpus:
tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'.
Free the stack from rendundant local vars:
tmpbuf[] and i.
Use a portable type (u32) for the 32bit tsec register value
holder: tempval.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Use cross arch portable u32 instead of uint for the
tsec registers. Remove the typedefs for the register
struct definitions in the process. Fix long lines.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Currently, the buffer descriptor (BD) fields cannot be
correctly accessed by a little endian processor. This
patch fixes the issue by making the access of BDs to be
portable among different cpu architectures.
Use portable data types for the Rx/Tx buffer descriptor
fields. Use portable I/O accessors to insure that the
big endian BDs are correctly accessed by little endian
cpus too, and to insure proper sync with the H/W.
Removed the redundant RTXBD "volatile" type, as proper
synchronization around BD data accesses is provided by
the I/O accessors now.
The "sparse" tool was also used to verify the correctness
of these changes.
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Fix bufPtr and the rxIdx/ txIdx occurrences to
solve the related checkpatch warnings for the
coming patches.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Remove tsec_t typedef. Define macros as getters of
tsec and mdio register memory regions, for consistent
initialization of various 'regs' fields and also to
manage overly long initialization lines.
Use the __iomem address space marker to address sparse
warnings in tsec.c where IO accessors are used, like:
tsec.c:394:19: warning: incorrect type in argument 1 (different
address spaces)
tsec.c:394:19: expected unsigned int volatile [noderef]
<asn:2>*addr
tsec.c:394:19: got unsigned int *<noident>
[...]
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers
with __iomem pointers for tsec.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Access to privlist[1] (hardcoded referece to the 2nd tsec's
priv area) is neither correct nor does it make sense in the
current context. Each tsec dev has access to its own priv
instance only, and hence to its own set of group address
registers (GADDR) to filter multicast addresses.
This fix leads to removal of the unused (faulty) privlist[]
and related global static vars. Note that mcast() can be
called only after eth_device allocation and init, and hence
after priv area allocation, so dev->priv is correctly
initialized upon mcast() call.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278990
There are several implementation issues for tsec_mcast_addr()
addressed by this patch:
* unmanaged, not portable r/w access to registers; fixed with
setbits_be32()/ clrbits_be32()
* use of volatile pointers
* unnecessary forced cast to u8 for the ether_crc() result
* removed redundant parens
* corrected some comment slips
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 279000
This fixes the following compiler warnings when activating
CONFIG_MCAST_TFTP:
tsec.c: In function 'tsec_mcast_addr':
tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer
from integer without a cast [enabled by default]
In file included from /work/u-boot-net/include/common.h:874:0,
from tsec.c:15:
/work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned
char *' but argument is of type 'u8'
tsec.c: In function 'tsec_initialize':
tsec.c:646:13: warning: assignment from incompatible pointer type
[enabled by default]
eth.c: In function 'eth_mcast_join':
eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes
integer from pointer without a cast [enabled by default]
eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *'
In the eth_mcast_join() implementation, eth_current->mcast()
takes a u8 pointer to the multicast mac address and not a ip
address value as implied by its prototype.
Fix parameter type mismatch for tsec_macst_addr() (tsec.c):
ether_crc() takes a u8 pointer not a u8 value.
mcast() is given a u8 pointer to the multicats mac address.
Update parameter type for the rest of mcast() instances.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278989
It's important that buffer descriptors are aligned in accordance to GMAC
data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes)
for every bus width type.
If buffer descriptor is improperly aligned GMAC discards lower bits of
provided address and as a result reads from improper location that
doesn't match expected fields.
Commit ef76025a99 "net: Multiple
updates/enhancements to designware.c" introduced another structure
member "link_printed" right before buffer descriptors while "padding"
member was left untouched. This together with alignment of structure
itself to 16-byte boundary forces buffer descriptoprs always to be
4-byte aligned that causes driver complete disfunction if GMAC bus width
is 64 or 128-bit.
Proposed change makes sure all buffer descriptors are 16-byte (128-bit)
aligned.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Patch: 277902
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
R8A7791 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7791.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Joe Hershberger <joe.hershberger@gmail.com>
AR8035 driver will be never applied because of wrong mask for
AR8031 driver. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 276944
This chip is compatible with other RTL8168 chips and can be found on the
NVIDIA Cardhu and Beaver boards.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276475
currticks() is defined as get_timer(0), which returns an unsigned long,
so use %lu instead of %d to print the result.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276473
The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following
method to determine which driver is to be loaded for a particular PHY
module:
list_for_each(entry, &phy_drivers) {
drv = list_entry(entry, struct phy_driver, list);
if ((drv->uid & drv->mask) == (phy_id & drv->mask))
return drv;
}
This means that a drv->mask of 0xfffff0 will return incorrect phy driver
for the logic above, even if the drv->uid is anything other than
something ending with a 0x0.
For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff
and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then
the phy driver selected will always be RTL8211B even though the
underlying phy connected on the board is a 8211E module.
This patch fixes this issue.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
This patch adds support for VSC8514 PHY module which can be
found on Freescale's T1040RDB boards.
Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
R8A7790 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7790.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The sh-eth of rmobile needs to use invalidate_cache* function.
This patch adds invalidate_cache* function.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Patch: 268948
sh-eth can change the alignment size of a packet descriptor according to BUS
size. This patch adds this function.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The cache API of SH was changed from dcache_wback_range to flush_dcache_range.
sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Avoid a recently introduced unused variable warning for boards that
use mvgbe but not phylib.
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Patch: 266334
As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the
common driver. Currently AR8031_driver didn't work for AR8033,
hence updated it to have it work on AR8031/AR8033.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
The fec_halt() never free'd both RX and TX DMA descriptors that
were allocated in fec_init(), nor did it free the RX buffers.
Rework the FEC driver so that these descriptors and buffers are
allocated only once in fec_probe().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch
Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles]
Acked-by: York Sun <yorksun@freescale.com>
The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade. It is now
causing build issues. Instead of wasting time on things nobody is
interested in any more, we rather drop this board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>
Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
board/compulab/cm_t35/Makefile
board/corscience/tricorder/Makefile
board/ppcag/bg0900/Makefile
drivers/bootcount/Makefile
include/configs/omap4_common.h
include/configs/pdnb3.h
Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:
board/compulab/common/Makefile
board/udoo/Makefile
include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.
include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.
Note: 'git show' will also list two files just because
they are new:
include/configs/am335x_igep0033.h
include/configs/omap3_igep00x0.h
On relatively slow boards (such as the MIPS Malta with an FPGA core
card) it can be extremely common for transmits to underflow - to the
point where it appears they simply do not work at all. Setting the
NOUFLO bit causes the ethernet controller to not begin transmission on
the wire until a transmit start point is reached. Setting that transmit
start point to the full packet will cause the controller to only
transmit the packet once it has buffered it entirely thus preventing any
transmit underflows from occuring and allowing the controller to
function on slower boards.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Ensure that the view of memory from the CPU & the ethernet controller is
coherent at the various points where they exchange data. This prevents
stale data from being transmitted or received, and prevents the driver
from getting stuck waiting for the ethernet controller to update
descriptors when in reality it has but the old values are being read
from cache.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fix up the code to match Documentation/CodingStyle. This is mostly
removing extraneous spaces.
No functional change is intended.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Netconsole loses the second character when used as input by
either setenv stdin nc or setenv stdin serial,nc if using CONSOLE_CONSOLE_MUX
Before a nc_send_packet() to echo the input, a check is done to see if
nc_ether is valid. If its not, it waits for an arp request and then sends
the packet (which contains the first character of line to be displayed as
output). As part of reaping the arp request, the second character is consumed.
We protect this by making the call to NetLoop(NETCONS) between
input_recursion.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Get DMA bus width from design config register
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This can be useful if one wants to disable an interface in u-boot
because u-boot should not manage it but then later reenable it for FDT
fixing or if the kernel uses this interface.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix conflict in fm_eth.h]
Acked-by: York Sun <yorksun@freescale.com>
T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.
T1040QDS board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
— SATA 2.0
— Aurora debug with dedicated connectors
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
— Two type A ports with 5V@1.5A per port.
— Second port can be converted to OTG mini-AB
- SDHC
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
— Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.
QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
1. Confirm whether QSGMII Riser Card is used.
2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.
However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
if phy_connect() did not find a phy, phydev is NULL and
following code in cpsw_phy_init() crashes. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Performing tftp transfers on mx28 results in random timeouts.
Hector Palacios and Robert Hodaszi analyzed the root cause being related to the
wrong alignment of the 'buff' buffer inside fec_recv().
Benoît Thébaudeau provided an excellent analysis of the alignment bug that is
present on older versions, such as GCC 4.5.4:
http://marc.info/?l=u-boot&m=137942904906131&w=2
Use ALLOC_CACHE_ALIGN_BUFFER() to avoid alignment issues from older GCC
versions.
Reported-by: Hector Palacios <hector.palacios@digi.com>
Tested-by: Oliver Metz <oliver@freetz.org>
Tested-by: Hector Palacios <hector.palacios@digi.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
Similarly as mx25 and mx53, mx6solo-lite needs to setup the MII gasket for RMII
mode.
Add support for mx6solo-lite.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license. However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word. I'd prefer
to be consistent to this end".
Change the license IDs to use the official name.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix various misspellings of things like "environment", "kernel",
"default" and "volatile", and throw in a couple grammar fixes.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
fix the following building warning
---8>---
macb.c: In function 'macb_init':
macb.c:400:14: warning: 'phydev' may be used uninitialized in this function
macb.c:377:21: note: 'phydev' was declared here
---<8---
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Without this change, the following message is generated:
Warning: FEC using MAC address from net device
See doc/README.enetaddr for details.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
This commit adapts the files that were derived from PIBS (PowerPC
Initialization and Boot Software) codeto using SPDX License
Identifiers.
So far, SPDX has not assigned an official License ID for the PIBS
license yet, so this should be considered preliminary.
Note that the following files contained incorrect license information:
arch/powerpc/cpu/ppc4xx/4xx_uart.c
arch/powerpc/cpu/ppc4xx/start.S
arch/powerpc/include/asm/ppc440.h
These files included, in addition to the GPL-2.0 / ibm-pibs dual
license as inherited from PIBS, a GPL-2.0+ license header which was
obviously incorrect. This has been removed.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Conflicts:
Licenses/README
Acked-by: Stefan Roese <sr@denx.de>
1. Reformat tx/rx descriptor as an uniform struct.
2. Replace uint32_t[2] with uint64_t for descriptor control.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Joe Hershberger <joe.hershberger@gmail.com>
This patch adds support for Realtek PHY modules RTL8211DN and
RTL8211E (variants: RTL8211E-VB-CG, RTL8211E-VL-CG, RTL8211EG-VB-CG),
which can be found on Freescale's T1040RDB boards.
To make the driver more generic across 8211 family, a generic name 8211x
is added for macros and function names.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Use ARRAY_SIZE instead of having similar implementation in each drivers.
The NUMELEMS defined in drivers/net/npe/include/IxOsalTypes.h is not used
at all, so this patch removes it instead of converting it to use ARRAY_SIZE.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.
Conflicts:
arch/arm/include/asm/arch-am33xx/hardware.h
Signed-off-by: Tom Rini <trini@ti.com>
FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.
Signed-off-by: York Sun <yorksun@freescale.com>
accessing a lan9303 switch with the cpsw driver results in wrong
speed detection, as the switch sets the BMSR_ERCAP in BMSR
register, and follow read of the MII_STAT1000 register fails, as
the switch does not support it. Current code did not check,
if a phy_read() fails ... fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
BD ram address may vary in various SOC, so removing the hardcoding and
passing the same information through platform data
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
There is no reason to wait for the entire frame to start DMA on receive,
so enable rx cut-thru for better performance.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.
On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the
checking for ESTATUS_1000_XHALF, but it incorrectly sets the
SUPPORTED_1000baseX_Full flag in this case.
Set the SUPPORTED_1000baseX_Half flag instead.
Acked-by: Charles Coldwell <coldwell@gmail.com>
Reviewed-By: Sascha Silbe <t-uboot@infra-silbe.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a
check for the extended status register in order to support
1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since
Extended Status only indicates what the PHY (i.e. the local side) is
capable of, this broke communication with non-1Gbps peers.
Only check the extended status if the 1000BASE-T registers are
actually missing so we don't end up setting speed to 1Gbps even though
the previous test (for the combination of local and peer support for
1Gbps) already indicated we can't do 1Gbps with the current peer.
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.
Conflicts:
arch/arm/dts/exynos5250.dtsi
Signed-off-by: Tom Rini <trini@ti.com>
The MX28 multi-layer AHB bus can be too slow and trigger the
FEC DMA too early, before all the data hit the DRAM. This patch
ensures the data are written in the RAM before the DMA starts.
Please see the comment in the patch for full details.
This patch was produced with an amazing help from Albert Aribaud,
who pointed out it can possibly be such a bus synchronisation
issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Remove incorrectly called and duplicate flush_dcache_range() call
from fec_mxc driver. The call is not needed, since the caches are
already flushed in fec_tbd_init(), moreover the second argument should
be the ending address, not size.
Signed-off-by: Marek Vasut <marex@denx.de>
Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
add atheros ar803x phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
add natsemi dp83630 phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
The device interface is 16 bits wide.
All the available packets are read from the incoming fifo.
Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it>
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
[voice.shen@atmel.com: address comments from review results]
[voice.shen@atmel.com: clean up for submit]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <coldwell@ll.mit.edu>
Date: Tue Feb 19 08:27:33 2013 -0500
Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)
Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Joe Herschberger <joe.hershberger@gmail.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This patch adds support for the WEMAC, the ethernet controller included
in the Allwinner A10 SoC. It will get used in the upcoming A10 board
support.
From: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
This patch adds FEC support for Vybrid VF610 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
MAC node disabled incorrectly.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO
Do not enable emio for this standard board configuration for now.
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Pass the PHY address to the driver init to
allow parallel use of both interfaces
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.
This patch solves the problem with repeatable tftp transfers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)
TRM: (Table 16-3: Tx Buffer Descriptor Entry)
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This phy is used on zedboard (xilinx zynq platform).
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
- In arch/arm/cpu/armv7/omap-common/timer.c,
drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
<asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
as that is the only include which defines things the config uses.
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance. With this the performance
is increased from 208KiB/s to 375KiB/s on EVMsk
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
It is useful to be able to try a range of
possible phy addresses to connect.
Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Only the hardware ethernet registers are needed
for this function, so don't pass the more general
structure. I'm trying to separate MII and fec.
This also fixes MX28 fec_mii_setspeed use on secondary ethernet port
This was found by inspection of the code and should be
checked on real hardware.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
It is more logical to test for CONFIG_FEC_MXC_PHYADDR
to determine whether to define the function fecmxc_initialize.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
SH7752 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marvell 88E1118R has different uid then 88E1118.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Andy Fleming <afleming@freescale.com>
CC: Zang Roy-R61911 <tie-fei.zang@freescale.com>
CC: Kumar Gala <galak@kernel.crashing.org>
In e1000e driver, Rx descriptor queue is used such that hardware can add only
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set
to single descriptor. This would ensure that every time controller fills a Rx
descriptor, it is flushed to host memory. Earlier this granularity was in
cache line units i.e 2 descriptors. This leads to controller always waiting
for 2 descriptors before flushing them out. But since not more than one Rx BD
is actually available , the accumulation condition never gets hit.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?
Note: in the ping.c fix, commit a36b12f95a
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.
struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The following warning was produced, fix it:
mcfmii.c: In function 'mcffec_miiphy_write':
mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: James MacAulay <james.macaulay@amirix.com>
Acked-by: Marek Vasut <marex@denx.de>
The mechanism waiting for transmission to finish in fec_send() now
relies on the E-bit being cleared in the TX buffer descriptor. In
case of data cache being on, this means invalidation of data cache
above this TX buffer descriptor on each test for the E-bit being
cleared.
Apparently, there is another way to check if the transmission did
complete. This is by checking the TDAR bit in the X_DES_ACTIVE
register. Reading a register does not need any data cache invalidation,
which is beneficial.
Rework the sequence that wait for completion of the transmission so that
the TDAR bit is tested first and afterwards check the E-bit being clear.
This cuts down the number of cache invalidation calls to one.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The FEC hardware sometimes errors out on data transfer and hangs in
the tightloop adjusted by this patch. So add timeout into the tightloop
to make such a hang recoverable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Align the address that's to be invalidated/flushed properly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advans>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Do not pass unaligned RX buffer to the upper layers. The upper layer,
especially in the ARP case, recycles the buffer and passes it back into
the FEC, into it's TX path. With caches enabled, the FEC hangs on this
from time to time.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advans>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
-VSC8662 is Dual Port 10/100/1000Base-T Phy,
100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.
-Its register set and features are similar to
other Vitesse Phys
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This patch add support for the configuration of an external switch from
the 88E6xxx series from Marvell trough an MDIO link using indirect
adressing. This can be used if we do not want to use an EEPROM for the
configuration.
This driver is not generic and was not tested on other switches than the
88e6352. This is proposed as a first implementation that is somewhat
limited but works and that can be used as a basis for further
developments for this switch family.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Device driver for Zynq Gem IP.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Check the incoming packets' source IP address... if ncip isn't set to a
broadcast address, only listen to the client at ncip.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Refresh the netconsole settings from the env before each packet instead
of only on netconsole init.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Previously u-boot would initialize the network interface for every
network operation and then shut it down again. This makes sense for
most operations where the network in not known to be needed soon after
the operation is complete. In the case of netconsole, it will use the
network for every interaction with the shell or every printf. This
means that the network is being reinitialized very often. On many
devices, this intialization is very slow.
This patch checks for consecutive netconsole actions and leaves the
ethernet hardware initialized between them. It will still behave the
same old way for all other network operations and any time another
network operation happens between netconsole operations.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Allow a board to configure a larger buffer for netconsole, but leave
the default.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
R8A7740 of rmobile has ethernet device, and this is same IP of
sh-ether. This support R8A7740 of rmobile.
Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Apply the following questionable adjustment to silence GCC.
armada100_fec.c: In function ‘armdfec_send’:
armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Support new CONFIG_OF_CONTROL option where device
probing is done based on device tree description.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
It is desirable to use different port numbers for sending and receiving
packets with netconsole in the case where you have more than one device
on the local subnet with netconsole enabled for broadcast. When they
use the same port for both, any output from one will look like input to
the other. This is typlically not desirable.
This patch allows the input and output ports to be specified separately
in the environment.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
greth.c: In function ‘greth_recv’:
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘unsigned int’ [-Wformat]
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘unsigned int’ [-Wformat]
greth.c:541:6: warning: pointer targets in assignment differ in signedness [-Wpointer-sign]
greth.c: In function ‘greth_initialize’:
greth.c:623:2: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:655:3: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:684:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: u-boot-dm@lists.denx.de
* 'master' of git://git.denx.de/u-boot-avr32:
net:macb: add line break
avr32:portmux: fix setup for macb1
avr32: Remove redundant LDSCRIPT definition
Signed-off-by: Wolfgang Denk <wd@denx.de>
Without this patch we see annoying output like this:
---8<---
U-Boot> dhcp
macb1: PHY not foundmacb0: PHY present at 1
macb0: Starting autonegotiation...
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.
This patch also adds support to clean and flush dcache during packet send
and receive.
Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's
GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757,
the driver handles the GETHER.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The previous code had many similar definitions in each CPU.
This patch borrows from the sh_eth driver of Linux kernel.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
At the moment, the driver supports the following CPUs:
- GETHER (Gigabit Ethernet) : SH7763, SH7734
- ETHER (Fast Ethernet) : SH7724, SH7757
And the driver had the following "#if":
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
- Those are for GETHER
#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
- This is for ETHER
So, for clean up the code, this patch adds SH_ETH_TYPE_GETHER and
SH_ETH_TYPE_ETHER. And then, the patch modifies the above "#if".
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The SH7757's ETHER can work using the SH7724's setting. So, the patch
modifies it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so
mii_speed has to be set for all these interfaces, and not only for MII.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
At least on i.MX25, the RMII mode did not work, which is fixed by this patch.
The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set
it accordingly.
According to the xMII and 7-wire (aka GPSI) standards, full duplex should be
available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may
support full duplex for 7-wire too, but the reference manual does not say that,
so avoid an invalid assumption. Actually, the choice between half and full
duplex also depends on the endpoint/switch/repeater configuration, so a config
option could be added for that, but there has been no need for it so far.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Now that common code doesn't declare these as volatile, we don't need to
either anymore. This fixes the build warning:
bfin_mac.c: In function 'bfin_EMAC_recv':
bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 'next' of git://git.denx.de/u-boot-net:
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
Micrel accidentally used the same part number
for the KS8721 and KSZ9021. So, both cannot be
in the same build of u-boot. Add a config option
to handle this.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part)
Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac)
Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.
Signed-off-by: Timur Tabi <timur@freescale.com>
When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed.
Therefore SH7757 and SH7724 can not build. This revise this probelem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This patch adds the following changes to designware ethernet driver
found on the ST SPEAr SoC:
- Don't init MAC & PHY upon startup. This causes a delay, waiting for
the auto negotiation to complete. And we don't want this delay to
always happen. Especially not on platforms where ethernet is not
used at all (e.g. booting via flash).
Instead postpone the MAC / PHY configuration to the stage, where
ethernet is first used.
- Add possibility for board specific PHY init code. This is needed
for example on the X600 board, where the Vitesse PHY needs to be
configured for GMII mode.
This board specific PHY init is done via the function
designware_board_phy_init(). And this driver now adds a weak default
which can be overridden by board code.
- Use common functions miiphy_speed() & miiphy_duplex() to read
link status from PHY.
- Print status and progress of auto negotiation.
- Print link status (speed, dupex) upon first usage.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
Few Designware peripheral registers need to be modified based on the
ethernet interface selected by the board. This patch supports interface
information in ethernet driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was not performed. This patch enables
auto negotiation in RMII mode. Without this patch, EMAC
initialization takes more time and sometimes tftp fails
in RMII mode.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
SH7734 support GMII. This add register infomation and the function
which enable GMII.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
SH7734 has one channel ethernet device.
This support 10/100/1000Base, and RMII/MII/GMII.
And this has the same structure as SH7763.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
