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net: tsec: Use portable regs type (uint->u32)
Use cross arch portable u32 instead of uint for the tsec registers. Remove the typedefs for the register struct definitions in the process. Fix long lines. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
This commit is contained in:
Claudiu Manoil
Joe Hershberger
parent
9c9141fd04
commit
82ef75ca5c
2 changed files with 136 additions and 138 deletions
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@ -166,7 +166,7 @@ static void init_registers(struct tsec __iomem *regs)
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out_be32(®s->rctrl, 0x00000000);
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/* Init RMON mib registers */
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memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
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memset((void *)®s->rmon, 0, sizeof(regs->rmon));
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out_be32(®s->rmon.cam1, 0xffffffff);
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out_be32(®s->rmon.cam2, 0xffffffff);
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272
include/tsec.h
272
include/tsec.h
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@ -210,179 +210,177 @@ struct rxbd8 {
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uint32_t bufptr; /* Buffer Pointer */
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};
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typedef struct rmon_mib
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{
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struct tsec_rmon_mib {
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/* Transmit and Receive Counters */
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uint tr64; /* Transmit and Receive 64-byte Frame Counter */
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uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
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uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
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uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
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uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
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uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
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uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
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u32 tr64; /* Tx/Rx 64-byte Frame Counter */
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u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
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u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
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u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
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u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
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u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
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u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
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/* Receive Counters */
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uint rbyt; /* Receive Byte Counter */
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uint rpkt; /* Receive Packet Counter */
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uint rfcs; /* Receive FCS Error Counter */
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uint rmca; /* Receive Multicast Packet (Counter) */
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uint rbca; /* Receive Broadcast Packet */
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uint rxcf; /* Receive Control Frame Packet */
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uint rxpf; /* Receive Pause Frame Packet */
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uint rxuo; /* Receive Unknown OP Code */
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uint raln; /* Receive Alignment Error */
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uint rflr; /* Receive Frame Length Error */
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uint rcde; /* Receive Code Error */
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uint rcse; /* Receive Carrier Sense Error */
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uint rund; /* Receive Undersize Packet */
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uint rovr; /* Receive Oversize Packet */
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uint rfrg; /* Receive Fragments */
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uint rjbr; /* Receive Jabber */
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uint rdrp; /* Receive Drop */
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u32 rbyt; /* Receive Byte Counter */
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u32 rpkt; /* Receive Packet Counter */
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u32 rfcs; /* Receive FCS Error Counter */
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u32 rmca; /* Receive Multicast Packet (Counter) */
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u32 rbca; /* Receive Broadcast Packet */
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u32 rxcf; /* Receive Control Frame Packet */
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u32 rxpf; /* Receive Pause Frame Packet */
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u32 rxuo; /* Receive Unknown OP Code */
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u32 raln; /* Receive Alignment Error */
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u32 rflr; /* Receive Frame Length Error */
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u32 rcde; /* Receive Code Error */
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u32 rcse; /* Receive Carrier Sense Error */
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u32 rund; /* Receive Undersize Packet */
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u32 rovr; /* Receive Oversize Packet */
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u32 rfrg; /* Receive Fragments */
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u32 rjbr; /* Receive Jabber */
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u32 rdrp; /* Receive Drop */
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/* Transmit Counters */
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uint tbyt; /* Transmit Byte Counter */
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uint tpkt; /* Transmit Packet */
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uint tmca; /* Transmit Multicast Packet */
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uint tbca; /* Transmit Broadcast Packet */
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uint txpf; /* Transmit Pause Control Frame */
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uint tdfr; /* Transmit Deferral Packet */
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uint tedf; /* Transmit Excessive Deferral Packet */
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uint tscl; /* Transmit Single Collision Packet */
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u32 tbyt; /* Transmit Byte Counter */
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u32 tpkt; /* Transmit Packet */
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u32 tmca; /* Transmit Multicast Packet */
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u32 tbca; /* Transmit Broadcast Packet */
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u32 txpf; /* Transmit Pause Control Frame */
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u32 tdfr; /* Transmit Deferral Packet */
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u32 tedf; /* Transmit Excessive Deferral Packet */
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u32 tscl; /* Transmit Single Collision Packet */
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/* (0x2_n700) */
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uint tmcl; /* Transmit Multiple Collision Packet */
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uint tlcl; /* Transmit Late Collision Packet */
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uint txcl; /* Transmit Excessive Collision Packet */
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uint tncl; /* Transmit Total Collision */
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u32 tmcl; /* Transmit Multiple Collision Packet */
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u32 tlcl; /* Transmit Late Collision Packet */
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u32 txcl; /* Transmit Excessive Collision Packet */
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u32 tncl; /* Transmit Total Collision */
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uint res2;
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u32 res2;
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uint tdrp; /* Transmit Drop Frame */
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uint tjbr; /* Transmit Jabber Frame */
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uint tfcs; /* Transmit FCS Error */
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uint txcf; /* Transmit Control Frame */
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uint tovr; /* Transmit Oversize Frame */
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uint tund; /* Transmit Undersize Frame */
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uint tfrg; /* Transmit Fragments Frame */
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u32 tdrp; /* Transmit Drop Frame */
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u32 tjbr; /* Transmit Jabber Frame */
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u32 tfcs; /* Transmit FCS Error */
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u32 txcf; /* Transmit Control Frame */
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u32 tovr; /* Transmit Oversize Frame */
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u32 tund; /* Transmit Undersize Frame */
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u32 tfrg; /* Transmit Fragments Frame */
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/* General Registers */
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uint car1; /* Carry Register One */
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uint car2; /* Carry Register Two */
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uint cam1; /* Carry Register One Mask */
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uint cam2; /* Carry Register Two Mask */
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} rmon_mib_t;
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u32 car1; /* Carry Register One */
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u32 car2; /* Carry Register Two */
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u32 cam1; /* Carry Register One Mask */
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u32 cam2; /* Carry Register Two Mask */
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};
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typedef struct tsec_hash_regs
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{
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uint iaddr0; /* Individual Address Register 0 */
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uint iaddr1; /* Individual Address Register 1 */
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uint iaddr2; /* Individual Address Register 2 */
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uint iaddr3; /* Individual Address Register 3 */
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uint iaddr4; /* Individual Address Register 4 */
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uint iaddr5; /* Individual Address Register 5 */
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uint iaddr6; /* Individual Address Register 6 */
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uint iaddr7; /* Individual Address Register 7 */
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uint res1[24];
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uint gaddr0; /* Group Address Register 0 */
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uint gaddr1; /* Group Address Register 1 */
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uint gaddr2; /* Group Address Register 2 */
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uint gaddr3; /* Group Address Register 3 */
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uint gaddr4; /* Group Address Register 4 */
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uint gaddr5; /* Group Address Register 5 */
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uint gaddr6; /* Group Address Register 6 */
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uint gaddr7; /* Group Address Register 7 */
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uint res2[24];
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} tsec_hash_t;
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struct tsec_hash_regs {
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u32 iaddr0; /* Individual Address Register 0 */
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u32 iaddr1; /* Individual Address Register 1 */
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u32 iaddr2; /* Individual Address Register 2 */
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u32 iaddr3; /* Individual Address Register 3 */
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u32 iaddr4; /* Individual Address Register 4 */
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u32 iaddr5; /* Individual Address Register 5 */
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u32 iaddr6; /* Individual Address Register 6 */
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u32 iaddr7; /* Individual Address Register 7 */
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u32 res1[24];
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u32 gaddr0; /* Group Address Register 0 */
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u32 gaddr1; /* Group Address Register 1 */
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u32 gaddr2; /* Group Address Register 2 */
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u32 gaddr3; /* Group Address Register 3 */
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u32 gaddr4; /* Group Address Register 4 */
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u32 gaddr5; /* Group Address Register 5 */
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u32 gaddr6; /* Group Address Register 6 */
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u32 gaddr7; /* Group Address Register 7 */
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u32 res2[24];
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};
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struct tsec {
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/* General Control and Status Registers (0x2_n000) */
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uint res000[4];
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u32 res000[4];
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uint ievent; /* Interrupt Event */
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uint imask; /* Interrupt Mask */
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uint edis; /* Error Disabled */
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uint res01c;
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uint ecntrl; /* Ethernet Control */
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uint minflr; /* Minimum Frame Length */
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uint ptv; /* Pause Time Value */
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uint dmactrl; /* DMA Control */
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uint tbipa; /* TBI PHY Address */
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u32 ievent; /* Interrupt Event */
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u32 imask; /* Interrupt Mask */
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u32 edis; /* Error Disabled */
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u32 res01c;
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u32 ecntrl; /* Ethernet Control */
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u32 minflr; /* Minimum Frame Length */
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u32 ptv; /* Pause Time Value */
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u32 dmactrl; /* DMA Control */
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u32 tbipa; /* TBI PHY Address */
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uint res034[3];
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uint res040[48];
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u32 res034[3];
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u32 res040[48];
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/* Transmit Control and Status Registers (0x2_n100) */
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uint tctrl; /* Transmit Control */
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uint tstat; /* Transmit Status */
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uint res108;
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uint tbdlen; /* Tx BD Data Length */
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uint res110[5];
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uint ctbptr; /* Current TxBD Pointer */
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uint res128[23];
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uint tbptr; /* TxBD Pointer */
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uint res188[30];
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u32 tctrl; /* Transmit Control */
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u32 tstat; /* Transmit Status */
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u32 res108;
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u32 tbdlen; /* Tx BD Data Length */
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u32 res110[5];
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u32 ctbptr; /* Current TxBD Pointer */
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u32 res128[23];
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u32 tbptr; /* TxBD Pointer */
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u32 res188[30];
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/* (0x2_n200) */
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uint res200;
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uint tbase; /* TxBD Base Address */
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uint res208[42];
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uint ostbd; /* Out of Sequence TxBD */
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uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
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uint res2b8[18];
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u32 res200;
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u32 tbase; /* TxBD Base Address */
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u32 res208[42];
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u32 ostbd; /* Out of Sequence TxBD */
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u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
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u32 res2b8[18];
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/* Receive Control and Status Registers (0x2_n300) */
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uint rctrl; /* Receive Control */
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uint rstat; /* Receive Status */
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uint res308;
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uint rbdlen; /* RxBD Data Length */
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uint res310[4];
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uint res320;
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uint crbptr; /* Current Receive Buffer Pointer */
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uint res328[6];
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uint mrblr; /* Maximum Receive Buffer Length */
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uint res344[16];
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uint rbptr; /* RxBD Pointer */
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uint res388[30];
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u32 rctrl; /* Receive Control */
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u32 rstat; /* Receive Status */
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u32 res308;
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u32 rbdlen; /* RxBD Data Length */
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u32 res310[4];
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u32 res320;
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u32 crbptr; /* Current Receive Buffer Pointer */
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u32 res328[6];
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u32 mrblr; /* Maximum Receive Buffer Length */
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u32 res344[16];
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u32 rbptr; /* RxBD Pointer */
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u32 res388[30];
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/* (0x2_n400) */
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uint res400;
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uint rbase; /* RxBD Base Address */
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uint res408[62];
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u32 res400;
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u32 rbase; /* RxBD Base Address */
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u32 res408[62];
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/* MAC Registers (0x2_n500) */
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uint maccfg1; /* MAC Configuration #1 */
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uint maccfg2; /* MAC Configuration #2 */
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uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
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uint hafdup; /* Half-duplex */
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uint maxfrm; /* Maximum Frame */
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uint res514;
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uint res518;
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u32 maccfg1; /* MAC Configuration #1 */
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u32 maccfg2; /* MAC Configuration #2 */
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u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
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u32 hafdup; /* Half-duplex */
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u32 maxfrm; /* Maximum Frame */
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u32 res514;
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u32 res518;
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uint res51c;
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u32 res51c;
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uint resmdio[6];
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u32 resmdio[6];
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uint res538;
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u32 res538;
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uint ifstat; /* Interface Status */
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uint macstnaddr1; /* Station Address, part 1 */
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uint macstnaddr2; /* Station Address, part 2 */
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uint res548[46];
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u32 ifstat; /* Interface Status */
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u32 macstnaddr1; /* Station Address, part 1 */
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u32 macstnaddr2; /* Station Address, part 2 */
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u32 res548[46];
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/* (0x2_n600) */
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uint res600[32];
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u32 res600[32];
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/* RMON MIB Registers (0x2_n680-0x2_n73c) */
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rmon_mib_t rmon;
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uint res740[48];
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struct tsec_rmon_mib rmon;
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u32 res740[48];
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/* Hash Function Registers (0x2_n800) */
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tsec_hash_t hash;
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struct tsec_hash_regs hash;
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uint res900[128];
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u32 res900[128];
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/* Pattern Registers (0x2_nb00) */
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uint resb00[62];
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uint attr; /* Default Attribute Register */
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uint attreli; /* Default Attribute Extract Length and Index */
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u32 resb00[62];
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u32 attr; /* Default Attribute Register */
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u32 attreli; /* Default Attribute Extract Length and Index */
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/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
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uint resc00[256];
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u32 resc00[256];
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};
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#define TSEC_GIGABIT (1 << 0)
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