In order to better compare the Linux rk3288.dtsi version
with the u-boot version update the cpu and gpu nodes.
Changed:
use operating-points-v2
update thermal for all cpus
add labels to all cpus
change gpu compatible
change gpu interrupt names
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi version
with the u-boot version move thermal sub nodes to the dtsi
file and remove rk3288-thermal.dtsi
Changed:
replace underscore in nodename
remove comments about sensor and ID
use gpu phandle
add #cooling-cells to gpu node
lower critical temparature
remove linux,hwmon property
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The phycore_rk3288 board has a SPL size problem,
so remove phycore_init() function to stay within the limits.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Provide a simple sandbox driver for the thermal uclass.
It simply registers and returns 100 degrees C if requested.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is used as delay for gpmi write strobe.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
- Update RISC-V to use 32bit or 64bit toolchains, depending on if we're
building for 32bit or 64bit CPUs. This requires updating the Docker
container as well to have the 32bit toolchain.
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
make W=1 generates the following warning in cpu_disable, cpu_status and
cpu_release functions.
arch/arm/mach-zynqmp/mp.c:166:16: warning: comparison of unsigned expression
in '>= 0' is always true [-Wtype-limits]
166 | if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
| ^~
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221004053454.25470-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
When MMU is already enabled then dcache_enable() does not call mmu_setup()
and so setup_all_pgtables() is also never called.
In this situation when some driver calls mmu_set_region_dcache_behaviour()
function then U-Boot crashes with error message:
Emergency page table not setup.
Fix this issue by explicitly calling setup_all_pgtables() in dcache_enable()
function near condition for mmu_setup().
This change fixes chainloading U-Boot from U-Boot on Turris Mox board which
uses mvneta ethernet driver which calls mmu_set_region_dcache_behaviour().
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
In order to move ppc-specific code out of setup_dest_addr(), provide an
arch-specific variant arch_setup_dest_addr(), that can be used by
architecture code to fix up the initial reloc address.
It is called at the end of setup_dest_addr() initcall and the default
implementation is a nop stub.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
asm/mach_type.h header and CONFIG_MACH_TYPE macro are arm-specific, so move
related bdinfo logic to arch_setup_bdinfo() in arch/arm/lib/bdinfo.c.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
The XTRN_DECLARE_GLOBAL_DATA_PTR declarations in ppc code are permanently
commented out, so there are no users for this macro:
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
#else /* We could use plain global data, but the resulting code is bigger */
#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
gd_t *gd
#endif
Remove all references to this macro, but add a documentation note regarding
the possibility of using plain global data for the GD pointer.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
VHV_Enable GPIO is required to enable during eFuse programming on Armada
SoCs not from 3700 family. Add support for enabling and disabling VHV pin
via GPIO during eFuse programming, when specified.
All details are in Marvell AN-389: ARMADA VHV Power document
(Doc. No. MV-S302545-00 Rev. C, August 2, 2016).
Note that due to HW Errata 3.6 eFuse erroneous burning (Ref #: HWE-3718342)
VHV power must be disabled while core voltage is off to prevent erroneous
eFuse programming.
This is specified in Marvell ARMADA 380/385/388 Functional Errata,
Guidelines, and Restrictions document
(Doc. No. MV-S501377-00 Rev. D, December 1, 2016).
Signed-off-by: Pali Rohár <pali@kernel.org>
This patch implements LD eFuse programming support. Armada 385 contains two
LD eFuse lines, each is 256 bit long with one additional lock bit. LD 0
line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. U-Boot
32-bit fuse words 0-8 are mapped to LD eFuse line bits 0-255. U-Boot fuse
word 9 is mapped to LD eFuse line lock bit.
So to program LD 1 General Purpose Data line, use U-Boot fuse command:
=> fuse prog -y 65 0 0x76543210
=> fuse prog -y 65 1 0xfedcba98
=> fuse prog -y 65 2 0x76543210
=> fuse prog -y 65 3 0xfedcba98
=> fuse prog -y 65 4 0x76543210
=> fuse prog -y 65 5 0xfedcba98
=> fuse prog -y 65 6 0x76543210
=> fuse prog -y 65 7 0xfedcba98
=> fuse prog -y 65 8 0x1
Signed-off-by: Pali Rohár <pali@kernel.org>
Since the move to CONFIG_TIMER with support for CONFIG_TIMER_EARLY, this
platform specific init_timer() function is not needed any more. Let's
remove it completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michael Walle <michael@walle.cc>
Cc: Pali Rohár <pali@kernel.org>
These boards are out of maintenance and can be removed.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
Reviewed-by: Stefan Roese <sr@denx.de>
For future DM based FPGA drivers and for now to have a meaningful
logging class for old FPGA drivers.
Suggested-by: Michal Simek <michal.simek@amd.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Dahl <post@lespocky.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
When the imx8mn.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree. This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot. Fix this by adding the spba node to the spl
device tree to restore normal booting.
Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.
Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
When the imx8mn.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree. This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot. Fix this by adding the spba node to the spl
device tree to restore normal booting.
Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.
Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Provide a way to copy over the 'other' FDT when running tests. This loads
it and allocates memory for the copy, if not done already, then does the
copy.
Avoid using U-Boot's malloc() pool for these copies, at least for now,
since they are part of the test system.
Tidy up the cpu.c header files while here.
Signed-off-by: Simon Glass <sjg@chromium.org>
We need an 'other' FDT which is different from the control FDT, so we can
check that the ofnode tests correctly handle them both.
Add this to the build along with a way to read it into the sandbox state.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this implementation is specific to loading the test FDT. We
plan to load others, so create a generic function to handle this.
The path is now limited to 256 characters, to simplify the code.
When there is an empty argv[0] (which should not happen), the function now
just uses the path as is, with no prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is helpful to test that out-of-memory checks work correctly in code
that calls malloc().
Add a simple way to force failure after a given number of malloc() calls.
Fix a header guard to avoid a build error on sandbox_vpl.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
This is not needed and we should avoid typedefs. Use the struct instead
and rename it to indicate that it really is a legacy struct.
Signed-off-by: Simon Glass <sjg@chromium.org>
- SPL fixes for STM32F7 MCUs
- Device tree alignement with kernelv6.0-rc4 for MCU's board
- Device tree alignement with kernelv6.0-rc3 for MPU's board
- Update DDR node for STM32MP15
- Cleanup config file for STM32MP1
- Update for cmd_stm32key command
- Fix compatible string to add partitions for STM32MP1
- Update for stm32programmer tool
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmMy5KMcHHBhdHJpY2Uu
Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/phGoEACO/DdR5qrZcWYZhK8t
4ZhCYW3+anI7hx/aOx2k36JIw8V7kTCivBszTXtvEFLoPARKSt2RCGKRrSciyPw8
e5HaX85fvOum1+p555LzGBerleezz3dMIE6PgjuWHQgznVh5jaJPvu5SacOoU2yt
RCQbrBUqMxZ9HPFWOWsmqBo5rIskgn0fhkSDaqj+v0yqnj/HLZk5NtAy4q3KYxA1
yL4rHB5+SM7ENh1KsPJm+8M5FTjBmVBZKp17mcu/3z3RwNNCjEVG0aXw8Im7pzb8
b0pwnOqxRMBsBNOqnZ6kmNdKeOBZVfh35dBXplUxfMG6VYWwrNUTAgLnwPIFbFWX
qaMiyRdAK5KArOCWFzbJN8oqCrM7hrTnlpmK9ilILJ81VuN/JDvFmLle31DrOxm6
XzVh8GOp+cjEmJckcm8ChAUGB/Q1ToTZd6TMXN69IzcmE0t0rW/j+muILVeq+rT5
JmWz+5av9W1nKRVP9WzfjOVASNdNgNRQMYAn8jJwUU/oiEw6QIZUP4m5rngSNMzQ
f3Jzl+zO7QfFtT4NHir1HNguJRnZxuzxBc3Ok639UwzMJQwHuy6LPJnAlKLUoYuE
LYkplLn7UA8aSbiWJq04fws0xrTYMvK1VWZp5CFgsnsc2usLy4Sks9JIwyqmAxme
dF0ut2NYT3o8Ctn9ppezA+sx2w==
=iA80
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20220927' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
- Device tree alignement with kernelv6.0-rc4 for MCU's board
- Device tree alignement with kernelv6.0-rc3 for MPU's board
- Update DDR node for STM32MP15
- Cleanup config file for STM32MP1
- Update for cmd_stm32key command
- Fix compatible string to add partitions for STM32MP1
- Update for stm32programmer tool
xilinx:
- Add support for new Versal NET SOC
zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio
versal:
- Config cleanup
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYzGwogAKCRDKSWXLKUoM
Ial4AJ9+4WHn0MV2X7gK1fyh4lUW7ggPhQCggsYlSoACgMgdji17SAPhCv/W3IA=
=BmA9
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
- Add support for new Versal NET SOC
zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio
versal:
- Config cleanup
Device tree alignment with kernel v6.0-rc4.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar to Versal but it will
likely diverge in longer run.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
In SMP all harts will register themself in available_hart
during start up. Then main hart will send IPI to other harts
according to this variables. But this mechanism may not
guarantee that all other harts can jump to next stage.
When main hart is sending IPI to other hart according to
available_harts, but other harts maybe still not finish the
registration. Then the SMP booting will miss some harts finally.
So let it become an option and it will be enabled by default.
Please refer to the discussion:
https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.
In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.
The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.
This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Add a simple uclass test for SCSI. It reads the partition table from a
disk image and checks that it looks correct.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present sandbox is producing a warning about SCSI migration. Drop the
legacy code and replace it with a new implementation.
Also drop the SATA command, which does not work with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
The following faulty behavior was observed. The sandbox configured with
CONFIG_SANDBOX_CRASH_RESET=y was invoked with
./u-boot -T -S
After executing `exception undefined' the sandbox reboots.
When executing `exception undefined' the sandbox exits with SIGSEGV.
The expected behavior is that the sandbox should reboot again.
If we are relaunching the sandbox in a signal handler, we have to unblock
the respective signal before calling execv(). See signal(7) man-page.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
During init_dram() is called also setup_ddr_tlbs_phys() function which may
print message about unmapped DDR memory. So in this case print also
re-aligning filler after unmapped DDR memory message.
Signed-off-by: Pali Rohár <pali@kernel.org>
Currently U-Boot SPL prints just generic message "2 GiB left unmapped".
Change it to more detailed "2 GiB of DDR memory left unmapped in U-Boot".
This is just U-Boot configuration and operating system may map more (or
also less) memory.
Signed-off-by: Pali Rohár <pali@kernel.org>
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.
So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.
Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
