The content dm_ofnode_pre_reloc() is identical with ofnode_pre_reloc()
defined in drivers/core/ofnode.c and used only three times:
- drivers/core/lists.c:lists_bind_fdt()
- drivers/clk/at91/pmc.c::at91_clk_sub_device_bind
- drivers/clk/altera/clk-arria10.c::socfpga_a10_clk_bind
So this function dm_ofnode_pre_reloc can be removed and replaced
by these function calls by ofnode_pre_reloc().
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp
specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT
introduced by the commit 535d76a121 ("armv8: layerscape: Add TFABOOT
support").
This config CONFIG_TFABOOT is activated for the trusted boot chain,
when U-Boot is loaded by TF-A.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Pull in changes that have been pending in our 'next' branch. This
includes:
- A large number of CI improvements including moving to gcc-9.2 for all
platforms.
- amlogic, xilinx, stm32, TI SoC updates
- USB and i2c subsystem updtaes
- Re-sync Kbuild/etc logic with v4.19 of the Linux kernel.
- RSA key handling improvements
- sync all Amlogic DT from Linux v5.6-rc2
- MMC clock fixups
- add support for Libre Computer AML-S905D-PC and AML-S912-PC
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Merge tag 'u-boot-amlogic-20200406' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic into next
- clk: meson-g12a: missing break
- sync all Amlogic DT from Linux v5.6-rc2
- MMC clock fixups
- add support for Libre Computer AML-S905D-PC and AML-S912-PC
On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit (82de42fa14) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.
But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.
So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add clock support for SPI5, as this instance is available on extension
connector of ST board.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Correct three masks used to access on the RCC register
RCC_QSPICKSELR, RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
If all branches of a switch statement have a return instruction, all
subsequent lines are unreachable.
Identified with cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling versal_pm_clock_get_name() in versal_get_clock_info() function.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
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Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree.
This patch solves the warnings when compiling with W=1
on stm32mp1 board:
clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’:
clk_stm32mp1.c:1238:15: warning: comparison of integer expressions
of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
[-Wsign-compare]
clk_stm32mp1.c:1239:13: warning: comparison of integer expressions
of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
[-Wsign-compare]
clk_stm32mp1.c: In function ‘stm32mp1_clktree’:
clk_stm32mp1.c:1814:17: warning: comparison of integer expressions
of different signedness: ‘int’ and ‘unsigned int’
[-Wsign-compare]
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
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Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.
This driver can be expanded later as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodes
K3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA support
DRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/ti
AM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
Add slack to the clock frequency parameters passed to firmware within
clk_set_rate. min-freq is changed to 0 and max-rate is changed to
ULONG_MAX. This fixes certain issues with pll clock rounding when the
firmware is not able to set the frequency exactly to the target, the
current implementation fails if the available frequency is even 1Hz off
the target. With the change, the firmware still tries its best to set
the frequency as close as possible to the target.
Reported-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This function related to timer and most of the timer functions are in
time.h, so move this function there.
Signed-off-by: Simon Glass <sjg@chromium.org>
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This is used to avoid clk_enable() return -ENOSYS.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Sometimes we may need get (optional) clock without a device,
that means use ofnode.
e.g. when the phy node has subnode, and there is no device created
for subnode, in this case, we need these new APIs to get subnode's
clock.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Add valid check for clk->dev, it's useful when get optional
clock even when the clk point is valid, but its dev will be
NULL.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
If skip all return error number, it may skip some real error cases,
so only skip the error when the clock is not provided in DTS
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
The SSUSB IP's clocks come from ssusbsys module on mt7629,
so add its driver
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
div_mask is different for GENERIC and USB pll, so set it according.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
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Merge tag 'efi-2020-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:
When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().
The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:
- The power-on-reset value of SCCR[PCICM] is 0, so
mpc83xx_clk_enable() would probably need to be tought to enable the
clock.
- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
depending on the CFG_CLKIN_DIV configuration input, but that can't
be read from software, so to properly fill out
->speed[MPC83XX_CLK_PCI] I think one would need guidance from
Kconfig or dtb.
Partially fixes: 07d538d281 clk: Add MPC83xx clock driver
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.
However in this case it causes a problem, something like this:
- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
- first sets up ofdata (which does nothing at present)
- DM marks clock device as active
- DM calls pinctrl
- pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
- ast_get_scu() probes the clock, but sees it already marked as
probed
- ast_get_scu() accesses the clock's private data, with scu as NULL
- DM calls clock probe function ast2500_clk_probe() which reads scu
By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.
Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.
agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-----------------
- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
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Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2020.01
-----------------
- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
The 24MHz oscillator clock is referenced by "clock-osc-24m" and not
"osc_24m".
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.
Use the vsprintf.h include file explicitly where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add clk controller driver for RK3308 SOC.
This patch depends on Elaine's pll patch[0].
[0]http://patchwork.ozlabs.org/patch/1183718/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so
without the leading CONFIG_. The clock drivers all wrongly check for
CONFIG_RESET_ROCKCHIP, fix that
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.
So we can get rid of the open-coded reset init and just fix
the correct cru reference.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
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Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add set_parent callback, then assigned-clock-parents in dts could
be work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Add enet ref/timer/PHY_REF/root clk which are required to make enet
function well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Add i.MX8MM ccf driver support.
Modifed from Linux Kernel 5.3.0-rc1, drop some entries
that not used in U-Boot and adapt to U-Boot CCF style.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Lukasz Majewski <lukma@denx.de>
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
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Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Make sure that the clock self-assignment works by having a clock of
clk-sbox be configured automatically when clk-sbox is probed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.
example:
muxed_clock: muxed_clock {
clocks = <&clk_provider 0>, <&clk_provider 1>;
#clock-cells = <0>;
assigned-clocks = <&muxed_clock>;
assigned-clock-parents = <&clk_provider 1>;
};
It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a few more clocks the clk_sandbox clock provider and get them using
the managed API.
Make sure they are released when the device is removed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This change adds support for I2C clock modeled in CCF. This code intention
is to only enable those clocks in the I2C driver with default settings.
For that reason the "busy" versions of clocks reuse the generic approach
and would need to be updated when one wants to adjust the I2C clock
frequency in U-Boot.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The SM1 clock controller is almost identical to the G12A and
so far the differences don't matter.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add necessary clock support to set up clock for the VPU and
HDMI support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add simple ZynqMP firmware drive to populate child nodes under
zynqmp_firmware DT node.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The G12B clock controller is almost identical to the G12A and
so far the differences don't matter. Adding the G12B compatible
makes USB work on the Odroid-N2.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Use existing gd structure to store frequency information
which can be used in drivers or arch without new request.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Several options are presenting themselves on a various boards
where the options are clearly not used. (ie, SPL/TPL options
when SPL or TPL are not defined)
This patch is not attempting to be a complete list of items, but
more like low hanging fruit. In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.
This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: Adam Ford <aford173@gmail.com>
- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver
Since we added clk enable_count and prograte clk child enabling
operation to clk parent, so add a new function sandbox_clk_enable_count
to get enable_count for test usage.
And add test code to get the enable_count after we enable/disable
the device clk.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX8MM, thinking such as clk path
OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device
Only enabling CCGR GATE is not enough, we also need to enable PLL GATE
to make sure the clk path work. So when enabling CCGR GATE,
we could prograte to enabling PLL GATE to make life easier.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
As what Linux Kernel 5.3.0 provides when enable/disable clk,
there is an enable_count in clk_core_disable/enable. Introduce
enable_count to track the clk enable/disable count when
clk_enable/disable for CCF. And Initialize enable_count to 0 when
register the clk.
And clk tree dump with enable_count will be supported, it will
be easy for us to check the clk status with enable_count
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for clk_is_match() which is required to
know if two clock pointers point to the same exact
physical clock.
Also add a unit test for the new API.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.
The control block is shared with ethsys and accordingly rename the
related defines.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
First thing we check in meson_clk_set_rate_by_id() is current_rate == rate.
There is not need to check it again.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When the device not binded with a node, we need ignore
the parents and rate settings.
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_uclass_priv to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
- Clean up and migrate to use common rockchip spl board file
- Clean up and migrate to use common rockchip board file
- Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
Init CPU frquency in clock driver instead of in SPL board file,
this will help for use common board file later.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Right now when using clk_of_xlate_default(), clk->data
remains un-initialized because clk_get_bulk() does not
initialize memory on allocation of clock structure.
This can cause problems when data is used to match if
two clocks pointers are exactly the same underlying
clocks, for example.
Fix it by initializing clk->data to 0.
Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add RTCAPB and RTC clock support.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- rk3399 lpddr4 support
- rk3399-rock960 board support improvement
- Eliminate pyelftools dependency by make_fit_atf.py
- clean up rockchip dts to use -u-boot.dtsi
- use ARM arch/generic timer instead of rk_timer
- clean up Kconfig options for board support
Add support for setting 400MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add support for setting 50MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.
In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.
Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The generic mux clock code for CCF requires reading the clock multiplexer
value from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.
The new field in the mux structure (accessible only when sandbox is run)
has been introduced for this purpose.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.
The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate()
provides recalculated clock value without considering the cache setting.
This may be necessary for some clocks tightly coupled with power domains
(i.e. imx8), and prevents from reading invalid cached values.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y
SHA1: 5752b50477da)to provide clocks support as it is used on the Linux
kernel with Common Clock Framework [CCF] setup.
The directory structure has been preserved. The ported code only supports
reading information from PLL, MUX, Divider, etc and enabling/disabling
the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic
to the alias numbering as the information about the clock is read from the
device tree.
One needs to pay attention to the comments indicating necessary for U-Boot's
driver model changes.
If needed, the code can be extended to support the "set" part of the clock
management.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit adds the clk_get_by_id() function, which is responsible
for getting the udevice with matching clk->id. Such approach allows
re-usage of inherit DM list relationship for the same class (UCLASS_CLK).
As a result - we don't need any other external list - it is just enough
to look for UCLASS_CLK related udevices.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit adds the clk_get_parent_rate() function, which is responsible
for getting the rate of parent clock.
Unfortunately, u-boot's DM support for getting parent is different
(the parent relationship is in udevice) than the one in Common Clock
Framework [CCF] in Linux.
To alleviate this problem - the clk_get_parent_rate() function has been
introduced to clk-uclass.c.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit adds the clk_get_parent() function, which is responsible
for getting the parent's struct clock pointer.
U-Boot's DM support for getting parent is different (the parent
relationship is in udevice) than the one in Common Clock Framework [CCF]
in Linux. To obtain the pointer to struct clk of parent the
pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK
without declaring struct clk. As a result it was only accessible by
iterating the udevice's uclass list.
This is a problem for clock code, which operates on pointers to struct
clk (like clk_get_rate()), not udevices.
After this change struct clk is accessible from udevice and udevice from
struct clk.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This check requires the struct clk passed to .get_rate() to be always
cleared out as any clock with valid ID causes -EINVAL return value.
The return code of fixed clocks shall always be returned.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The DT bindings of SiFive clock driver in upstream Linux has
changes. As-per latest DT bindings, the clock driver takes two
parent clocks and compatible string has also changed.
This patch sync-up SiFive clock driver implementation as-per
upstream Linux so that we now use latest DT bindings.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements
Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
The "simple" OF glue layer for the Designware USB3 core enables
all refernced clocks. These need to be need to be implemented
otherwise the driver fails to probe. A dummy implementation
that simply returns success is sufficient since the RK3399 comes
out of reset with all clock gates open.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This patch solves the following warnings:
drivers/clk/clk_stm32mp1.c: In function 'stm32mp1_clk_get_parent':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
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Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot
- Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
Trying to bring up uSDHC2 the following error message was observed:
MMC: imx8_clk_set_rate(Invalid clk ID #60)
imx8_clk_set_rate(Invalid clk ID #60)
usdhc@5b030000 - probe failed: -22
This commit fixes this by properly setting resp. clocks.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
ETHCK_K is the identifier the kernel clock for ETH in kernel
binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7).
U-Boot driver need to use the same identifier, so change ETHCK
to ETHCK_K.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
This adds a clock driver to support the GEMGXL management IP block
found in FU540 SoCs to control GEM TX clock operation mode for
10/100/1000 Mbps.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
- some fix for rk3399-puma;
- rockchip script make_fit_atf.py cleanup
- Enable TPL for rk3399 orangepi and nanopi4;
- add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed
for USB to operate, add basic support for it and associated gates.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This patch adds the rate for UART1 and UART3 the same way
as already implemented for UART0 and UART2.
This is required for boards, which have their console output
on these UARTs.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some DM drivers have hardcoded clk_enable calls when handling
clocks (for example the fsl_esdhc driver).
To work with these drivers, add an enable method to the MCP83xx clock
driver (which does nothing, because the clocks are always enabled).
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
clk_get_by_index_tail() now handle common clk get by index
code so use it from clk_get_by_indexed_prop().
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.
So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.
In these scenarios with current order of include files
the fu540-prci driver is unable to find CONFIG_ENV_SIZE.
In file included from arch/riscv/include/asm/u-boot.h:23:0,
from include/dm/of.h:10,
from include/dm/ofnode.h:12,
from include/clk.h:11,
from include/clk-uclass.h:13,
from drivers/clk/sifive/fu540-prci.c:32:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
So, fix consists of changing the order of include files
in fu540-prci.c to include first common.h file.
Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
Porting to DM and i.MX8
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To make it easy to add new clk driver for i.MX8, split
the code into common part and SoC specific part.
Make the get/set/enable non static and introduce a num_clks for
soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to support the Amlogic G12A clock controller,
re-architect the clock files into a meson directory.
No functionnal changes.
MAINTAINERS entry is also updated.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C
support because requesting the clock for the I2C ip-block isn't
supported during SPL.
To fixup this we add support requesting clocks for:
- i2c0
- i2c1
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
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Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm
fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32
The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power
The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The $div and $mul values were swapped in the debug output,
fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux
Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of clk dump command and
display information during probe (under CONFIG_DISPLAY_CPUINFO).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Because stgen is initialized with HSI clock, we need to
recalculate the counter when changing frequency.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove support of ck_usbo_48m clock node in device tree,
but force 48MHz frequency to prepare alignment
with kernel device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
These clocks are needed to get MMC running. We don't actually support
setting them yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.
Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.
Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the
MMC driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add initial clock driver for Allwinner A80.
- Implement UART bus clocks via ccu_clk_gate table for
A80, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Add initial clock driver for Allwinner V3S.
- Implement USB bus and USB clocks via ccu_clk_gate table
for V3S, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for V3S, so it can accessed in common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner R40.
- Implement USB bus and USB clocks via ccu_clk_gate
for R40, so it can accessed in common clk enable
and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for R40, so it can accessed in common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A83T.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A83T, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A83T, so it can accessed in common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A23/A33.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A23/A33, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A23/A33, so it can accessed in common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A31.
- Implement USB ahb1 and USB clocks via ccu_clk_gate table
for A31, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
for A31, so it can accessed in common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A10s/A13.
- Implement USB ahb and USB clocks via ccu_clk_gate table
for A10s/A13, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A10/A20.
- Implement USB ahb and USB clocks via ccu_clk_gate table
for A10/A20, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner H3/H5.
- Implement USB bus and USB clocks via ccu_clk_gate table for
H3/H5, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
H3/H5, so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add common reset driver for all Allwinner SoC's.
Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.
Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
The ethsys contains not only the clock gating controller, but also the
reset controller for the whole ethernet subsystem and its components.
This patch adds binding of the reset controller so that the ethernet node
can have references on it.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
When build clk driver in spl, met the warning:
"
drivers/clk/imx/clk-imx8.c:21:25: warning: ‘imx8_clk_names’ defined but not used [-Wunused-variable]
static struct imx8_clks imx8_clk_names[] = {
^~~~~~~~~~~~~~
"
Fix with wrapping the array with CONFIG_CMD_CLK.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The Denali NAND controller IP needs three clocks:
- clk: controller core clock
- clk_x: bus interface clock
- ecc_clk: clock at which ECC circuitry is run
Currently, only the first one (50MHz) is provided. The rest of the
two clock ports must be connected to the 200MHz clock line. Add this.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add hardware spinlock in the list of the clocks.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
