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25176 commits

Author SHA1 Message Date
Marek Vasut
68e0d92d33 arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT
In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3
carrier board, the on-SoM PHY PHYAD1 signal has been pulled high
by the carrier board and changed the PHY MDIO address from 5 to 7.
This has been fixed on production rev.200 SoM by additional buffer
on the SoM PHYAD/LED signals, remove the workaround.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 16:25:10 +02:00
Marek Vasut
9de599ec3d arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200
The current imx8mp-dhcom-som.dtsi describes prototype rev.100 SoM,
update the DT to describe production rev.200 SoM which brings the
following changes:
- Fast SoC GPIOs exposed on the SoM edge connector
- Slow GPIOs like component resets moved to I2C GPIO expander
- ADC upgraded from TLA2024 to ADS1015 with conversion interrupt
- EEPROM size increased from 256 B to 4 kiB

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 16:25:10 +02:00
Marek Vasut
ad1158c50e arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM
Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100
population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3
carrier boards.

Use SPL DTO support to apply matching SoM specific DTO to cater
for the SoM differences. Remove ad-hoc patching of control DT from
fdtdec_board_setup().

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 16:25:10 +02:00
Marek Vasut
b0296e22cb imx: hab: Use size parameter
The current code works by sheer coincidence, because (see HABv4 API
documentation, section 3.4) the RVT authenticate_image call updates
the size that is passed in with the actual size ROM code pulls from
IVT/CSF . So if the input size is larger, that is "fine" . Pass in
size instead to make this really correct.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 16:25:09 +02:00
Tom Rini
3616218b5a cmd: Convert existing long help messages to the new macro
- Generally we just drop the #ifdef CONFIG_SYS_LONGHELP and endif lines
  and use U_BOOT_LONGHELP to declare the same variable name as before
- In a few places, either rename the variable to follow convention or
  introduce the variable as it was being done inline before.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-16 10:24:58 -04:00
Paul Barker
21e4ba153f gpio: Add RZ/G2L GPIO driver
This driver adds support for the gpio features of the GPIO/PFC module in
the Renesas RZ/G2L (R9A07G044) SoC.

The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as
the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both
GPIO and pin multiplexing features.

This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Paul Barker
b378c400e0 pinctrl: renesas: Add RZ/G2L PFC driver
This driver adds support for the pinctrl features of the GPIO/PFC module
in the Renesas RZ/G2L (R9A07G044) SoC.

A multi-function `rzg2l-pfc` driver is defined for UCLASS_NOP, which
binds the `rzg2l-pfc-pinctrl` UCLASS_PINCTRL driver dynamically. We also
define common macros and functions for the PFC in <renesas/rzg2l-pfc.h>.
This makes it easy to add an additional UCLASS_GPIO driver for the GPIO
functionality of this module in a follow-up patch.

This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Paul Barker
959fc0bd72 arm: rmobile: Restrict PINCTRL_PFC selection to R-Car gen3/gen4
The RZ/G2L family uses CONFIG_RCAR_64 but does not share a common PFC
driver with the R-Car gen3 & gen4 boards.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Paul Barker
1918ff5c95 clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:

* driver code which is applicable to all SoCs in the RZ/G2L family.

* static data describing the clocks and resets which are specific to the
  R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
  is used to indicate that both SoCs are supported.

clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.

The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.

This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Paul Barker
a4b3e08652 arm: rmobile: Add basic R9A07G044L SoC support
Add a config option for the R9A07G044L SoC used in the RZ/G2L so that we
can make use of this in the subsequent driver patches.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Paul Barker
387d4275ab arm: rmobile: Add basic RZ/G2L family support
The Renesas RZ/G2L family includes the following ARM SoCs:

* RZ/G2L  (r9a07g044l)
* RZ/G2LC (r9a07g044c)
* RZ/G2UL (r9a07g043u)
* RZ/V2L  (r9a07g054l)

Support for individual SoCs and evaluation boards will be added in
separate patches.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Tom Rini
2e1577e836 - add Amlogic A1 clock driver
- add Amlogic A1 reset support
 - add USB Device support for Amlogic A1
 - enable RNG on Amlogic A1 & Amlogic S4
 - move Amlogic Secure Monitor to standalone driver
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Merge tag 'u-boot-amlogic-20231015' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- add Amlogic A1 clock driver
- add Amlogic A1 reset support
- add USB Device support for Amlogic A1
- enable RNG on Amlogic A1 & Amlogic S4
- move Amlogic Secure Monitor to standalone driver
2023-10-16 09:09:54 -04:00
Alice Guo
30e5b403d7 arm: dts: imx93: add a per clock for LPUART1
When CLK is enabled, get_lpuart_clk_rate() needs to get a per clock of
lpuart, so that add a per clock for lpuart1.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2023-10-16 14:02:38 +02:00
Marek Vasut
6bd39dee63 ARM: dts: imx: Switch USB1 port control to GPIO on Data Modul i.MX8M Plus eDM SBC
The USB_PWR signal operation is not reliable on this DWC3 controller
instance in case the signal is active high. Switch to GPIO control,
which always behaves correctly. Perform the change in u-boot extras
until this hits Linux upstream.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 14:02:38 +02:00
Chris Packham
10c937fa23 Revert "arm: mvebu: x240: Use i2c-gpio instead of built in controller"
This reverts commit 5c1c6b7306. The reason
for switching to i2c-gpio was due to an issue we were seeing in the
Linux kernel where the CPU would lock up on certain adverse I2C bus
conditions. We were never able to reproduce the lockup in U-Boot but
assumed that was probably just luck.

Since then we have discovered that the lock up was due to the I2C
transaction offload engine in the I2C controller not coping with the
adverse bus conditions (basically it thinks there's another master and
waits for a STOP condition that never comes). U-Boot doesn't use the I2C
offload feature so is not susceptible to the lockup.

We can therefore safely return to using the built-in I2C controller.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16 14:00:45 +02:00
Tony Dinh
b3f559a147 arm: kirkwood: Add support for ZyXEL NSA325 board
ZyXEL NSA325 specifications:

Marvell Kirkwood 88F6282 SoC
1.6 GHz CPU
1x GBE LAN port (Marvell MV88E1318)
512 MB RAM
128 MB Eon NAND, SLC
I2C
1x USB 3.0 (on PCIe bus)
2x USB 2.0
2x SATA (hot swap slots)
Serial console

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16 11:10:42 +02:00
Chris Packham
4df539c0c5 ARM64: dts: marvell: cn9310-crb: Remove duplicate pinctrl
The cn9130.dtsi defines a pinctrl node for SPI1 (until recently it was
mislabeled as spi0). Use this instead of having a duplicate definition
with a different label.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16 11:10:32 +02:00
Chris Packham
6b8efc66ea ARM64: dts: marvell: cn9310: Use appropriate label for spi1 pins
The CN9130-DB uses the SPI1 interface but had the pinctrl node labelled
as "cp0_spi0_pins". Use the label "cp0_spi1_pins" and update the node
name to "cp0-spi-pins-1" to avoid confusion with the pinctrl options for
SPI0.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-16 11:10:32 +02:00
Hiago De Franco
7dede4033b arm: mach-imx: Makefile: Extend u-boot-nand.imx padding
Extend the padding process of u-boot-nand.imx target by adding 10k bytes
of zeros to the end of the binary using the 'dd' command.

The existing padding method did not generate a functional binary,
as discussed in more detail in this thread [1]. Instead, we adopt the
end-padding calculation method documented in 'board/doc/colibri_imx7.rst'
as a reference, which is relevant for iMX7 with NAND storage.

Adding 10k bytes of zeros provides an approximate value that makes the
proper padding for these NAND devices.

[1] https://lore.kernel.org/all/CAC4tdFUqffQzRQFv5AGe_xtbFy1agr2SEpn_FzEdexhwjdryyw@mail.gmail.com/

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-10-16 08:46:01 +02:00
Rasmus Villemoes
3c3976ff2b imx: spl_imx_romapi.c: remove dead code
These IS_ENABLED(CONFIG_SPL_LOAD_FIT) cases can no longer be reached,
and thus get_fit_image_size() is also redundant.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-10-16 08:46:01 +02:00
Rasmus Villemoes
4b4472438f imx: spl_imx_romapi: avoid tricky use of spl_load_simple_fit() to get full FIT size
Currently, spl_imx_romapi uses a somewhat tricky workaround for the
fact that a FIT image with external data doesn't directly allow one to
know the full size of the file: It does a dummy spl_load_simple_fit(),
having the ->read callback remember the largest offset requested, and
then does a last call to rom_api_download_image() to fetch the
remaining part of the full FIT image.

We can avoid that by just keeping track of how much we have downloaded
already, and if the ->read() requests something outside the current
valid buffer, fetch up to the end of the current request.

The current method also suffers from not working when CONFIG_IMX_HAB
is enabled: While in that case u-boot.itb is not built with external
data, so the fdt header does contain the full size of the dtb
structure. However, it does not account for the extra CONFIG_CSF_SIZE
added by board_spl_fit_size_align(). And also, the data it hands out
during the first dummy spl_load_simple_fit() is of course garbage, and
wouldn't pass the verification.

So we really need to call spl_load_simple_fit() only once, let that
figure out just how big the FIT image is (including whatever data, CSF
or "ordinary" external data, has been tacked on beyond the fdt
structure), and always provide valid data from the ->read callback.

This only affects the CONFIG_SPL_LOAD_FIT case - I don't have any
hardware or experience with the CONFIG_SPL_LOAD_IMX_CONTAINER case, so
I leave that alone for now.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-10-16 08:46:01 +02:00
Rasmus Villemoes
9960d4a540 imx8mp: binman: rename spl and u-boot nodes
The hab signing script doc/imx/habv4/csf_examples/mx8m/csf.sh does

  fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset

to figure out the offset of u-boot.itb inside flash.bin. That works
fine for imx8mm, imx8mn, imx8mq, but fails for imx8mp because in that
case 'uboot' is merely a label and not actually the node name.

Homogenize these cases and make imx8mp the same as the other imx8m*
variants. The binman type is explicitly given and no longer derived
from the node name, and the csf.sh script will work for all four SOCs.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-10-16 08:46:01 +02:00
Tim Harvey
ae56026783 arm: imx: imx8m: add optee configuration to ft_system_setup
If optee is detected configure it in the Linux device-tree:
 - add /firmware/optee node
 - add /reserved-memory nodes for optee_core and optee_shm

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-10-16 08:46:01 +02:00
Tim Harvey
93cac45c97 arm: dts: imx8m: move CAAM nodes into common u-boot.dtsi
Move the crypto and sec_jr* nodes from board-specific
u-boot.dtsi files into the common files. Additionally protect the
nodes with ifdef CONFIG_FSL_CAAM as they don't serve any purpose if
that is not enabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-10-16 08:46:01 +02:00
Tim Harvey
c0887faade arm: dts: imx8mn: protect the firmware/optee node with ifdef
There is no need to include the firmware/optee node if the optee
driver is not enabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-10-16 08:46:01 +02:00
Tim Harvey
93aa9699fc arm: dts: imx8mp: move firmware/optee node to common imx8mp-u-boot.dtsi
Move the firmware/optee node to the common imx8mp-u-boot.dtsi and
protect it with an ifdef CONFIG_OPTEE as it is a meaningless node
without the optee driver enabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-10-16 08:46:01 +02:00
Tim Harvey
bb6a4c5536 arm: dts: imx8mm: move firmware/optee node to common imx8mm-u-boot.dtsi
Move the firmware/optee node to the common imx8mm-u-boot.dtsi and
protect it with an ifdef CONFIG_OPTEE as it is a meaningless node
without the optee driver enabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-10-16 08:46:01 +02:00
Marcel Ziswiler
d0dd76f3eb board: toradex: verdin-imx8mm: enable usb sdp spl recovery support
Enable USB SDP SPL aka serial downloader recovery mode support.

While at it also enable fastboot support which may be used to
subsequently load further stages like a Toradex Easy Installer FIT
image.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-10-16 08:46:01 +02:00
Tim Harvey
7db3404e0f board: gateworks: venice: updates for imx8mp-venice-gw74xx revB PCB
Update the imx8mp-venice-gw74xx for revB:
 - add CAN1
 - add TIS-TPM on SPI2
 - add FAN controller
 - fix PMIC I2C bus (revA PMIC I2C was non-functional so no need for
   backward compatible option)
 - M2 socket GPIO's moved

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-10-16 08:46:01 +02:00
Tim Harvey
52346fcb90 board: gateworks: venice: add imx8mm-gw7905-0x support
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard.

The GW700x SOM contains the following:
 - i.MX8M Mini SoC
 - LPDDR4 memory
 - eMMC Boot device
 - Gateworks System Controller (GSC) with integrated EEPROM, button
   controller, and ADC's
 - RGMII PHY
 - PMIC
 - SOM connector providing:
  - FEC GbE MII
  - 1x SPI
  - 2x I2C
  - 4x UART
  - 2x USB 2.0
  - 1x PCI
  - 1x SDIO (4-bit 3.3V)
  - 1x SDIO (4-bit 3.3V/1.8V)
  - GPIO

The GW7905 Baseboard contains the following:
 - GPS
 - microSD
 - off-board I/O connector with I2C, SPI, GPIO
 - EERPOM
 - PCIe clock generator
 - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
 - 1x half-length miniPCIe socket with USB2.0 and USB3.0
 - USB 3.0 HUB
 - USB Type-C with USB PD Sink capability and peripheral support
 - USB Type-C with USB 3.0 host support

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-10-16 08:46:01 +02:00
Tim Harvey
8aa5e6973c board: gateworks: venice: add imx8mp-gw73xx-2x support
The Gateworks imx8mp-venice-gw73xx-2x consists of a SOM + baseboard.

The GW702x SOM contains the following:
 - i.MX8M Plus SoC
 - LPDDR4 memory
 - eMMC Boot device
 - Gateworks System Controller (GSC) with integrated EEPROM, button
   controller, and ADC's
 - PMIC
 - SOM connector providing:
  - eQoS GbE MII
  - 1x SPI
  - 2x I2C
  - 4x UART
  - 2x USB 3.0
  - 1x PCI
  - 1x SDIO (4-bit 3.3V)
  - 1x SDIO (4-bit 3.3V/1.8V)
  - GPIO

The GW73xx Baseboard contains the following:
 - 1x RJ45 GbE (eQoS from SOM)
 - 1x RJ45 GbE (PCI)
 - off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
 - off-board I/O connector with RS232/RS485
 - off-board I/O connector with SPI
 - off-board I/O connector with I2C, UART, and GPIO
   I2C, I2S and GPIO
 - microSD (1.8V/3.3V)
 - GPS
 - Accelerometer
 - EERPOM
 - USB 3.0 Hub
 - Front Panel bi-color LED
 - re-chargeable battery (for RTC)
 - PCIe clock generator
 - PCIe switch
 - on-board 802.11abgnac 1x1 WiFi and Bluetooth 5.2
 - 1x USB Type-A host socket with USB 3.0 support
 - 1x USB OTG with USB 2.0 support
 - 2x MiniPCIe socket with PCI and USB 2.0
 - 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
 - Wide range DC input supply

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-10-16 08:46:01 +02:00
Tim Harvey
e55422a113 board: gateworks: venice: add imx8mp-gw72xx-2x support
The Gateworks imx8mp-venice-gw72xx-2x consists of a SOM + baseboard.

The GW702x SOM contains the following:
 - i.MX8M Plus SoC
 - LPDDR4 memory
 - eMMC Boot device
 - Gateworks System Controller (GSC) with integrated EEPROM, button
   controller, and ADC's
 - PMIC
 - SOM connector providing:
  - eQoS GbE MII
  - 1x SPI
  - 2x I2C
  - 4x UART
  - 2x USB 3.0
  - 1x PCI
  - 1x SDIO (4-bit 3.3V)
  - 1x SDIO (4-bit 3.3V/1.8V)
  - GPIO

The GW72xx Baseboard contains the following:
 - 1x RJ45 GbE (eQoS from SOM)
 - 1x RJ45 GbE (PCI)
 - off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
 - off-board I/O connector with RS232/RS485
 - off-board I/O connector with SPI
 - off-board I/O connector with I2C, UART, and GPIO
   I2C, I2S and GPIO
 - microSD (1.8V/3.3V)
 - GPS
 - Accelerometer
 - EERPOM
 - USB 3.0 Hub
 - Front Panel bi-color LED
 - re-chargeable battery (for RTC)
 - PCIe clock generator
 - PCIe switch
 - 1x USB Type-A host socket with USB 3.0 support
 - 1x USB OTG with USB 2.0 support
 - 1x MiniPCIe socket with PCI and USB 2.0
 - 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
 - Wide range DC input supply

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-10-16 08:46:01 +02:00
Tim Harvey
6db1085623 board: gateworks: venice: add imx8mp-gw71xx-2x support
The Gateworks imx8mp-venice-gw71xx-2x consists of a SOM + baseboard.

The GW702x SOM contains the following:
 - i.MX8M Plus SoC
 - LPDDR4 memory
 - eMMC Boot device
 - Gateworks System Controller (GSC) with integrated EEPROM, button
   controller, and ADC's
 - PMIC
 - SOM connector providing:
  - eQoS GbE MII
  - 1x SPI
  - 2x I2C
  - 4x UART
  - 2x USB 3.0
  - 1x PCI
  - 1x SDIO (4-bit 3.3V)
  - 1x SDIO (4-bit 3.3V/1.8V)
  - GPIO

The GW71xx Baseboard contains the following:
 - 1x RJ45 GbE (eQoS from SOM)
 - off-board I/O connector with I2C, SPI, UART, and GPIO
 - Front Panel bi-color LED
 - re-chargeable battery (for RTC)
 - PCIe clock generator
 - 1x USB Type-C connector supporting USB 2.0 host mode with VBUS
 - 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
 - GPS
 - Accelerometer
 - EERPOM
 - Wide range DC input supply

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-10-16 08:46:01 +02:00
Ricardo Salveti
004bd3ff03 arm: dts: imx6ull-14x14-evk-u-boot: add rngb
Linux microPlatform uses an rngb device in optee-os in boot scheme
SPL -> OPTEE -> U-Boot. To make rngb available for optee-os, enable
it in SPL.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-10-16 08:46:01 +02:00
Michael Scott
43b1e83a73 imx: syscounter: allow timer_init for SPL build
With enabled SKIP_LOWLEVEL_INIT, the weak function timer_init() is
used in the SPL build. For iMX6 SoC, this leads MMC to fail once
u-boot proper is booted due to a timing issue.
Always use iMX-specific timer_init() in SPL to fix timing issues.

Fixes: be277c3a89 ("imx: mx7: avoid some initialization if low level is skipped")
Signed-off-by: Michael Scott <mike@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-10-16 08:46:01 +02:00
Alexey Romanov
7cd53e0d52 arch: meson: use secure monitor driver
Now we have to use UCLASS_SM driver instead of
raw smc_call() function call.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-9-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-15 12:23:48 +02:00
Alexey Romanov
67c03a9474 arch: meson: sm: set correct order of the includes
The common.h header should always be first, followed
by other headers in order, then headers with directories,
then local files.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-8-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-15 12:23:48 +02:00
Alexey Romanov
c3be2f18dd sandbox: dts: add meson secure monitor node
We need this to test UCLASS_SM.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-4-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-15 12:23:48 +02:00
Tom Rini
3c3f162691 improvements with dev_read_addr_..._ptr()
scan all entries in multi-device boot_targets
 EFI empty-capsule support
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Merge tag 'dm-pull-13oct23' of https://source.denx.de/u-boot/custodians/u-boot-dm

improvements with dev_read_addr_..._ptr()
scan all entries in multi-device boot_targets
EFI empty-capsule support
2023-10-14 10:50:20 -04:00
AKASHI Takahiro
8c5def59e8 sandbox: remove SCMI base node definition from test.dts
SCMI base protocol is mandatory and doesn't need to be listed in a device
tree.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-10-13 16:59:24 -04:00
AKASHI Takahiro
bddcd3af9c test: dm: simplify SCMI unit test on sandbox
Adding SCMI base protocol makes it inconvenient to hold the agent instance
(udevice) locally since the agent device will be re-created per each test.
Just remove it and simplify the test flows.
The test scenario is not changed at all.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-10-13 16:59:24 -04:00
AKASHI Takahiro
a89d9f41e0 test: dm: add protocol-specific channel test
Any SCMI protocol may have its own channel.
Test this feature on sandbox as the necessary framework was added
in a prior commit.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-10-13 16:59:23 -04:00
AKASHI Takahiro
a70a897e31 firmware: scmi: support dummy channels for sandbox agent
In sandbox scmi agent, channels are not used at all. But in this patch,
dummy channels are supported in order to test protocol-specific channels.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-10-13 16:59:23 -04:00
Matthias Schiffer
5fecea171d treewide: use dev_read_addr_*_ptr() where appropriate
A follow-up to commit 842fb5de42
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").

In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.

This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-13 14:01:42 -06:00
Heinrich Schuchardt
3cce6fcea7 sandbox: fix spl_board_init
sandbox_spl_defconfig with CONFIG_SPL_UNIT_TEST=n fails to build.

    in function `spl_board_init':
    arch/sandbox/cpu/spl.c:134:(.text.spl_board_init+0x4a):
    undefined reference to `ut_run_list'

Add the missing configuration check.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-13 10:15:41 -07:00
Tom Rini
6961ca0a46 Xilinx changes for v2024.01-rc1 v3
clk:
 - remove additional compatible strings for Versal NET
 
 net:
 - zynq_gem: Fix clock calculation for MDC for higher frequencies
 
 pinctrl:
 - core: Extend pinmux status buffere size
 - zynqmp driver: Show also tristate configuration
 
 test:
 - add test case for pxe get
 
 Xilinx:
 - describe SelectMAP boot mode
 
 Zynq:
 - Fix nand description in DT
 
 ZynqMP:
 - DTS sync patches with kernel and also W=1 related fixes
 - Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
   description for other SC based boards
 - k24 psu_init cleanup
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Merge tag 'xilinx-for-v2024.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2024.01-rc1 v3

clk:
- remove additional compatible strings for Versal NET

net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies

pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration

test:
- add test case for pxe get

Xilinx:
- describe SelectMAP boot mode

Zynq:
- Fix nand description in DT

ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
  description for other SC based boards
- k24 psu_init cleanup
2023-10-13 08:45:55 -04:00
Dominik Haller
2c6e28831b arm: mach-k3: j721s2_init: Enable memory with CONFIG_K3_J721E_DDRSS
Make that condition more generic by checking if the memory controller
driver is enabled instead of using the EVM's config.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
2023-10-12 14:06:05 -04:00
Manorit Chawdhry
4dff5aa5c3 arm: dts: k3-am68: Sync from Linux tag v6.6-rc1
The following commit syncs the device tree from Linux tag
v6.6-rc1 to U-boot and fixes the following to be compatible with
the future syncs -

- Include k3-am68-sk-base-board.dts file

    Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
    include k3-am68-sk-base-board.dts for Linux fixes to propagate
    to U-boot.

- Fixing the mcu_timer0

    Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi

- Fixing secure proxy nodes

    Linux DT now have these nodes defined so remove them and rename to
    use the Linux DT ones.

- Remove cpsw node

    The compatible is now fixed and the node is not required in
    -u-boot specifically

- Remove aliases and chosen node

    Use these from Linux and don't override when not required.

- Remove /delete-property/ from sdhci nodes

    We have the necessary clock and dev data so remove these.

- Remove dummy_clocks and fs_loader0

    These weren't being used anywhere so remove it.

- Remove mcu_ringacc override

All these have been put in a single commit to not break the
bisectability.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-12 14:06:04 -04:00
Manorit Chawdhry
050f8b5df8 arm: dts: k3-j721s2: Sync from Linux tag v6.6-rc1
The following commit syncs the device tree from Linux tag
v6.6-rc1 to U-boot and fixes the following to be compatible with
the future syncs -

- Include k3-j721s2-common-proc-board.dts file

    Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
    include k3-j721s2-common-proc-board.dts for Linux fixes to propagate
    to U-boot.

- Fixing the mcu_timer0

    Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi

- Fixing secure proxy nodes

    Linux DT now have these nodes defined so remove them and rename to
    use the Linux DT ones.

- Remove cpsw node

    The compatible is now fixed and the node is not required in
    -u-boot specifically

- Remove aliases and chosen node

    Use these from Linux and don't override when not required.

- Remove /delete-property/ from sdhci nodes

    We have the necessary clock and dev data so remove these.

- Remove dummy_clocks and fs_loader0

    These weren't being used anywhere so remove it.

- Remove mcu_ringacc override

All these have been put in a single commit to not break the
bisectability.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-12 14:06:04 -04:00
Manorit Chawdhry
82d44bfbe3 arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list
mcu_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices lsit so it an be enabled via the k3 power controller.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-10-12 14:06:04 -04:00
Manorit Chawdhry
0b21d357f5 Revert "arm: dts: k3-j7*: ddr: Update to 0.10 version of DDR config tool"
The update causes instability in am68-sk boards so revert the patch in
the meantime till fix is available.

This reverts commit f1edf4bb6a.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-10-12 14:06:04 -04:00
Reid Tonking
df73e791ce arm: dts: j7200: dts sync with Linux 6.6-rc1
Sync j7200 dts with Linux 6.6-rc1

- k3-j7200-r5-common-proc-board.dts now inherits from
  k3-j7200-common-proc-board.dts instead of k3-j7200-som-p0.dtsi. This
  allows us to trim down the r5 file considerably by using existing
  properties

- remove pimux nodes from r5 file

- remove duplicate nodes & node properties from r5/u-boot files

- mcu_timer0 now used instead of timer1

  mcu_timer0 device id added to dev-data.c file in order to work

- remove cpsw node

  This node is no longer required since the compatible is now fixed

- remove dummy_clock_19_2_mhz

  This node wasn't being used anyhere, so it was removed

- remove dummy_clock_200mhz

  main_sdhci0 & main_sdhci1 no longer need dummy clock for eMMC/SD

- fix secure proxy node

  mcu_secproxy changed to used secure_prxy_mcu which is already
  defined in k3-j7200-mcu-wakeup.dtsi

- removed &mcu_ringacc property override since they're present in
  v6.6-rc1

Signed-off-by: Reid Tonking <reidt@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-10-12 14:06:04 -04:00
Reid Tonking
83eb443696 arm: mach-k3: j7200: Add mcu_timer0 id to the dev list
mcu_timer0 is now used as the tick timer in u-boot, so this adds the
timer to the soc device list so it can be enabled via the k3 power
controller.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
2023-10-12 14:06:04 -04:00
Alexey Romanov
7b4116f8f7 meson-a1: dts: add ao secure node
ao-secure node can be used to get information about the board,
so, for example, using show_board_info() we can get following
information for board with Meson A1 SoC:

SoC: Amlogic Meson A1 (A113L) Revision 2c:a (1:a)

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Link: https://lore.kernel.org/r/20231010100623.74475-3-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Alexey Romanov
87dfb37d54 meson-a1: dts: add hw rng node
Add support for hardware random number generator
of Amlogic Meson SoCs.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Link: https://lore.kernel.org/r/20231010100623.74475-2-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Igor Prusov
1fcf190e70 clk: Add clock driver for Amlogic A1
This patch adds basic clock driver for Amlogic A1 Family which supports
enabling/disabling some gates, getting frequencies and setting rate
with limited reparenting.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230925155209.130671-3-ivprusov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Simon Glass
c2bd2d33d9 expo: Update tests to include textline
Provide test coverage for the new expo object type, including building
and reading/writing settings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-11 15:43:55 -04:00
Andrew Davis
1a1d48e36a configs: Make TI_SECURE_DEVICE default for K3
All K3 boards now are secure by default, instead of setting this in each
defconfig, make it implied by the ARCH config.

The only exception is IOT2050, which I do not believe will have any
problems with being a TI_SECURE_DEVICE, but for now turn it off to keep
its config the same.

Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
2023-10-11 13:22:32 -04:00
Andre Przywara
3d5e52bd97 ARM: psci: move GIC address override to Kconfig
As the code to switch an ARM core from secure to the non-secure state
needs to know the base address of the Generic Interrupt Controller
(GIC), we read an Arm Cortex defined system register that is supposed to
hold that base address. However there are SoCs out there that get this
wrong, and this CBAR register either reads as 0 or points to the wrong
address. To accommodate those systems, so far we use a macro defined in
some platform specific header files, for affected boards.

To simplify future extensions, replace that macro with a Kconfig variable
that holds this override address, and define a default value for SoCs
that need it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
2023-10-11 13:22:32 -04:00
Rasmus Villemoes
01bf2e2eb3 sandbox: rename overlay sources to .dtso
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.

Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-11 13:22:32 -04:00
Rasmus Villemoes
e6e3a3d9fc arm64: zynqmp: rename overlay sources to .dtso
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.

Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-10-11 13:22:32 -04:00
Rasmus Villemoes
35c4bccd89 iot2050: rename overlay sources to .dtso
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.

Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-10-11 13:22:32 -04:00
Rasmus Villemoes
7efe195096 arm: dts: imx8mm-cl-iot-gate: rename overlay sources to .dtso
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.

Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-10-11 13:22:32 -04:00
Janne Grunau
0f2f5191e5 arm: apple: Add initial Apple M2 Ultra support
Apple's M2 Ultra SoC are somewhat similar to the M1 Ultra but needs
a tweaked memory map as the M2 Pro/Max SoCs.  USB, NVMe, UART, WDT
and PCIe are working with the existing drivers.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2023-10-11 13:22:32 -04:00
Andre Przywara
31565bb0aa driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
system registers, that provide 64 bits worth of randomness on every
read. Since it's an extension, and implementing it is optional, there is
a field in the ID_AA64ISAR0_EL1 ID register to query the availability
of those registers.

Add a UCLASS_RNG driver that returns entropy via repeated reads from
those system registers, if the extension is implemented.
The driver always binds, but checks the availability in the probe()
routine.

This helps systems which suffer from low boot entropy, since U-Boot can
provide entropy via the generic UEFI entropy gathering protocol to the OS,
at an early stage.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-11 13:22:32 -04:00
Marcel Ziswiler
5be1fef7f3 arm: dts: k3-am625-verdin: fix boot
A53 U-Boot proper got broken because nodes marked as 'bootph-pre-ram'
are no longer available in U-Boot proper before relocation.

Fix this by marking all nodes in u-boot.dtsi as 'bootph-all'.

Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-10-11 13:22:29 -04:00
Nishanth Menon
9214da7b93 arm: dts: k3-j721e-sk/common-proc-board: Fix boot
Since commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node
as pre-reloc after relocation") A53 u-boot proper is broken. This is
because nodes marked as 'bootph-pre-ram' are not available at u-boot
proper before relocation.

To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.

Fixes: 69b19ca67b ("arm: dts: k3-j721e: Sync with v6.6-rc1")
Cc: Neha Francis <n-francis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Tom Rini <trini@konsulko.com> # J721E-EVM GP
Tested-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
2023-10-11 13:22:27 -04:00
Andrew Davis
693886856a arm: mach-k3: Remove secure device makefile
This is now done using binman but this file was leftover and is now
unused, remove it.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-10-11 13:22:27 -04:00
Jan Kiszka
53a1eb994a arm: dts: k3-am65-iot2050: Fix boot
Since commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node
as pre-reloc after relocation") A53 u-boot proper is broken. This is
because nodes marked as 'bootph-pre-ram' are not available at u-boot
proper before relocation.

To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-10-11 13:21:54 -04:00
Tom Rini
5ae883c716 Merge tag 'fsl-qoirq-2023-10-10' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Drop legacy PPA secure FW support
support for MC reserved memory
reset the FLSHxCR1 registers for nxp_fspi
2023-10-11 10:21:33 -04:00
Laurentiu Tudor
b9112cdfb5 armv8: fsl-layerscape: make some functions static
Some functions are not used outside this file, so make them static.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-10-10 10:13:32 +08:00
Laurentiu Tudor
487fa1aa97 fsl-layerscape: drop obsolete PPA secure firmware support
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. Drop support
for it.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-10-10 10:13:32 +08:00
Matthias Schiffer
17deab0edd arm: mach-k3: common: fix compile warnings with PHYS_64BIT on 32bit
Use uintptr_t instead of phys_addr_t where appropriate, so passing the
addresses to writel() doesn't result in compile warnings when PHYS_64BIT
is set for 32bit builds (which is actually a useful configuration, as
the K3 SoC family boots from an R5 SPL, which may pass bank information
based on gd->bd->bi_dram to fdt_fixup_memory_banks() etc., so PHYS_64BIT
is needed for fixing up the upper bank).

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2023-10-09 15:24:31 -04:00
Tom Rini
4f9c7a9f54 exynos: Cleanup exynos_init
- None of the callers perform error checking and based on the non-empty
  versions of this function, there's no checking to be done, so make
  this a void.
- Add a default weak version of the function.
- Remove the empty versions of exynos_init now that we have a weak
  version.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-09 15:24:31 -04:00
Polak, Leszek
facfa5659b arm64: versal: Add SelectMAP boot mode identification
The SelectMAP configuration interface provides an 8-bit,
16-bit or 32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and readback.

A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.

This commit adds the missing identification of the SelectMAP mode.

Signed-off-by: Polak, Leszek <LPolak@arri.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/DU0PR07MB8419F7765892CDBCE7D559C5C8CFA@DU0PR07MB8419.eurprd07.prod.outlook.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-10-09 13:03:23 +02:00
Michal Simek
82bb62dfa9 arm64: xilinx: Do not use '_' in si5335 DT node names
Character '_' not recommended in node name. Use '-' instead.
Pretty much run sed below for node names.
s/si5335_/si5335-/

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ac752b1e27f02efb32608188992bb7ae50e4b1b0.1695809130.git.michal.simek@amd.com
2023-10-09 12:14:41 +02:00
Michal Simek
b311c9c40a arm64: zynqmp: Do not use '_' in DT node names
Using '_' is not recommended for node names. Use '-' instead.
Pretty much run seds below for node names.
s/heartbeat_led/heartbeat-led/
s/gtr_sel/gtr-sel/
s/zynqmp_ipi/zynqmp-ipi/
s/nvmem_firmware/nvmem-firmware/
s/soc_revision/soc-revision/

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dd33d6cb0595ffedab117d477f4a3c9d9eb11715.1695808665.git.michal.simek@amd.com
2023-10-09 12:13:36 +02:00
Michal Simek
c5cd2d2aba arm: dts: xilinx: Remove undocumented is-dual property
Xilinx was using in past is-dual property for QSPIs to reflect their
configurations. But handling for them never reached upstream code that's
why better to remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15980560b98672959a889ff9970cbe9540b4ed69.1695808563.git.michal.simek@amd.com
2023-10-09 12:13:04 +02:00
Michal Simek
b51371e8c9 arm64: zynqmp: Add support for zcu670-revB
RevB has different SD level shifter compare to revA. There are couple of
changes between revisions but none of them requires SW alignment.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0f2bb29f88615ce75f887c006060543b4aeafd48.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
1ddf10d178 arm64: zynqmp: Add support for zcu670-revA
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.

MIO configuration is also shared with zcu111.

The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b296ef0f52bd94e32bdeb6d1beee29ac85f00a2.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
eb357b75b7 arm64: zynqmp: Add support for VPXA2785
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.

The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/59d3b1f7e785bc65518b465e5122fd2787616a93.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
7f3639918f arm64: zynqmp: Describe i2c structures for SCs
Generic system controller (SC) covers connection defined by specification
but different boards have different i2c devices. That's why describe i2c
devices available on multiple boards.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ca1826b8b58981111229a94527818cc5a191ca9a.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
fa822ad19e arm64: zynqmp: Add support for SC revC
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
64f5e3b492 arm64: zynqmp: Create description for generic SC (vpk120-revB)
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.

All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.

Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).

NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).

i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8092340f92144f0cc9096194198f227015bc013.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
fe90ce2368 arm64: zynqmp: Add support for vpk120-revA
Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller. The patch is
describing only ZynqMP system controller part.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bd8b79d7c6693e90e12bce422f8ed00f2f43c9ae.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
96e98b0264 arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC
Add i2c accessible devices with description.
There is versal specific eeprom and i2c-gpio controller.

SE3 has also clock chip present.

Also remove x-prc description from SC dts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4f71ec6a63240fd4aaa3453824138281c50d71c3.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:30 +02:00
Michal Simek
46f0408771 arm64: zynqmp: Add support for vck190 revB system controller
There are some changes between revA and revB boards. u39 8T49N240 was
removed and also three ina226 at 42/43/44 addresses (u178/u180/u182).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/461cfe5b2b882365413f90d19efd8abcd6be56ed.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:29 +02:00
Michal Simek
44a56c2679 arm64: zynqmp: Remove xlnx,fclk nodes
xlnx,fclk nodes are not described in dtschema that's why remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b25dedd066f587321751d7d20c1f65bb96c53b89.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:29 +02:00
Michal Simek
7771873ab4 arm64: zynqmp: Add support for KD240 Kria SOM CC
Add support for KD240 Kria SOM CC. It is pretty much subset of KR260 board
from PS perspective.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/835f1d1b8982d46b902db69daad64e8445c051e9.1695808407.git.michal.simek@amd.com
2023-10-09 12:12:29 +02:00
Michal Simek
5d80889783 arm64: zynqmp: Aligned QSPI configuration with latest spec
Official DT binding description for dual stacked/paralllel configurations
have been merged that's why switch to it.

Link: https://lore.kernel.org/r/20220126112608.955728-3-miquel.raynal@bootlin.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2912091c231f5e945ee44601c285fe16263448da.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
d095631d8d ARM: zynq: Describe nand device in DT
Linux requires to describe nand structure under nand controller.
If it is not described nand device is not detected by Linux.

Error shown by Linux kernel:
pl35x-nand-controller e1000000.nand-controller: Incorrect number of NAND chips (0)
pl35x-nand-controller: probe of e1000000.nand-controller failed with error -22

When wired:
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3fcd68ccdfed5e6c079681e3b29e06583ec8a375.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
8daa786211 arm64: zynqmp: Sync licenses with Linux kernel
There is difference between licenses in the Linux kernel and there
shouldn't be any diff because all changes are coming from the same source
at the same time. The difference is really in a time when they were
upstreamed. That's why sync it up.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/813b29378083153b67c60772f28cd2613519f338.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
c5eb6c2d4a arm64: zynqmp: Convert kv260-revA overlay to ASCII text
File was in UTF-8 format but there is no reason for it. Convert it to
ASCII/plain text.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e4d52b898b461b86bb82009f37635f351279c753.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Laurent Pinchart
32b8d6a7e5 arm64: dts: zynqmp: Add ports for the DisplayPort subsystem
The DPSUB DT bindings now specify ports to model the connections with
the programmable logic and the DisplayPort output. Add them to the
device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1c91420e90bc823d7529834c33438216857c7161.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Laurent Pinchart
b0c000b661 arm64: dts: zynqmp: zcu106a: Describe DisplayPort connector
Add a device tree node to describe the DisplayPort connector, and
connect it to the DPSUB output.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe037c93ed41bc5ca97887964037520d449ca98c.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
7469befcd5 arm64: xilinx: Remove address/size-cells from gem nodes
Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.

Error log:
/axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/02f308c774d4f2a798a9a8c066824114a19841a7.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
5c214bac46 arm64: xilinx: Put ethernet phys to mdio node
All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
2036621a61 arm64: zynqmp: Fix Siva's email address format
Some patches didn't have his full name and also there was one more ">" at
the end of email address. That's why correct both of these issues.

Fixes: 174d728471 ("arm64: zynqmp: Switch to amd.com emails")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e970cc0dfabe293c2baf6b231d34f3af0386f1eb.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
1b273a960a arm64: zynqmp: Describe bus-width for SD card on KV260
SD card is connected with 4 data lines which should be described properly.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/065cb9f1c6706eb4d70066e25cfc30d17b9f875d.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00
Michal Simek
1aa867094b arm64: xilinx: Use lower case for partition address
Lower case should be used for register address.
Issue is reported as:
flash@0: partitions: Unevaluated properties are not allowed
('partition@22A0000' was unexpected)

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/66b3361df883ecab4f36ce3b4196fb606c802598.1695378830.git.michal.simek@amd.com
2023-10-09 10:25:32 +02:00