These files include <common.h> twice. Start by removing the second
inclusion of the file.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since
day 1.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add the xfer callback which is used by the MMC_SPI driver and generally by
the dm_spi_xfer callback.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20231116164336.140171-3-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Modify start_transfer and related functions to take a udevice parameter
as input instead of spi_slave. This is needed so that start_transfer can
be used directly via the xfer callback. Also fix a compiler warning.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20231116164336.140171-2-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Currently spi driver gets flash parameter from first subnode.
Few boards have more than one flash with different parameters
and selection of flash is done by on board switch settings.
In such case, uboot needs to be recompiled with updated
device tree to align with board switch settings.
This patch allows to select flash node at runtime.
Boards those are supporting multiple flashes
needs to implement cadence_qspi_get_subnode function and return correct
flash node.
Cc: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
When build for arm64 target, comipler reports the following warning:
drivers/spi/bcm63xx_hsspi.c: In function ‘bcm63xx_hsspi_xfer_dummy_cs’:
include/linux/kernel.h:184:17: warning: comparison of distinct pointer
types lacks a cast
184 | (void) (&_min1 == &_min2); \
| ^~
drivers/spi/bcm63xx_hsspi.c:298:22: note: in expansion of macro ‘min’
298 | size_t curr_step = min(step_size, data_bytes);
This change fix this warning by casting the data_bytes to size_t.
Fixes: 0e144ec38c ("spi: bcm63xx-hsspi: Add prepend mode support")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
To quote the author:
This series imports generic versions of ioread_rep/iowrite_rep and
reads/writes from Linux. Some cleanup is done to make sure that all
platforms have proper defines for implemented functions and there are no
redefinitions.
Directly including asm-generic/io.h may break build because it will
cause redefenition of generic io macros if linux/io.h gets included
later, hence replace it with direct include of linux/io.h
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This file uses errno return values in functions, so include <errno.h>
here rather than rely on indirect inclusion.
Signed-off-by: Tom Rini <trini@konsulko.com>
The following patch migrates the usage of debug and printf functions
to the relevant logging function as per U-Boot DM guidelines.
Additionally some of the debugging statements have been rearanged for
a more meaningfull debug experience.
aarch64-linux-gnu-size reports 229 bytes less when debug is enabled at
file level, while is just 5bytes more when disabled.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Link: https://lore.kernel.org/r/20231013123739.2757979-1-ibai.erkiaga-elorza@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
When 64-bit address is passed only lower 32-bit address
is getting updated. Program the upper 32-bit address in the
DMA destination memory address MSBs register.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231011031515.4151-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Similar change was done by commit b4c2c151b1 ("Kconfig: Remove all
default n/no options") and again sync is required.
default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver
framework and accommodate to lack of ioread32_rep/iowrite32_rep.
Based on Linux version 6.6-rc4
Signed-off-by: Igor Prusov <IVPrusov@sberdevices.ru>
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[trini: Drop <common.h> as it's not needed]
With commit 793e623011 ("spi: mtk_spim: get spi clk rate only once") a
new system to calculate the SPI clocks has been added.
Unfortunately, the do_div macro overrides the global priv->pll_clk_rate
field. This will cause to have a reduced clock rate on each subsequent
SPI call.
Signed-off-by: Valerio 'ftp21' Mancini <ftp21@ftp21.eu>
Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
Reset the FLSHxCR1 registers to default value. ROM may set the register
value and it affects the SPI NAND normal functions.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Cache related issues are seen with small sized data reads.
Due to this, proper data is not read. Also some times sf probe
fails randomly. To workaround this issue, invalidate dcache after read DMA
is triggered.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230915031759.28889-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Before DMA read, ideally cache should be invalidated, so that data from
memory will be updated to cache after DMA is completed. But
flush_dcache_range is being used which is incorrect. Change
flush_dcache_range to invalidate_dcache_range.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230915031759.28889-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The last user of the NEEDS_MANUAL_RELOC has been removed in commit
26af162ac8 ("arch: m68k: Implement relocation")
Remove now unused NEEDS_MANUAL_RELOC code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS.
However these IRQ enable bits may be set in previous boot stage (BootROM).
If we leave these bits not cleared, although u-boot has disabled IRQ and
nothing will happen, the linux kernel may encounter panic during
initializing the spim driver due to IRQ event happens before IRQ handler
is properly setup.
This patch clear IRQ bits to prevent this from happening.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
We don't really need to switch clk rate during operating SPIM controller.
Get clk rate only once at driver probing.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.
Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.
Add read_delay initialization for Versal NET also.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
If cs gpio is requested with ACTIVE_HIGH flag, it will
be pulled low(i.e. active). This is not what we expected.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
According to Documentation/devicetree/bindings/spi/spi-gpio.yaml
from Linux, the recommended spio-gpio properties are:
sck-gpios, miso-gpios and mosi-gpios.
gpio-sck, gpio-mosi and gpio-miso are considered deprecated.
Currently, U-Boot only supports the deprecated properties.
Allow the soft_spi driver to support both the new and old properties.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Current code expects that SPI_TX_BYTE is single bit mode
but it is wrong. It indicates byte program mode,
not single bit mode.
If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
the default transfer bus width is single bit.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC
for common features and IP blocks. Use this config instead of each chip
config as the Kconfig dependency for Broadcom HSSPI driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for an optional external chip-select gpio.
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Remove the platform data header because its content is only used by the
driver.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Rename the flush function into pl022_spi_flush to avoid conflicting
types with previous declaration of the function in stdio.h header.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Align the compatible property with the kernel device tree binding [1]
by removing the '-spi' suffix.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
At first SPI transfers, multiple chip selects can be
enabled simultaneously. This is due to chip select
polarity, which is not properly initialized for all
channels. This patch fixes the issue.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
This patch adds 4-byte address mode support. Because traditional access
based on FIFO/shift register, it's complex to specify information like
opcode, address length, dummy bytes etc to flash. Replace the traditional
access by spi-mem layer which is essential to make 4-byte address mode
support possible.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
