mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
Prepare v2024.01-rc6
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This commit is contained in:
commit
93a0138acb
35 changed files with 1295 additions and 928 deletions
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@ -1 +1 @@
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|||
--find-maintainer-files --maintainer-path=.
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||||
--find-maintainer-files --git --maintainer-path=.
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||||
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|
2
Makefile
2
Makefile
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@ -3,7 +3,7 @@
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|||
VERSION = 2024
|
||||
PATCHLEVEL = 01
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||||
SUBLEVEL =
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||||
EXTRAVERSION = -rc5
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||||
EXTRAVERSION = -rc6
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NAME =
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# *DOCUMENTATION*
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||||
|
|
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@ -77,10 +77,59 @@
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|||
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||||
&gpio2 {
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bootph-pre-ram;
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||||
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||||
dsi-reset-hog {
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bootph-pre-ram;
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gpio-hog;
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output-high;
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gpios = <2 GPIO_ACTIVE_LOW>;
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line-name = "DSI_RESET_1V8#";
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||||
};
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||||
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||||
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||||
dsi-irq-hog {
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bootph-pre-ram;
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gpio-hog;
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input;
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gpios = <3 GPIO_ACTIVE_LOW>;
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line-name = "DSI_IRQ_1V8#";
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};
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||||
graphics-prsnt-hog {
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bootph-pre-ram;
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gpio-hog;
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input;
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gpios = <7 GPIO_ACTIVE_LOW>;
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line-name = "GRAPHICS_PRSNT_1V8#";
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};
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};
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&gpio3 {
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bootph-pre-ram;
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bl-enable-hog {
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bootph-pre-ram;
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gpio-hog;
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output-low;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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line-name = "BL_ENABLE_1V8";
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};
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tft-enable-hog {
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bootph-pre-ram;
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gpio-hog;
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output-low;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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line-name = "TFT_ENABLE_1V8";
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};
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graphics-gpio0-hog {
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bootph-pre-ram;
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gpio-hog;
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input;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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line-name = "GRAPHICS_GPIO0_1V8";
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};
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};
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&gpio4 {
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|
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@ -67,10 +67,58 @@
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|||
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&gpio3 {
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bootph-pre-ram;
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bl-enable-hog {
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bootph-pre-ram;
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gpio-hog;
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output-low;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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line-name = "BL_ENABLE_1V8";
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};
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tft-enable-hog {
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bootph-pre-ram;
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gpio-hog;
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output-low;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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line-name = "TFT_ENABLE_1V8";
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};
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graphics-gpio0-hog {
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bootph-pre-ram;
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gpio-hog;
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input;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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line-name = "GRAPHICS_GPIO0_1V8";
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};
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};
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&gpio4 {
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bootph-pre-ram;
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dsi-reset-hog {
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bootph-pre-ram;
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gpio-hog;
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output-high;
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gpios = <0 GPIO_ACTIVE_LOW>;
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line-name = "DSI_RESET_1V8#";
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};
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||||
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graphics-prsnt-hog {
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bootph-pre-ram;
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gpio-hog;
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input;
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gpios = <18 GPIO_ACTIVE_LOW>;
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line-name = "GRAPHICS_PRSNT_1V8#";
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||||
};
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dsi-irq-hog {
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bootph-pre-ram;
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gpio-hog;
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||||
input;
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gpios = <19 GPIO_ACTIVE_LOW>;
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||||
line-name = "DSI_IRQ_1V8#";
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||||
};
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};
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||||
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&gpio5 {
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|
|
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@ -1,19 +1,20 @@
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|||
// SPDX-License-Identifier: GPL-2.0+
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||||
/*
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||||
* This file was generated with the
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||||
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
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||||
* Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
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||||
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
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||||
* Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
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||||
* DDR Type: LPDDR4
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* F0 = 50MHz F1 = NA F2 = 800MHz
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||||
* Density (per channel): 16Gb
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* Write DBI: Enable
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||||
* Number of Ranks: 1
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*/
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*/
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||||
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#define DDRSS_PLL_FHS_CNT 3
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#define DDRSS_PLL_FREQUENCY_1 400000000
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#define DDRSS_PLL_FREQUENCY_2 400000000
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#define DDRSS_CTL_0_DATA 0x00000B00
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#define DDRSS_CTL_1_DATA 0x00000000
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||||
#define DDRSS_CTL_2_DATA 0x00000000
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|
@ -54,20 +55,20 @@
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|||
#define DDRSS_CTL_37_DATA 0x00000000
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||||
#define DDRSS_CTL_38_DATA 0x0000040C
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#define DDRSS_CTL_39_DATA 0x00000000
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#define DDRSS_CTL_40_DATA 0x0000081C
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||||
#define DDRSS_CTL_40_DATA 0x00000A1C
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||||
#define DDRSS_CTL_41_DATA 0x00000000
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||||
#define DDRSS_CTL_42_DATA 0x0000081C
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||||
#define DDRSS_CTL_42_DATA 0x00000A1C
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||||
#define DDRSS_CTL_43_DATA 0x00000000
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||||
#define DDRSS_CTL_44_DATA 0x05000804
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#define DDRSS_CTL_45_DATA 0x00000B00
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#define DDRSS_CTL_46_DATA 0x09090004
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#define DDRSS_CTL_47_DATA 0x00000204
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||||
#define DDRSS_CTL_47_DATA 0x00000304
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#define DDRSS_CTL_48_DATA 0x00370008
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#define DDRSS_CTL_49_DATA 0x09090024
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||||
#define DDRSS_CTL_50_DATA 0x00001910
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#define DDRSS_CTL_50_DATA 0x00002110
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||||
#define DDRSS_CTL_51_DATA 0x00370008
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#define DDRSS_CTL_52_DATA 0x09090024
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||||
#define DDRSS_CTL_53_DATA 0x09001910
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||||
#define DDRSS_CTL_53_DATA 0x09002110
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#define DDRSS_CTL_54_DATA 0x000A0A09
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#define DDRSS_CTL_55_DATA 0x0400036D
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#define DDRSS_CTL_56_DATA 0x09092004
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@ -223,19 +224,19 @@
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|||
#define DDRSS_CTL_206_DATA 0x00000000
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#define DDRSS_CTL_207_DATA 0x00000000
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#define DDRSS_CTL_208_DATA 0x00000024
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#define DDRSS_CTL_209_DATA 0x00000012
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#define DDRSS_CTL_209_DATA 0x0000001A
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#define DDRSS_CTL_210_DATA 0x00000000
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#define DDRSS_CTL_211_DATA 0x00000024
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#define DDRSS_CTL_212_DATA 0x00000012
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#define DDRSS_CTL_212_DATA 0x0000001A
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#define DDRSS_CTL_213_DATA 0x00000000
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#define DDRSS_CTL_214_DATA 0x00000004
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#define DDRSS_CTL_215_DATA 0x00000000
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#define DDRSS_CTL_216_DATA 0x00000000
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#define DDRSS_CTL_217_DATA 0x00000024
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#define DDRSS_CTL_218_DATA 0x00000012
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#define DDRSS_CTL_218_DATA 0x0000001A
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#define DDRSS_CTL_219_DATA 0x00000000
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#define DDRSS_CTL_220_DATA 0x00000024
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#define DDRSS_CTL_221_DATA 0x00000012
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#define DDRSS_CTL_221_DATA 0x0000001A
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#define DDRSS_CTL_222_DATA 0x00000000
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#define DDRSS_CTL_223_DATA 0x00000000
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#define DDRSS_CTL_224_DATA 0x00000031
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@ -268,21 +269,21 @@
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#define DDRSS_CTL_251_DATA 0x00000000
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#define DDRSS_CTL_252_DATA 0x00000000
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#define DDRSS_CTL_253_DATA 0x00000000
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#define DDRSS_CTL_254_DATA 0x46004646
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#define DDRSS_CTL_255_DATA 0x00002746
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#define DDRSS_CTL_256_DATA 0x00000027
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#define DDRSS_CTL_257_DATA 0x00000027
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#define DDRSS_CTL_258_DATA 0x00000027
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#define DDRSS_CTL_259_DATA 0x00000027
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#define DDRSS_CTL_260_DATA 0x00000027
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#define DDRSS_CTL_254_DATA 0x44004444
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#define DDRSS_CTL_255_DATA 0x00004D44
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#define DDRSS_CTL_256_DATA 0x0000004D
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#define DDRSS_CTL_257_DATA 0x0000004D
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#define DDRSS_CTL_258_DATA 0x0000004D
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#define DDRSS_CTL_259_DATA 0x0000004D
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#define DDRSS_CTL_260_DATA 0x0000004D
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#define DDRSS_CTL_261_DATA 0x00000000
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#define DDRSS_CTL_262_DATA 0x00000000
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#define DDRSS_CTL_263_DATA 0x0000000F
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#define DDRSS_CTL_264_DATA 0x0000000F
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#define DDRSS_CTL_265_DATA 0x0000000F
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#define DDRSS_CTL_266_DATA 0x0000000F
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#define DDRSS_CTL_267_DATA 0x0000000F
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#define DDRSS_CTL_268_DATA 0x0000000F
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#define DDRSS_CTL_263_DATA 0x0000004D
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#define DDRSS_CTL_264_DATA 0x0000004D
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#define DDRSS_CTL_265_DATA 0x0000004D
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#define DDRSS_CTL_266_DATA 0x0000004D
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#define DDRSS_CTL_267_DATA 0x0000004D
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#define DDRSS_CTL_268_DATA 0x0000004D
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#define DDRSS_CTL_269_DATA 0x00000000
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#define DDRSS_CTL_270_DATA 0x00001000
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||||
#define DDRSS_CTL_271_DATA 0x00000015
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||||
|
@ -388,13 +389,13 @@
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|||
#define DDRSS_CTL_371_DATA 0x01000101
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||||
#define DDRSS_CTL_372_DATA 0x01010001
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||||
#define DDRSS_CTL_373_DATA 0x00010101
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||||
#define DDRSS_CTL_374_DATA 0x01050503
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||||
#define DDRSS_CTL_374_DATA 0x01070703
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||||
#define DDRSS_CTL_375_DATA 0x05020201
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||||
#define DDRSS_CTL_376_DATA 0x08080C0C
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||||
#define DDRSS_CTL_377_DATA 0x00080308
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||||
#define DDRSS_CTL_378_DATA 0x000B030E
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||||
#define DDRSS_CTL_379_DATA 0x000B0310
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||||
#define DDRSS_CTL_380_DATA 0x0B0B0810
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||||
#define DDRSS_CTL_378_DATA 0x0009030E
|
||||
#define DDRSS_CTL_379_DATA 0x00090312
|
||||
#define DDRSS_CTL_380_DATA 0x09090806
|
||||
#define DDRSS_CTL_381_DATA 0x01000000
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||||
#define DDRSS_CTL_382_DATA 0x03020301
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||||
#define DDRSS_CTL_383_DATA 0x04000102
|
||||
|
@ -416,7 +417,7 @@
|
|||
#define DDRSS_CTL_399_DATA 0x00003690
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||||
#define DDRSS_CTL_400_DATA 0x00007940
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||||
#define DDRSS_CTL_401_DATA 0x070D0402
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||||
#define DDRSS_CTL_402_DATA 0x00260405
|
||||
#define DDRSS_CTL_402_DATA 0x00260607
|
||||
#define DDRSS_CTL_403_DATA 0x00000C20
|
||||
#define DDRSS_CTL_404_DATA 0x00000200
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||||
#define DDRSS_CTL_405_DATA 0x00000200
|
||||
|
@ -425,7 +426,7 @@
|
|||
#define DDRSS_CTL_408_DATA 0x00003690
|
||||
#define DDRSS_CTL_409_DATA 0x00007940
|
||||
#define DDRSS_CTL_410_DATA 0x070D0402
|
||||
#define DDRSS_CTL_411_DATA 0x00000405
|
||||
#define DDRSS_CTL_411_DATA 0x00000607
|
||||
#define DDRSS_CTL_412_DATA 0x00000000
|
||||
#define DDRSS_CTL_413_DATA 0x0302000A
|
||||
#define DDRSS_CTL_414_DATA 0x01000500
|
||||
|
@ -609,8 +610,8 @@
|
|||
#define DDRSS_PI_169_DATA 0x00020043
|
||||
#define DDRSS_PI_170_DATA 0x02000200
|
||||
#define DDRSS_PI_171_DATA 0x00000004
|
||||
#define DDRSS_PI_172_DATA 0x0000080C
|
||||
#define DDRSS_PI_173_DATA 0x00081C00
|
||||
#define DDRSS_PI_172_DATA 0x00000A0C
|
||||
#define DDRSS_PI_173_DATA 0x000A1C00
|
||||
#define DDRSS_PI_174_DATA 0x001C0000
|
||||
#define DDRSS_PI_175_DATA 0x00000013
|
||||
#define DDRSS_PI_176_DATA 0x00000059
|
||||
|
@ -624,15 +625,15 @@
|
|||
#define DDRSS_PI_184_DATA 0x01000100
|
||||
#define DDRSS_PI_185_DATA 0x00000100
|
||||
#define DDRSS_PI_186_DATA 0x00000000
|
||||
#define DDRSS_PI_187_DATA 0x05050503
|
||||
#define DDRSS_PI_187_DATA 0x05070703
|
||||
#define DDRSS_PI_188_DATA 0x01010C0C
|
||||
#define DDRSS_PI_189_DATA 0x01010101
|
||||
#define DDRSS_PI_190_DATA 0x000C0C0A
|
||||
#define DDRSS_PI_191_DATA 0x00000000
|
||||
#define DDRSS_PI_192_DATA 0x00000000
|
||||
#define DDRSS_PI_193_DATA 0x04000000
|
||||
#define DDRSS_PI_194_DATA 0x04020808
|
||||
#define DDRSS_PI_195_DATA 0x04040204
|
||||
#define DDRSS_PI_194_DATA 0x06020808
|
||||
#define DDRSS_PI_195_DATA 0x04040206
|
||||
#define DDRSS_PI_196_DATA 0x00090031
|
||||
#define DDRSS_PI_197_DATA 0x00110039
|
||||
#define DDRSS_PI_198_DATA 0x00110039
|
||||
|
@ -661,13 +662,13 @@
|
|||
#define DDRSS_PI_221_DATA 0x00001900
|
||||
#define DDRSS_PI_222_DATA 0x32000056
|
||||
#define DDRSS_PI_223_DATA 0x06000101
|
||||
#define DDRSS_PI_224_DATA 0x001D0204
|
||||
#define DDRSS_PI_225_DATA 0x32120058
|
||||
#define DDRSS_PI_224_DATA 0x001F0204
|
||||
#define DDRSS_PI_225_DATA 0x72400056
|
||||
#define DDRSS_PI_226_DATA 0x05000101
|
||||
#define DDRSS_PI_227_DATA 0x001D0408
|
||||
#define DDRSS_PI_228_DATA 0x32120058
|
||||
#define DDRSS_PI_227_DATA 0x001F0608
|
||||
#define DDRSS_PI_228_DATA 0x72400056
|
||||
#define DDRSS_PI_229_DATA 0x05000101
|
||||
#define DDRSS_PI_230_DATA 0x00000408
|
||||
#define DDRSS_PI_230_DATA 0x00000608
|
||||
#define DDRSS_PI_231_DATA 0x05040900
|
||||
#define DDRSS_PI_232_DATA 0x00060900
|
||||
#define DDRSS_PI_233_DATA 0x00000315
|
||||
|
@ -741,23 +742,23 @@
|
|||
#define DDRSS_PI_301_DATA 0x00000000
|
||||
#define DDRSS_PI_302_DATA 0x00000000
|
||||
#define DDRSS_PI_303_DATA 0x00000000
|
||||
#define DDRSS_PI_304_DATA 0x00100F27
|
||||
#define DDRSS_PI_304_DATA 0x00104D4D
|
||||
#define DDRSS_PI_305_DATA 0x00000000
|
||||
#define DDRSS_PI_306_DATA 0x00000024
|
||||
#define DDRSS_PI_307_DATA 0x00000012
|
||||
#define DDRSS_PI_307_DATA 0x0000001A
|
||||
#define DDRSS_PI_308_DATA 0x000000B1
|
||||
#define DDRSS_PI_309_DATA 0x00000000
|
||||
#define DDRSS_PI_310_DATA 0x00000000
|
||||
#define DDRSS_PI_311_DATA 0x46000000
|
||||
#define DDRSS_PI_312_DATA 0x00150F27
|
||||
#define DDRSS_PI_311_DATA 0x44000000
|
||||
#define DDRSS_PI_312_DATA 0x00154D4D
|
||||
#define DDRSS_PI_313_DATA 0x00000000
|
||||
#define DDRSS_PI_314_DATA 0x00000024
|
||||
#define DDRSS_PI_315_DATA 0x00000012
|
||||
#define DDRSS_PI_315_DATA 0x0000001A
|
||||
#define DDRSS_PI_316_DATA 0x000000B1
|
||||
#define DDRSS_PI_317_DATA 0x00000000
|
||||
#define DDRSS_PI_318_DATA 0x00000000
|
||||
#define DDRSS_PI_319_DATA 0x46000000
|
||||
#define DDRSS_PI_320_DATA 0x00150F27
|
||||
#define DDRSS_PI_319_DATA 0x44000000
|
||||
#define DDRSS_PI_320_DATA 0x00154D4D
|
||||
#define DDRSS_PI_321_DATA 0x00000000
|
||||
#define DDRSS_PI_322_DATA 0x00000004
|
||||
#define DDRSS_PI_323_DATA 0x00000000
|
||||
|
@ -765,23 +766,23 @@
|
|||
#define DDRSS_PI_325_DATA 0x00000000
|
||||
#define DDRSS_PI_326_DATA 0x00000000
|
||||
#define DDRSS_PI_327_DATA 0x00000000
|
||||
#define DDRSS_PI_328_DATA 0x00100F27
|
||||
#define DDRSS_PI_328_DATA 0x00104D4D
|
||||
#define DDRSS_PI_329_DATA 0x00000000
|
||||
#define DDRSS_PI_330_DATA 0x00000024
|
||||
#define DDRSS_PI_331_DATA 0x00000012
|
||||
#define DDRSS_PI_331_DATA 0x0000001A
|
||||
#define DDRSS_PI_332_DATA 0x000000B1
|
||||
#define DDRSS_PI_333_DATA 0x00000000
|
||||
#define DDRSS_PI_334_DATA 0x00000000
|
||||
#define DDRSS_PI_335_DATA 0x46000000
|
||||
#define DDRSS_PI_336_DATA 0x00150F27
|
||||
#define DDRSS_PI_335_DATA 0x44000000
|
||||
#define DDRSS_PI_336_DATA 0x00154D4D
|
||||
#define DDRSS_PI_337_DATA 0x00000000
|
||||
#define DDRSS_PI_338_DATA 0x00000024
|
||||
#define DDRSS_PI_339_DATA 0x00000012
|
||||
#define DDRSS_PI_339_DATA 0x0000001A
|
||||
#define DDRSS_PI_340_DATA 0x000000B1
|
||||
#define DDRSS_PI_341_DATA 0x00000000
|
||||
#define DDRSS_PI_342_DATA 0x00000000
|
||||
#define DDRSS_PI_343_DATA 0x46000000
|
||||
#define DDRSS_PI_344_DATA 0x00150F27
|
||||
#define DDRSS_PI_343_DATA 0x44000000
|
||||
#define DDRSS_PI_344_DATA 0x00154D4D
|
||||
#define DDRSS_PHY_0_DATA 0x04F00000
|
||||
#define DDRSS_PHY_1_DATA 0x00000000
|
||||
#define DDRSS_PHY_2_DATA 0x00030200
|
||||
|
@ -856,8 +857,8 @@
|
|||
#define DDRSS_PHY_71_DATA 0x00000000
|
||||
#define DDRSS_PHY_72_DATA 0x041F07FF
|
||||
#define DDRSS_PHY_73_DATA 0x00000000
|
||||
#define DDRSS_PHY_74_DATA 0x01CC0B01
|
||||
#define DDRSS_PHY_75_DATA 0x1003CC0B
|
||||
#define DDRSS_PHY_74_DATA 0x01FF0B01
|
||||
#define DDRSS_PHY_75_DATA 0x1003FF0B
|
||||
#define DDRSS_PHY_76_DATA 0x20000140
|
||||
#define DDRSS_PHY_77_DATA 0x07FF0200
|
||||
#define DDRSS_PHY_78_DATA 0x0000DD01
|
||||
|
@ -872,7 +873,7 @@
|
|||
#define DDRSS_PHY_87_DATA 0x02020010
|
||||
#define DDRSS_PHY_88_DATA 0x51516041
|
||||
#define DDRSS_PHY_89_DATA 0x31C06000
|
||||
#define DDRSS_PHY_90_DATA 0x07AB0340
|
||||
#define DDRSS_PHY_90_DATA 0x06B60340
|
||||
#define DDRSS_PHY_91_DATA 0x0000C0C0
|
||||
#define DDRSS_PHY_92_DATA 0x04050000
|
||||
#define DDRSS_PHY_93_DATA 0x00000504
|
||||
|
@ -1112,8 +1113,8 @@
|
|||
#define DDRSS_PHY_327_DATA 0x00000000
|
||||
#define DDRSS_PHY_328_DATA 0x041F07FF
|
||||
#define DDRSS_PHY_329_DATA 0x00000000
|
||||
#define DDRSS_PHY_330_DATA 0x01CC0B01
|
||||
#define DDRSS_PHY_331_DATA 0x1003CC0B
|
||||
#define DDRSS_PHY_330_DATA 0x01FF0B01
|
||||
#define DDRSS_PHY_331_DATA 0x1003FF0B
|
||||
#define DDRSS_PHY_332_DATA 0x20000140
|
||||
#define DDRSS_PHY_333_DATA 0x07FF0200
|
||||
#define DDRSS_PHY_334_DATA 0x0000DD01
|
||||
|
@ -1128,7 +1129,7 @@
|
|||
#define DDRSS_PHY_343_DATA 0x02020010
|
||||
#define DDRSS_PHY_344_DATA 0x51516041
|
||||
#define DDRSS_PHY_345_DATA 0x31C06000
|
||||
#define DDRSS_PHY_346_DATA 0x07AB0340
|
||||
#define DDRSS_PHY_346_DATA 0x06B60340
|
||||
#define DDRSS_PHY_347_DATA 0x0000C0C0
|
||||
#define DDRSS_PHY_348_DATA 0x04050000
|
||||
#define DDRSS_PHY_349_DATA 0x00000504
|
||||
|
@ -1326,7 +1327,7 @@
|
|||
#define DDRSS_PHY_541_DATA 0x003F0000
|
||||
#define DDRSS_PHY_542_DATA 0x000F013F
|
||||
#define DDRSS_PHY_543_DATA 0x0000000F
|
||||
#define DDRSS_PHY_544_DATA 0x020002CC
|
||||
#define DDRSS_PHY_544_DATA 0x020002FF
|
||||
#define DDRSS_PHY_545_DATA 0x00030000
|
||||
#define DDRSS_PHY_546_DATA 0x00000300
|
||||
#define DDRSS_PHY_547_DATA 0x00000300
|
||||
|
@ -1582,7 +1583,7 @@
|
|||
#define DDRSS_PHY_797_DATA 0x00000000
|
||||
#define DDRSS_PHY_798_DATA 0x000F0000
|
||||
#define DDRSS_PHY_799_DATA 0x0000000F
|
||||
#define DDRSS_PHY_800_DATA 0x020002CC
|
||||
#define DDRSS_PHY_800_DATA 0x020002FF
|
||||
#define DDRSS_PHY_801_DATA 0x00030000
|
||||
#define DDRSS_PHY_802_DATA 0x00000300
|
||||
#define DDRSS_PHY_803_DATA 0x00000300
|
||||
|
@ -1838,7 +1839,7 @@
|
|||
#define DDRSS_PHY_1053_DATA 0x10000000
|
||||
#define DDRSS_PHY_1054_DATA 0x000F0000
|
||||
#define DDRSS_PHY_1055_DATA 0x0000000F
|
||||
#define DDRSS_PHY_1056_DATA 0x020002CC
|
||||
#define DDRSS_PHY_1056_DATA 0x020002FF
|
||||
#define DDRSS_PHY_1057_DATA 0x00030000
|
||||
#define DDRSS_PHY_1058_DATA 0x00000300
|
||||
#define DDRSS_PHY_1059_DATA 0x00000300
|
||||
|
@ -2169,22 +2170,22 @@
|
|||
#define DDRSS_PHY_1384_DATA 0x00000300
|
||||
#define DDRSS_PHY_1385_DATA 0x00000300
|
||||
#define DDRSS_PHY_1386_DATA 0x00000300
|
||||
#define DDRSS_PHY_1387_DATA 0x3183BF77
|
||||
#define DDRSS_PHY_1387_DATA 0x31833F77
|
||||
#define DDRSS_PHY_1388_DATA 0x00000000
|
||||
#define DDRSS_PHY_1389_DATA 0x0C000DFF
|
||||
#define DDRSS_PHY_1390_DATA 0x30000DFF
|
||||
#define DDRSS_PHY_1391_DATA 0x3F0DFF11
|
||||
#define DDRSS_PHY_1392_DATA 0x01990000
|
||||
#define DDRSS_PHY_1393_DATA 0x780DFFCC
|
||||
#define DDRSS_PHY_1389_DATA 0x0C000DBF
|
||||
#define DDRSS_PHY_1390_DATA 0x30000DBF
|
||||
#define DDRSS_PHY_1391_DATA 0x3F0DBF11
|
||||
#define DDRSS_PHY_1392_DATA 0x01FF0000
|
||||
#define DDRSS_PHY_1393_DATA 0x780DBFFF
|
||||
#define DDRSS_PHY_1394_DATA 0x00000C11
|
||||
#define DDRSS_PHY_1395_DATA 0x00018011
|
||||
#define DDRSS_PHY_1396_DATA 0x0089FF00
|
||||
#define DDRSS_PHY_1397_DATA 0x000C3F11
|
||||
#define DDRSS_PHY_1398_DATA 0x01990000
|
||||
#define DDRSS_PHY_1399_DATA 0x000C3F11
|
||||
#define DDRSS_PHY_1400_DATA 0x01990000
|
||||
#define DDRSS_PHY_1401_DATA 0x3F0DFF11
|
||||
#define DDRSS_PHY_1402_DATA 0x01990000
|
||||
#define DDRSS_PHY_1398_DATA 0x01FF0000
|
||||
#define DDRSS_PHY_1399_DATA 0x000C3F91
|
||||
#define DDRSS_PHY_1400_DATA 0x01FF0000
|
||||
#define DDRSS_PHY_1401_DATA 0x3F0DBF11
|
||||
#define DDRSS_PHY_1402_DATA 0x01FF0000
|
||||
#define DDRSS_PHY_1403_DATA 0x00018011
|
||||
#define DDRSS_PHY_1404_DATA 0x0089FF00
|
||||
#define DDRSS_PHY_1405_DATA 0x20040004
|
||||
|
|
|
@ -35,7 +35,10 @@
|
|||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01880000 0x00 0x90000>; /* GICR */
|
||||
<0x00 0x01880000 0x00 0x90000>, /* GICR */
|
||||
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
|
||||
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
|
||||
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
|
||||
/*
|
||||
* vcpumntirq:
|
||||
* virtual CPU interface maintenance interrupt
|
||||
|
@ -88,6 +91,7 @@
|
|||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_uart1: serial@2810000 {
|
||||
|
@ -96,6 +100,7 @@
|
|||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_uart2: serial@2820000 {
|
||||
|
@ -104,29 +109,47 @@
|
|||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: crypto@4e00000 {
|
||||
compatible = "ti,am654-sa2ul";
|
||||
reg = <0x0 0x4e00000 0x0 0x1200>;
|
||||
power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
|
||||
power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
|
||||
|
||||
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
|
||||
<&main_udmap 0x4001>;
|
||||
dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
|
||||
<&main_udmap 0x4003>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
dma-coherent;
|
||||
|
||||
rng: rng@4e10000 {
|
||||
compatible = "inside-secure,safexcel-eip76";
|
||||
reg = <0x0 0x4e10000 0x0 0x7d>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 136 1>;
|
||||
status = "disabled"; /* Used by OP-TEE */
|
||||
};
|
||||
};
|
||||
|
||||
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
|
||||
main_timerio_input: pinctrl@104200 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0x104200 0x0 0x30>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000001ff>;
|
||||
};
|
||||
|
||||
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
|
||||
main_timerio_output: pinctrl@104280 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0x104280 0x0 0x20>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
};
|
||||
|
||||
main_pmx0: pinctrl@11c000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0x11c000 0x0 0x2e4>;
|
||||
|
@ -152,6 +175,7 @@
|
|||
clock-names = "fck";
|
||||
clocks = <&k3_clks 110 1>;
|
||||
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_i2c1: i2c@2010000 {
|
||||
|
@ -163,6 +187,7 @@
|
|||
clock-names = "fck";
|
||||
clocks = <&k3_clks 111 1>;
|
||||
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_i2c2: i2c@2020000 {
|
||||
|
@ -174,6 +199,7 @@
|
|||
clock-names = "fck";
|
||||
clocks = <&k3_clks 112 1>;
|
||||
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_i2c3: i2c@2030000 {
|
||||
|
@ -185,6 +211,7 @@
|
|||
clock-names = "fck";
|
||||
clocks = <&k3_clks 113 1>;
|
||||
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap0: pwm@3100000 {
|
||||
|
@ -194,6 +221,7 @@
|
|||
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 39 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi0: spi@2100000 {
|
||||
|
@ -206,6 +234,7 @@
|
|||
#size-cells = <0>;
|
||||
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
|
||||
dma-names = "tx0", "rx0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi1: spi@2110000 {
|
||||
|
@ -218,6 +247,7 @@
|
|||
#size-cells = <0>;
|
||||
assigned-clocks = <&k3_clks 137 1>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi2: spi@2120000 {
|
||||
|
@ -228,6 +258,7 @@
|
|||
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi3: spi@2130000 {
|
||||
|
@ -238,6 +269,7 @@
|
|||
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi4: spi@2140000 {
|
||||
|
@ -248,6 +280,151 @@
|
|||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_timer0: timer@2400000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2400000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 23 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 23 0>;
|
||||
assigned-clock-parents = <&k3_clks 23 1>;
|
||||
power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer1: timer@2410000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2410000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 24 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 24 0>;
|
||||
assigned-clock-parents = <&k3_clks 24 1>;
|
||||
power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer2: timer@2420000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2420000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 27 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 27 0>;
|
||||
assigned-clock-parents = <&k3_clks 27 1>;
|
||||
power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer3: timer@2430000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2430000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 28 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 28 0>;
|
||||
assigned-clock-parents = <&k3_clks 28 1>;
|
||||
power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer4: timer@2440000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2440000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 29 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 29 0>;
|
||||
assigned-clock-parents = <&k3_clks 29 1>;
|
||||
power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer5: timer@2450000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2450000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 30 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 30 0>;
|
||||
assigned-clock-parents = <&k3_clks 30 1>;
|
||||
power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer6: timer@2460000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2460000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 31 0>;
|
||||
assigned-clocks = <&k3_clks 31 0>;
|
||||
assigned-clock-parents = <&k3_clks 31 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer7: timer@2470000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2470000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 32 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 32 0>;
|
||||
assigned-clock-parents = <&k3_clks 32 1>;
|
||||
power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer8: timer@2480000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2480000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 33 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 33 0>;
|
||||
assigned-clock-parents = <&k3_clks 33 1>;
|
||||
power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer9: timer@2490000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2490000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 34 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 34 0>;
|
||||
assigned-clock-parents = <&k3_clks 34 1>;
|
||||
power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer10: timer@24a0000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x24a0000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 25 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 25 0>;
|
||||
assigned-clock-parents = <&k3_clks 25 1>;
|
||||
power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
main_timer11: timer@24b0000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x24b0000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 26 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 26 0>;
|
||||
assigned-clock-parents = <&k3_clks 26 1>;
|
||||
power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
sdhci0: mmc@4f80000 {
|
||||
|
@ -292,7 +469,6 @@
|
|||
ti,otap-del-sel-ddr52 = <0x4>;
|
||||
ti,otap-del-sel-hs200 = <0x7>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
@ -304,21 +480,6 @@
|
|||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x00100000 0x1c000>;
|
||||
|
||||
pcie0_mode: pcie-mode@4060 {
|
||||
compatible = "syscon";
|
||||
reg = <0x00004060 0x4>;
|
||||
};
|
||||
|
||||
pcie1_mode: pcie-mode@4070 {
|
||||
compatible = "syscon";
|
||||
reg = <0x00004070 0x4>;
|
||||
};
|
||||
|
||||
pcie_devid: pcie-devid@210 {
|
||||
compatible = "syscon";
|
||||
reg = <0x00000210 0x4>;
|
||||
};
|
||||
|
||||
serdes0_clk: clock@4080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x00004080 0x4>;
|
||||
|
@ -338,11 +499,11 @@
|
|||
|
||||
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0000041e0 0x14>;
|
||||
reg = <0x000041e0 0x14>;
|
||||
};
|
||||
|
||||
ehrpwm_tbclk: clock@4140 {
|
||||
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
|
||||
ehrpwm_tbclk: clock-controller@4140 {
|
||||
compatible = "ti,am654-ehrpwm-tbclk";
|
||||
reg = <0x4140 0x18>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
@ -439,7 +600,7 @@
|
|||
};
|
||||
|
||||
main_navss: bus@30800000 {
|
||||
compatible = "simple-mfd";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
|
||||
|
@ -497,6 +658,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster1: mailbox@31f81000 {
|
||||
|
@ -506,6 +668,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@31f82000 {
|
||||
|
@ -515,6 +678,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@31f83000 {
|
||||
|
@ -524,6 +688,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster4: mailbox@31f84000 {
|
||||
|
@ -533,6 +698,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster5: mailbox@31f85000 {
|
||||
|
@ -542,6 +708,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster6: mailbox@31f86000 {
|
||||
|
@ -551,6 +718,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster7: mailbox@31f87000 {
|
||||
|
@ -560,6 +728,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster8: mailbox@31f88000 {
|
||||
|
@ -569,6 +738,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster9: mailbox@31f89000 {
|
||||
|
@ -578,6 +748,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster10: mailbox@31f8a000 {
|
||||
|
@ -587,6 +758,7 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster11: mailbox@31f8b000 {
|
||||
|
@ -596,15 +768,17 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x3c000000 0x0 0x400000>,
|
||||
<0x0 0x38000000 0x0 0x400000>,
|
||||
<0x0 0x31120000 0x0 0x100>,
|
||||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
reg = <0x0 0x3c000000 0x0 0x400000>,
|
||||
<0x0 0x38000000 0x0 0x400000>,
|
||||
<0x0 0x31120000 0x0 0x100>,
|
||||
<0x0 0x33000000 0x0 0x40000>,
|
||||
<0x0 0x31080000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
|
@ -614,9 +788,9 @@
|
|||
|
||||
main_udmap: dma-controller@31150000 {
|
||||
compatible = "ti,am654-navss-main-udmap";
|
||||
reg = <0x0 0x31150000 0x0 0x100>,
|
||||
<0x0 0x34000000 0x0 0x100000>,
|
||||
<0x0 0x35000000 0x0 0x100000>;
|
||||
reg = <0x0 0x31150000 0x0 0x100>,
|
||||
<0x0 0x34000000 0x0 0x100000>,
|
||||
<0x0 0x35000000 0x0 0x100000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
#dma-cells = <1>;
|
||||
|
@ -687,15 +861,15 @@
|
|||
|
||||
pcie0_rc: pcie@5500000 {
|
||||
compatible = "ti,am654-pcie-rc";
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "config", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
|
||||
0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&pcie_devid>;
|
||||
ti,syscon-pcie-mode = <&pcie0_mode>;
|
||||
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
|
||||
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&scm_conf 0x210>;
|
||||
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
|
||||
bus-range = <0x0 0xff>;
|
||||
num-viewport = <16>;
|
||||
max-link-speed = <2>;
|
||||
|
@ -703,32 +877,34 @@
|
|||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
device_type = "pci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@5500000 {
|
||||
compatible = "ti,am654-pcie-ep";
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "addr_space", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,syscon-pcie-mode = <&pcie0_mode>;
|
||||
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
|
||||
num-ib-windows = <16>;
|
||||
num-ob-windows = <16>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1_rc: pcie@5600000 {
|
||||
compatible = "ti,am654-pcie-rc";
|
||||
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
|
||||
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "config", "atu";
|
||||
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
|
||||
0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&pcie_devid>;
|
||||
ti,syscon-pcie-mode = <&pcie1_mode>;
|
||||
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
|
||||
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&scm_conf 0x210>;
|
||||
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
|
||||
bus-range = <0x0 0xff>;
|
||||
num-viewport = <16>;
|
||||
max-link-speed = <2>;
|
||||
|
@ -736,19 +912,21 @@
|
|||
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
||||
device_type = "pci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@5600000 {
|
||||
compatible = "ti,am654-pcie-ep";
|
||||
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
|
||||
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "addr_space", "atu";
|
||||
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,syscon-pcie-mode = <&pcie1_mode>;
|
||||
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
|
||||
num-ib-windows = <16>;
|
||||
num-ob-windows = <16>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp0: mcasp@2b00000 {
|
||||
|
@ -766,6 +944,7 @@
|
|||
clocks = <&k3_clks 104 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@2b10000 {
|
||||
|
@ -783,6 +962,7 @@
|
|||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp2: mcasp@2b20000 {
|
||||
|
@ -800,6 +980,7 @@
|
|||
clocks = <&k3_clks 106 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cal: cal@6f03000 {
|
||||
|
@ -826,13 +1007,13 @@
|
|||
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,am65x-dss";
|
||||
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
|
||||
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
|
||||
<0x0 0x04a06000 0x0 0x1000>, /* vid */
|
||||
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
|
||||
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
|
||||
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
|
||||
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
|
||||
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
|
||||
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
|
||||
<0x0 0x04a06000 0x0 0x1000>, /* vid */
|
||||
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
|
||||
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
|
||||
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
|
||||
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
|
||||
reg-names = "common", "vidl1", "vid",
|
||||
"ovr1", "ovr2", "vp1", "vp2";
|
||||
|
||||
|
@ -840,9 +1021,9 @@
|
|||
|
||||
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
clocks = <&k3_clks 67 1>,
|
||||
<&k3_clks 216 1>,
|
||||
<&k3_clks 67 2>;
|
||||
clocks = <&k3_clks 67 1>,
|
||||
<&k3_clks 216 1>,
|
||||
<&k3_clks 67 2>;
|
||||
clock-names = "fck", "vp1", "vp2";
|
||||
|
||||
/*
|
||||
|
@ -870,6 +1051,7 @@
|
|||
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: pwm@3010000 {
|
||||
|
@ -879,6 +1061,7 @@
|
|||
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: pwm@3020000 {
|
||||
|
@ -888,6 +1071,7 @@
|
|||
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm3: pwm@3030000 {
|
||||
|
@ -897,6 +1081,7 @@
|
|||
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm4: pwm@3040000 {
|
||||
|
@ -906,6 +1091,7 @@
|
|||
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm5: pwm@3050000 {
|
||||
|
@ -915,6 +1101,7 @@
|
|||
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
icssg0: icssg@b000000 {
|
||||
|
@ -964,6 +1151,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
icssg0_iep0: iep@2e000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2e000 0x1000>;
|
||||
clocks = <&icssg0_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg0_iep1: iep@2f000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2f000 0x1000>;
|
||||
clocks = <&icssg0_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg0_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
|
@ -1055,6 +1254,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -1105,6 +1305,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
icssg1_iep0: iep@2e000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2e000 0x1000>;
|
||||
clocks = <&icssg1_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg1_iep1: iep@2f000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2f000 0x1000>;
|
||||
clocks = <&icssg1_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
|
@ -1196,6 +1408,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -1246,6 +1459,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
icssg2_iep0: iep@2e000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2e000 0x1000>;
|
||||
clocks = <&icssg2_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg2_iep1: iep@2f000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2f000 0x1000>;
|
||||
clocks = <&icssg2_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg2_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
|
@ -1337,6 +1562,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -20,13 +20,32 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
|
||||
mcu_timerio_input: pinctrl@40f04200 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0x40f04200 0x0 0x10>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x00000101>;
|
||||
};
|
||||
|
||||
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
|
||||
mcu_timerio_output: pinctrl@40f04280 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0x40f04280 0x0 0x8>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x00000003>;
|
||||
};
|
||||
|
||||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_ram: sram@41c00000 {
|
||||
|
@ -46,6 +65,7 @@
|
|||
clock-names = "fck";
|
||||
clocks = <&k3_clks 114 1>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@40300000 {
|
||||
|
@ -56,6 +76,7 @@
|
|||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi1: spi@40310000 {
|
||||
|
@ -66,6 +87,7 @@
|
|||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi2: spi@40320000 {
|
||||
|
@ -76,6 +98,7 @@
|
|||
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
|
@ -85,10 +108,11 @@
|
|||
clocks = <&k3_clks 0 2>;
|
||||
assigned-clocks = <&k3_clks 0 2>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
clock-names = "fck";
|
||||
dmas = <&mcu_udmap 0x7100>,
|
||||
<&mcu_udmap 0x7101 >;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
status = "disabled";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
|
@ -103,10 +127,11 @@
|
|||
clocks = <&k3_clks 1 2>;
|
||||
assigned-clocks = <&k3_clks 1 2>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
clock-names = "fck";
|
||||
dmas = <&mcu_udmap 0x7102>,
|
||||
<&mcu_udmap 0x7103>;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
status = "disabled";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
|
@ -114,8 +139,53 @@
|
|||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The MCU domain timer interrupts are routed only to the ESM module,
|
||||
* and not currently available for Linux. The MCU domain timers are
|
||||
* of limited use without interrupts, and likely reserved by the ESM.
|
||||
*/
|
||||
mcu_timer0: timer@40400000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x40400000 0x00 0x400>;
|
||||
clocks = <&k3_clks 35 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
mcu_timer1: timer@40410000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x40410000 0x00 0x400>;
|
||||
clocks = <&k3_clks 36 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
mcu_timer2: timer@40420000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x40420000 0x00 0x400>;
|
||||
clocks = <&k3_clks 37 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
mcu_timer3: timer@40430000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x40430000 0x00 0x400>;
|
||||
clocks = <&k3_clks 38 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,timer-pwm;
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
|
@ -126,11 +196,13 @@
|
|||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>,
|
||||
<0x0 0x28440000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg",
|
||||
"proxy_target", "cfg";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
|
@ -140,9 +212,9 @@
|
|||
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,am654-navss-mcu-udmap";
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>;
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
#dma-cells = <1>;
|
||||
|
@ -159,7 +231,54 @@
|
|||
};
|
||||
};
|
||||
|
||||
fss: fss@47000000 {
|
||||
secure_proxy_mcu: mailbox@2a480000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x0 0x2a480000 0x0 0x80000>,
|
||||
<0x0 0x2a380000 0x0 0x80000>,
|
||||
<0x0 0x2a400000 0x0 0x80000>;
|
||||
/*
|
||||
* Marked Disabled:
|
||||
* Node is incomplete as it is meant for bootloaders and
|
||||
* firmware on non-MPU processors
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can0: can@40528000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x0 0x40528000 0x0 0x400>,
|
||||
<0x0 0x40500000 0x0 0x4400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can1: can@40568000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x0 0x40568000 0x0 0x400>,
|
||||
<0x0 0x40540000 0x0 0x4400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fss: bus@47000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
@ -180,6 +299,7 @@
|
|||
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ospi1: spi@47050000 {
|
||||
|
@ -194,6 +314,7 @@
|
|||
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -243,6 +364,7 @@
|
|||
clocks = <&k3_clks 5 10>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
|
|
|
@ -12,8 +12,8 @@
|
|||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes= <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
mboxes = <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x44083000 0x1000>;
|
||||
|
@ -54,6 +54,7 @@
|
|||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
|
@ -65,6 +66,7 @@
|
|||
clock-names = "fck";
|
||||
clocks = <&k3_clks 115 1>;
|
||||
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intr_wkup_gpio: interrupt-controller@42200000 {
|
||||
|
@ -100,8 +102,4 @@
|
|||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
#include "k3-am654-industrial-thermal.dtsi"
|
||||
};
|
||||
};
|
||||
|
|
|
@ -8,9 +8,10 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM654 SoC";
|
||||
compatible = "ti,am654";
|
||||
|
@ -18,21 +19,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
i2c0 = &wkup_i2c0;
|
||||
i2c1 = &mcu_i2c0;
|
||||
i2c2 = &main_i2c0;
|
||||
i2c3 = &main_i2c1;
|
||||
i2c4 = &main_i2c2;
|
||||
i2c5 = &main_i2c3;
|
||||
ethernet0 = &cpsw_port1;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
|
@ -84,6 +70,7 @@
|
|||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
|
||||
|
|
|
@ -3,9 +3,168 @@
|
|||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am654-r5-base-board-u-boot.dtsi"
|
||||
#include "k3-am65x-binman.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
tick-timer = &mcu_timer0;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_timer0 {
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <25000000>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&vtt_supply {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_navss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_navss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_ringacc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_udmap {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
bootph-all;
|
||||
|
||||
chipid@43000014 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_vtm0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_uart0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ddr_vtt_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_uart0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_i2c0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_fss0_ospi0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_mmc0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_mmc1_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&vdd_mpu {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
bootph-all;
|
||||
|
||||
flash@0 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&scm_conf {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&fss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pru0_0 {
|
||||
remoteproc-name = "pru0_0";
|
||||
};
|
||||
|
@ -81,3 +240,37 @@
|
|||
&mcu_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA driver requires a few extra register ranges
|
||||
* which are missing for the am65x. A patch has been
|
||||
* sent and will be synced after the v6.8-rc1 linux
|
||||
* tag is published
|
||||
*/
|
||||
&main_udmap {
|
||||
reg = <0x0 0x31150000 0x0 0x100>,
|
||||
<0x0 0x34000000 0x0 0x100000>,
|
||||
<0x0 0x35000000 0x0 0x100000>,
|
||||
<0x0 0x30b00000 0x0 0x10000>,
|
||||
<0x0 0x30c00000 0x0 0x10000>,
|
||||
<0x0 0x30d00000 0x0 0x8000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt",
|
||||
"tchan", "rchan", "rflow";
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA driver requires a few extra register ranges
|
||||
* which are missing for the am65x. A patch has been
|
||||
* sent and will be synced after the v6.8-rc1 linux
|
||||
* tag is published
|
||||
*/
|
||||
&mcu_udmap {
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>,
|
||||
<0x0 0x284a0000 0x0 0x4000>,
|
||||
<0x0 0x284c0000 0x0 0x4000>,
|
||||
<0x0 0x28400000 0x0 0x2000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt",
|
||||
"tchan", "rchan", "rflow";
|
||||
};
|
||||
|
|
|
@ -10,12 +10,25 @@
|
|||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,am654-evm", "ti,am654";
|
||||
compatible = "ti,am654-evm", "ti,am654";
|
||||
model = "Texas Instruments AM654 Base Board";
|
||||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
i2c0 = &wkup_i2c0;
|
||||
i2c1 = &mcu_i2c0;
|
||||
i2c2 = &main_i2c0;
|
||||
i2c3 = &main_i2c1;
|
||||
i2c4 = &main_i2c2;
|
||||
ethernet0 = &cpsw_port1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
|
@ -73,20 +86,20 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&push_button_pins_default>;
|
||||
|
||||
sw5 {
|
||||
switch-5 {
|
||||
label = "GPIO Key USER1";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sw6 {
|
||||
switch-6 {
|
||||
label = "GPIO Key USER2";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
evm_12v0: regulator-0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
|
@ -96,7 +109,7 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_io: fixedregulator-vcc3v3io {
|
||||
vcc3v3_io: regulator-1 {
|
||||
/* Output of TPS54334 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_io";
|
||||
|
@ -107,7 +120,7 @@
|
|||
vin-supply = <&evm_12v0>;
|
||||
};
|
||||
|
||||
vdd_mmc1_sd: fixedregulator-sd {
|
||||
vdd_mmc1_sd: regulator-2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
@ -117,24 +130,53 @@
|
|||
vin-supply = <&vcc3v3_io>;
|
||||
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vtt_supply: regulator-3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ddr_vtt_pins_default>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc3v3_io>;
|
||||
gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
wkup_uart0_pins_default: wkup-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
|
||||
AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
|
||||
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
|
||||
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
|
||||
>;
|
||||
};
|
||||
|
||||
ddr_vtt_pins_default: ddr-vtt-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
|
||||
>;
|
||||
};
|
||||
|
||||
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
push_button_pins_default: push-button-pins-default {
|
||||
push_button_pins_default: push-button-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
|
||||
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
|
||||
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
|
||||
|
@ -150,13 +192,22 @@
|
|||
>;
|
||||
};
|
||||
|
||||
wkup_pca554_default: wkup-pca554-default {
|
||||
wkup_pca554_default: wkup-pca554-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
|
||||
mcu_uart0_pins_default: mcu-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
|
||||
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
|
||||
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
|
||||
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
|
||||
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
|
||||
|
@ -173,16 +224,23 @@
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_mdio_pins_default: mcu-mdio1-pins-default {
|
||||
mcu_mdio_pins_default: mcu-mdio1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
|
||||
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
|
||||
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
|
||||
|
@ -191,14 +249,14 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_i2c2_pins_default: main-i2c2-pins-default {
|
||||
main_i2c2_pins_default: main-i2c2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
|
||||
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_spi0_pins_default: main-spi0-pins-default {
|
||||
main_spi0_pins_default: main-spi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
|
||||
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
|
||||
|
@ -207,7 +265,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-pins-default {
|
||||
main_mmc0_pins_default: main-mmc0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
|
@ -224,7 +282,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
main_mmc1_pins_default: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
|
||||
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
|
||||
|
@ -237,7 +295,7 @@
|
|||
>;
|
||||
};
|
||||
|
||||
usb1_pins_default: usb1-pins-default {
|
||||
usb1_pins_default: usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
|
||||
>;
|
||||
|
@ -245,21 +303,21 @@
|
|||
};
|
||||
|
||||
&main_pmx1 {
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
main_i2c0_pins_default: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
|
||||
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
|
||||
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins_default: ecap0-pins-default {
|
||||
ecap0_pins_default: ecap0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
|
@ -269,19 +327,55 @@
|
|||
&wkup_uart0 {
|
||||
/* Wakeup UART is used by System firmware */
|
||||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@50 {
|
||||
/* AT24CM01 */
|
||||
compatible = "atmel,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
vdd_mpu: regulator@60 {
|
||||
compatible = "ti,tps62363";
|
||||
reg = <0x60>;
|
||||
regulator-name = "VDD_MPU";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1770000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
ti,enable-vout-discharge;
|
||||
};
|
||||
|
||||
gpio@38 {
|
||||
compatible = "nxp,pca9554";
|
||||
reg = <0x38>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pca9554: gpio@39 {
|
||||
compatible = "nxp,pca9554";
|
||||
reg = <0x39>;
|
||||
|
@ -296,7 +390,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
@ -310,37 +412,39 @@
|
|||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c2_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&main_spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
#size-cells = <0>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
spi-max-frequency = <48000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -381,12 +485,14 @@
|
|||
};
|
||||
|
||||
&tscadc0 {
|
||||
status = "okay";
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc1 {
|
||||
status = "okay";
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
|
@ -400,23 +506,8 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
|
@ -426,6 +517,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
|
@ -434,63 +526,24 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
|
||||
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
|
@ -501,17 +554,65 @@
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x20000>;
|
||||
};
|
||||
|
||||
partition@6a0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6a0000 0x20000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.sysfw";
|
||||
reg = <0x6c0000 0x100000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fe0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fe0000 0x20000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mdio_pins_default>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
|
@ -524,30 +625,6 @@
|
|||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg2_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -1,208 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am65x-binman.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
ethernet0 = &cpsw_port1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
spi0 = &ospi0;
|
||||
spi1 = &ospi1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
bootph-pre-ram;
|
||||
main_navss: bus@30800000 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
bootph-pre-ram;
|
||||
|
||||
mcu_navss: bus@28380000 {
|
||||
bootph-pre-ram;
|
||||
|
||||
ringacc@2b800000 {
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>,
|
||||
<0x0 0x28440000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
||||
bootph-pre-ram;
|
||||
ti,dma-ring-reset-quirk;
|
||||
};
|
||||
|
||||
dma-controller@285c0000 {
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x284c0000 0x0 0x4000>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x284a0000 0x0 0x4000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>,
|
||||
<0x0 0x28400000 0x0 0x2000>;
|
||||
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
|
||||
"tchanrt", "rflow";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
bootph-pre-ram;
|
||||
|
||||
chipid@43000014 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
bootph-pre-ram;
|
||||
k3_sysreset: sysreset-controller {
|
||||
compatible = "ti,sci-sysreset";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
bootph-pre-ram;
|
||||
|
||||
wkup_i2c0_pins_default {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
bootph-pre-ram;
|
||||
usb0_pins_default: usb0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0_pins_default {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
mcu-fss0-ospi0-pins-default {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&main_mmc0_pins_default {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&main_mmc1_pins_default {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
reg = <0x0 0x46000000 0x0 0x200000>,
|
||||
<0x0 0x40f00200 0x0 0x2>;
|
||||
reg-names = "cpsw_nuss", "mac_efuse";
|
||||
/delete-property/ ranges;
|
||||
|
||||
cpsw-phy-sel@40f04040 {
|
||||
compatible = "ti,am654-cpsw-phy-sel";
|
||||
reg= <0x0 0x40f04040 0x0 0x4>;
|
||||
reg-names = "gmii-sel";
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&fss {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
bootph-pre-ram;
|
||||
|
||||
flash@0{
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_pins_default>;
|
||||
dr_mode = "peripheral";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&scm_conf {
|
||||
bootph-pre-ram;
|
||||
};
|
|
@ -5,25 +5,12 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am654.dtsi"
|
||||
#include "k3-am654-base-board.dts"
|
||||
#include "k3-am654-base-board-u-boot.dtsi"
|
||||
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
|
||||
#include "k3-am654-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am654-evm", "ti,am654";
|
||||
model = "Texas Instruments AM654 R5 Base Board";
|
||||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &sysctrler;
|
||||
remoteproc1 = &a53_0;
|
||||
|
@ -44,51 +31,6 @@
|
|||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
vtt_supply: vtt_supply {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vtt";
|
||||
regulator-min-microvolt = <0>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
|
||||
states = <0 0x0 3300000 0x1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
timer1: timer@40400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x40400000 0x0 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <25000000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_secproxy: secproxy@28380000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
reg = <0x0 0x2a380000 0x0 0x80000>,
|
||||
<0x0 0x2a400000 0x0 0x80000>,
|
||||
<0x0 0x2a480000 0x0 0x80000>;
|
||||
reg-names = "rt", "scfg", "target_data";
|
||||
#mbox-cells = <1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
|
||||
mbox-names = "tx", "rx";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
clk_200mhz: dummy_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
@ -97,237 +39,120 @@
|
|||
};
|
||||
};
|
||||
|
||||
&secure_proxy_mcu {
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
|
||||
mbox-names = "tx", "rx";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* timer init is called as part of rproc_start() while
|
||||
* starting System Firmware, so any clock/power-domain
|
||||
* operations will fail as SYSFW is not yet up and running.
|
||||
* Delete all clock/power-domain properties to avoid
|
||||
* timer init failure.
|
||||
* This is an always on timer at 20MHz.
|
||||
*/
|
||||
&mcu_timer0 {
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
|
||||
mboxes = <&secure_proxy_mcu 8>,
|
||||
<&secure_proxy_mcu 6>,
|
||||
<&secure_proxy_mcu 5>;
|
||||
mbox-names = "tx", "rx", "notify";
|
||||
ti,host-id = <4>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
bootph-pre-ram;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
bootph-pre-ram;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
clock-frequency = <48000000>;
|
||||
/delete-property/ power-domains;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&wkup_vtm0 {
|
||||
compatible = "ti,am654-vtm", "ti,am654-avs";
|
||||
vdd-supply-3 = <&vdd_mpu>;
|
||||
vdd-supply-4 = <&vdd_mpu>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
bootph-pre-ram;
|
||||
wkup_uart0_pins_default: wkup_uart0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
|
||||
AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
|
||||
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
|
||||
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
wkup_vtt_pins_default: wkup_vtt_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
mcu_uart0_pins_default: mcu_uart0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
|
||||
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
|
||||
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
|
||||
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
|
||||
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
|
||||
AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
|
||||
AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
|
||||
AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
|
||||
AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
|
||||
AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
|
||||
AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
|
||||
AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
|
||||
AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
|
||||
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
bootph-pre-ram;
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
|
||||
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
|
||||
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
|
||||
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main_mmc0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
|
||||
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
|
||||
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
|
||||
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
|
||||
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
|
||||
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
|
||||
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
|
||||
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
|
||||
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main_mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
|
||||
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
|
||||
AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
|
||||
AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
|
||||
AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
|
||||
AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
|
||||
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
|
||||
AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&memorycontroller {
|
||||
vtt-supply = <&vtt_supply>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_vtt_pins_default>;
|
||||
};
|
||||
|
||||
/*
|
||||
* MMC is probed to pull in firmware, so any clock
|
||||
* or power-domain operation will fail as we do not
|
||||
* have the firmware running at this point. Delete the
|
||||
* power-domain properties to avoid making calls to
|
||||
* SYSFW before it is loaded. Public ROM has already
|
||||
* set it up for us anyway.
|
||||
*/
|
||||
&sdhci0 {
|
||||
clock-names = "clk_xin";
|
||||
clocks = <&clk_200mhz>;
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
/delete-property/ power-domains;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
};
|
||||
|
||||
/*
|
||||
* MMC is probed to pull in firmware, so any clock
|
||||
* or power-domain operation will fail as we do not
|
||||
* have the firmware running at this point. Delete the
|
||||
* power-domain properties to avoid making calls to
|
||||
* SYSFW before it is loaded. Public ROM has already
|
||||
* set it up for us anyway.
|
||||
*/
|
||||
&sdhci1 {
|
||||
clock-names = "clk_xin";
|
||||
clocks = <&clk_200mhz>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
/delete-property/ power-domains;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
bootph-pre-ram;
|
||||
|
||||
vdd_mpu: tps62363@60 {
|
||||
compatible = "ti,tps62363";
|
||||
reg = <0x60>;
|
||||
regulator-name = "VDD_MPU";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1770000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
<0x0 0x50000000 0x0 0x8000000>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <50000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
bootph-pre-ram;
|
||||
usb0_pins_default: usb0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
bootph-pre-ram;
|
||||
/delete-property/ clocks;
|
||||
&mcu_cpsw {
|
||||
reg = <0x0 0x46000000 0x0 0x200000>,
|
||||
<0x0 0x40f00200 0x0 0x2>;
|
||||
reg-names = "cpsw_nuss", "mac_efuse";
|
||||
/delete-property/ ranges;
|
||||
|
||||
cpsw-phy-sel@40f04040 {
|
||||
compatible = "ti,am654-cpsw-phy-sel";
|
||||
reg= <0x0 0x40f04040 0x0 0x4>;
|
||||
reg-names = "gmii-sel";
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_pins_default>;
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&scm_conf {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
|
|
@ -93,6 +93,7 @@
|
|||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
|
@ -102,6 +103,7 @@
|
|||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
|
@ -111,5 +113,10 @@
|
|||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
#include "k3-am654-industrial-thermal.dtsi"
|
||||
};
|
||||
};
|
||||
|
|
|
@ -5,6 +5,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
|
@ -30,9 +31,11 @@ int mach_cpu_init(void)
|
|||
int board_phys_sdram_size(phys_size_t *size)
|
||||
{
|
||||
const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
|
||||
const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
|
||||
u8 memcfg = dh_get_memcfg();
|
||||
|
||||
*size = (u64)memsz[memcfg] << 20ULL;
|
||||
/* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */
|
||||
*size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -9,6 +9,12 @@
|
|||
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
|
||||
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
|
||||
|
||||
typedef void (*scrub_func_t)(void);
|
||||
extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
|
||||
extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
|
||||
|
||||
u8 dh_get_memcfg(void);
|
||||
|
||||
#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
|
||||
|
||||
#endif /* __LPDDR4_TIMING_H__ */
|
||||
|
|
|
@ -14,48 +14,62 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d400030, 0x1 },
|
||||
{ 0x3d400000, 0xa1080020 },
|
||||
{ 0x3d400020, 0x1323 },
|
||||
{ 0x3d400024, 0x1c79100 },
|
||||
{ 0x3d400064, 0x710106 },
|
||||
{ 0x3d400024, 0x1b77400 },
|
||||
{ 0x3d400064, 0x6d00fc },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d400070, 0x7027fd4 },
|
||||
#else
|
||||
{ 0x3d400070, 0x7027f90 },
|
||||
#endif
|
||||
{ 0x3d400074, 0x790 },
|
||||
{ 0x3d4000d0, 0xc0030720 },
|
||||
{ 0x3d4000d4, 0xb80000 },
|
||||
{ 0x3d4000d0, 0xc00306df },
|
||||
{ 0x3d4000d4, 0xb10000 },
|
||||
{ 0x3d4000dc, 0xe40036 },
|
||||
{ 0x3d4000e0, 0x330000 },
|
||||
{ 0x3d4000e0, 0xf30000 },
|
||||
{ 0x3d4000e8, 0x660048 },
|
||||
{ 0x3d4000ec, 0x160048 },
|
||||
{ 0x3d400100, 0x1e262028 },
|
||||
{ 0x3d400104, 0x7073b },
|
||||
{ 0x3d40010c, 0xe0e000 },
|
||||
{ 0x3d400110, 0x11040a11 },
|
||||
{ 0x3d400100, 0x1d241e26 },
|
||||
{ 0x3d400104, 0x70739 },
|
||||
{ 0x3d40010c, 0xd0d000 },
|
||||
{ 0x3d400110, 0x11040911 },
|
||||
{ 0x3d400114, 0x2050e0e },
|
||||
{ 0x3d400118, 0x1010008 },
|
||||
{ 0x3d40011c, 0x502 },
|
||||
{ 0x3d400130, 0x20700 },
|
||||
{ 0x3d400134, 0xd100002 },
|
||||
{ 0x3d400138, 0x10d },
|
||||
{ 0x3d400144, 0xbb005e },
|
||||
{ 0x3d400180, 0x3a5001c },
|
||||
{ 0x3d400184, 0x2f071e5 },
|
||||
{ 0x3d400138, 0x103 },
|
||||
{ 0x3d400144, 0xb4005a },
|
||||
{ 0x3d400180, 0x384001b },
|
||||
{ 0x3d400184, 0x2d06ddd },
|
||||
{ 0x3d400188, 0x0 },
|
||||
{ 0x3d400190, 0x49b820c },
|
||||
{ 0x3d400190, 0x49f820c },
|
||||
{ 0x3d400194, 0x80303 },
|
||||
{ 0x3d4001b4, 0x1b0c },
|
||||
{ 0x3d4001b4, 0x1f0c },
|
||||
{ 0x3d4001a0, 0xe0400018 },
|
||||
{ 0x3d4001a4, 0xdf00e4 },
|
||||
{ 0x3d4001a8, 0x80000000 },
|
||||
{ 0x3d4001b0, 0x11 },
|
||||
{ 0x3d4001c0, 0x1 },
|
||||
{ 0x3d4001c0, 0x7 },
|
||||
{ 0x3d4001c4, 0x1 },
|
||||
{ 0x3d4000f4, 0x799 },
|
||||
{ 0x3d400108, 0x810191a },
|
||||
{ 0x3d400108, 0x8121b1a },
|
||||
{ 0x3d400200, 0x1f },
|
||||
{ 0x3d400208, 0x0 },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d40020c, 0x13131300 },
|
||||
#else
|
||||
{ 0x3d40020c, 0x0 },
|
||||
#endif
|
||||
{ 0x3d400210, 0x1f1f },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d400204, 0x50505 },
|
||||
{ 0x3d400214, 0x4040404 },
|
||||
{ 0x3d400218, 0x4040404 },
|
||||
#else
|
||||
{ 0x3d400204, 0x80808 },
|
||||
{ 0x3d400214, 0x7070707 },
|
||||
{ 0x3d400218, 0x7070707 },
|
||||
#endif
|
||||
{ 0x3d40021c, 0xf0f },
|
||||
{ 0x3d400250, 0x1705 },
|
||||
{ 0x3d400254, 0x2c },
|
||||
|
@ -74,7 +88,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d402050, 0x20d000 },
|
||||
{ 0x3d402064, 0xc001c },
|
||||
{ 0x3d4020dc, 0x840000 },
|
||||
{ 0x3d4020e0, 0x330000 },
|
||||
{ 0x3d4020e0, 0xf30000 },
|
||||
{ 0x3d4020e8, 0x660048 },
|
||||
{ 0x3d4020ec, 0x160048 },
|
||||
{ 0x3d402100, 0xa040305 },
|
||||
|
@ -99,7 +113,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d403050, 0x20d000 },
|
||||
{ 0x3d403064, 0x30007 },
|
||||
{ 0x3d4030dc, 0x840000 },
|
||||
{ 0x3d4030e0, 0x330000 },
|
||||
{ 0x3d4030e0, 0xf30000 },
|
||||
{ 0x3d4030e8, 0x660048 },
|
||||
{ 0x3d4030ec, 0x160048 },
|
||||
{ 0x3d403100, 0xa010102 },
|
||||
|
@ -269,7 +283,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
|
|||
{ 0x20018, 0x3 },
|
||||
{ 0x20075, 0x4 },
|
||||
{ 0x20050, 0x0 },
|
||||
{ 0x20008, 0x3a5 },
|
||||
{ 0x20008, 0x384 },
|
||||
{ 0x120008, 0x64 },
|
||||
{ 0x220008, 0x19 },
|
||||
{ 0x20088, 0x9 },
|
||||
|
@ -315,19 +329,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
|
|||
{ 0x200f6, 0x0 },
|
||||
{ 0x200f7, 0xf000 },
|
||||
{ 0x20025, 0x0 },
|
||||
{ 0x2002d, 0x0 },
|
||||
{ 0x12002d, 0x0 },
|
||||
{ 0x22002d, 0x0 },
|
||||
{ 0x2002d, 0x1 },
|
||||
{ 0x12002d, 0x1 },
|
||||
{ 0x22002d, 0x1 },
|
||||
{ 0x2007d, 0x212 },
|
||||
{ 0x12007d, 0x212 },
|
||||
{ 0x22007d, 0x212 },
|
||||
{ 0x2007c, 0x61 },
|
||||
{ 0x12007c, 0x61 },
|
||||
{ 0x22007c, 0x61 },
|
||||
{ 0x1004a, 0x500 },
|
||||
{ 0x1104a, 0x500 },
|
||||
{ 0x1204a, 0x500 },
|
||||
{ 0x1304a, 0x500 },
|
||||
{ 0x2002c, 0x0 },
|
||||
};
|
||||
|
||||
|
@ -1057,7 +1067,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
|
|||
/* P0 message block paremeter for training firmware */
|
||||
static struct dram_cfg_param ddr_fsp0_cfg[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54003, 0xe94 },
|
||||
{ 0x54003, 0xe10 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
|
@ -1067,25 +1077,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
|
|||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x36e4 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x36e4 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0xe400 },
|
||||
{ 0x54033, 0x3336 },
|
||||
{ 0x54033, 0xf336 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0xe400 },
|
||||
{ 0x54039, 0x3336 },
|
||||
{ 0x54039, 0xf336 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1107,25 +1117,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
|
|||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x84 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x84 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0x8400 },
|
||||
{ 0x54033, 0x3300 },
|
||||
{ 0x54033, 0xf300 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0x8400 },
|
||||
{ 0x54039, 0x3300 },
|
||||
{ 0x54039, 0xf300 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1147,25 +1157,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
|
|||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x84 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x84 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0x8400 },
|
||||
{ 0x54033, 0x3300 },
|
||||
{ 0x54033, 0xf300 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0x8400 },
|
||||
{ 0x54039, 0x3300 },
|
||||
{ 0x54039, 0xf300 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1176,7 +1186,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
|
|||
/* P0 2D message block paremeter for training firmware */
|
||||
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54003, 0xe94 },
|
||||
{ 0x54003, 0xe10 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
|
@ -1187,25 +1197,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
|
|||
{ 0x54010, 0x1f7f },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x36e4 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x36e4 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0xe400 },
|
||||
{ 0x54033, 0x3336 },
|
||||
{ 0x54033, 0xf336 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0xe400 },
|
||||
{ 0x54039, 0x3336 },
|
||||
{ 0x54039, 0xf336 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1695,9 +1705,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
|
|||
{ 0x400d7, 0x20b },
|
||||
{ 0x2003a, 0x2 },
|
||||
{ 0x200be, 0x3 },
|
||||
{ 0x2000b, 0x419 },
|
||||
{ 0x2000c, 0xe9 },
|
||||
{ 0x2000d, 0x91c },
|
||||
{ 0x2000b, 0x3f4 },
|
||||
{ 0x2000c, 0xe1 },
|
||||
{ 0x2000d, 0x8ca },
|
||||
{ 0x2000e, 0x2c },
|
||||
{ 0x12000b, 0x70 },
|
||||
{ 0x12000c, 0x19 },
|
||||
|
@ -1800,8 +1810,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
|
|||
|
||||
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
||||
{
|
||||
/* P0 3733mts 1D */
|
||||
.drate = 3733,
|
||||
/* P0 3600mts 1D */
|
||||
.drate = 3600,
|
||||
.fw_type = FW_1D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp0_cfg,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
|
||||
|
@ -1821,8 +1831,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
|||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
|
||||
},
|
||||
{
|
||||
/* P0 3733mts 2D */
|
||||
.drate = 3733,
|
||||
/* P0 3600mts 2D */
|
||||
.drate = 3600,
|
||||
.fw_type = FW_2D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp0_2d_cfg,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
||||
|
@ -1841,5 +1851,19 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = {
|
|||
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
||||
.ddrphy_pie = ddr_phy_pie,
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3733, 400, 100, },
|
||||
.fsp_table = { 3600, 400, 100, },
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
|
||||
{
|
||||
ddrc_inline_ecc_scrub(0x0,0x3ffffff);
|
||||
ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
|
||||
ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
|
||||
ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
|
||||
ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
|
||||
ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
|
||||
ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
|
||||
ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -14,47 +14,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d400030, 0x1 },
|
||||
{ 0x3d400000, 0xa3080020 },
|
||||
{ 0x3d400020, 0x1323 },
|
||||
{ 0x3d400024, 0x1c79100 },
|
||||
{ 0x3d400064, 0x710106 },
|
||||
{ 0x3d400024, 0x1b77400 },
|
||||
{ 0x3d400064, 0x6d00fc },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d400070, 0x7027fd4 },
|
||||
#else
|
||||
{ 0x3d400070, 0x7027f90 },
|
||||
#endif
|
||||
{ 0x3d400074, 0x790 },
|
||||
{ 0x3d4000d0, 0xc0030720 },
|
||||
{ 0x3d4000d4, 0xb80000 },
|
||||
{ 0x3d4000d0, 0xc00306df },
|
||||
{ 0x3d4000d4, 0xb10000 },
|
||||
{ 0x3d4000dc, 0xe40036 },
|
||||
{ 0x3d4000e0, 0x330000 },
|
||||
{ 0x3d4000e0, 0xf30000 },
|
||||
{ 0x3d4000e8, 0x660048 },
|
||||
{ 0x3d4000ec, 0x160048 },
|
||||
{ 0x3d400100, 0x1e262028 },
|
||||
{ 0x3d400104, 0x7073b },
|
||||
{ 0x3d40010c, 0xe0e000 },
|
||||
{ 0x3d400110, 0x11040a11 },
|
||||
{ 0x3d400100, 0x1d241e26 },
|
||||
{ 0x3d400104, 0x70739 },
|
||||
{ 0x3d40010c, 0xd0d000 },
|
||||
{ 0x3d400110, 0x11040911 },
|
||||
{ 0x3d400114, 0x2050e0e },
|
||||
{ 0x3d400118, 0x1010008 },
|
||||
{ 0x3d40011c, 0x501 },
|
||||
{ 0x3d40011c, 0x502 },
|
||||
{ 0x3d400130, 0x20700 },
|
||||
{ 0x3d400134, 0xe100002 },
|
||||
{ 0x3d400138, 0x10d },
|
||||
{ 0x3d400144, 0xbb005e },
|
||||
{ 0x3d400180, 0x3a5001c },
|
||||
{ 0x3d400184, 0x2f071e5 },
|
||||
{ 0x3d400134, 0xd100002 },
|
||||
{ 0x3d400138, 0x103 },
|
||||
{ 0x3d400144, 0xb4005a },
|
||||
{ 0x3d400180, 0x384001b },
|
||||
{ 0x3d400184, 0x2d06ddd },
|
||||
{ 0x3d400188, 0x0 },
|
||||
{ 0x3d400190, 0x49b820c },
|
||||
{ 0x3d400190, 0x49f820c },
|
||||
{ 0x3d400194, 0x80303 },
|
||||
{ 0x3d4001b4, 0x1b0c },
|
||||
{ 0x3d4001b4, 0x1f0c },
|
||||
{ 0x3d4001a0, 0xe0400018 },
|
||||
{ 0x3d4001a4, 0xdf00e4 },
|
||||
{ 0x3d4001a8, 0x80000000 },
|
||||
{ 0x3d4001b0, 0x11 },
|
||||
{ 0x3d4001c0, 0x1 },
|
||||
{ 0x3d4001c0, 0x7 },
|
||||
{ 0x3d4001c4, 0x1 },
|
||||
{ 0x3d4000f4, 0xc99 },
|
||||
{ 0x3d400108, 0x810191a },
|
||||
{ 0x3d4000f4, 0x799 },
|
||||
{ 0x3d400108, 0x8121b1a },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d400200, 0x14 },
|
||||
#else
|
||||
{ 0x3d400200, 0x17 },
|
||||
#endif
|
||||
{ 0x3d400208, 0x0 },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d40020c, 0x14141400 },
|
||||
#else
|
||||
{ 0x3d40020c, 0x0 },
|
||||
#endif
|
||||
{ 0x3d400210, 0x1f1f },
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
{ 0x3d400204, 0x50505 },
|
||||
{ 0x3d400214, 0x4040404 },
|
||||
{ 0x3d400218, 0x4040404 },
|
||||
#else
|
||||
{ 0x3d400204, 0x80808 },
|
||||
{ 0x3d400214, 0x7070707 },
|
||||
{ 0x3d400218, 0x7070707 },
|
||||
#endif
|
||||
{ 0x3d40021c, 0xf0f },
|
||||
{ 0x3d400250, 0x1705 },
|
||||
{ 0x3d400254, 0x2c },
|
||||
|
@ -73,7 +92,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d402050, 0x20d000 },
|
||||
{ 0x3d402064, 0xc001c },
|
||||
{ 0x3d4020dc, 0x840000 },
|
||||
{ 0x3d4020e0, 0x330000 },
|
||||
{ 0x3d4020e0, 0xf30000 },
|
||||
{ 0x3d4020e8, 0x660048 },
|
||||
{ 0x3d4020ec, 0x160048 },
|
||||
{ 0x3d402100, 0xa040305 },
|
||||
|
@ -83,7 +102,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d402110, 0x2040202 },
|
||||
{ 0x3d402114, 0x2030202 },
|
||||
{ 0x3d402118, 0x1010004 },
|
||||
{ 0x3d40211c, 0x301 },
|
||||
{ 0x3d40211c, 0x302 },
|
||||
{ 0x3d402130, 0x20300 },
|
||||
{ 0x3d402134, 0xa100002 },
|
||||
{ 0x3d402138, 0x1d },
|
||||
|
@ -92,13 +111,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d402190, 0x3818200 },
|
||||
{ 0x3d402194, 0x80303 },
|
||||
{ 0x3d4021b4, 0x100 },
|
||||
{ 0x3d4020f4, 0xc99 },
|
||||
{ 0x3d4020f4, 0x599 },
|
||||
{ 0x3d403020, 0x1021 },
|
||||
{ 0x3d403024, 0xc3500 },
|
||||
{ 0x3d403050, 0x20d000 },
|
||||
{ 0x3d403064, 0x30007 },
|
||||
{ 0x3d4030dc, 0x840000 },
|
||||
{ 0x3d4030e0, 0x330000 },
|
||||
{ 0x3d4030e0, 0xf30000 },
|
||||
{ 0x3d4030e8, 0x660048 },
|
||||
{ 0x3d4030ec, 0x160048 },
|
||||
{ 0x3d403100, 0xa010102 },
|
||||
|
@ -108,7 +127,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d403110, 0x2040202 },
|
||||
{ 0x3d403114, 0x2030202 },
|
||||
{ 0x3d403118, 0x1010004 },
|
||||
{ 0x3d40311c, 0x301 },
|
||||
{ 0x3d40311c, 0x302 },
|
||||
{ 0x3d403130, 0x20300 },
|
||||
{ 0x3d403134, 0xa100002 },
|
||||
{ 0x3d403138, 0x8 },
|
||||
|
@ -117,7 +136,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d403190, 0x3818200 },
|
||||
{ 0x3d403194, 0x80303 },
|
||||
{ 0x3d4031b4, 0x100 },
|
||||
{ 0x3d4030f4, 0xc99 },
|
||||
{ 0x3d4030f4, 0x599 },
|
||||
{ 0x3d400028, 0x0 },
|
||||
};
|
||||
|
||||
|
@ -268,7 +287,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
|
|||
{ 0x20018, 0x3 },
|
||||
{ 0x20075, 0x4 },
|
||||
{ 0x20050, 0x0 },
|
||||
{ 0x20008, 0x3a5 },
|
||||
{ 0x20008, 0x384 },
|
||||
{ 0x120008, 0x64 },
|
||||
{ 0x220008, 0x19 },
|
||||
{ 0x20088, 0x9 },
|
||||
|
@ -314,19 +333,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
|
|||
{ 0x200f6, 0x0 },
|
||||
{ 0x200f7, 0xf000 },
|
||||
{ 0x20025, 0x0 },
|
||||
{ 0x2002d, 0x0 },
|
||||
{ 0x12002d, 0x0 },
|
||||
{ 0x22002d, 0x0 },
|
||||
{ 0x2002d, 0x1 },
|
||||
{ 0x12002d, 0x1 },
|
||||
{ 0x22002d, 0x1 },
|
||||
{ 0x2007d, 0x212 },
|
||||
{ 0x12007d, 0x212 },
|
||||
{ 0x22007d, 0x212 },
|
||||
{ 0x2007c, 0x61 },
|
||||
{ 0x12007c, 0x61 },
|
||||
{ 0x22007c, 0x61 },
|
||||
{ 0x1004a, 0x500 },
|
||||
{ 0x1104a, 0x500 },
|
||||
{ 0x1204a, 0x500 },
|
||||
{ 0x1304a, 0x500 },
|
||||
{ 0x2002c, 0x0 },
|
||||
};
|
||||
|
||||
|
@ -1056,7 +1071,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
|
|||
/* P0 message block paremeter for training firmware */
|
||||
static struct dram_cfg_param ddr_fsp0_cfg[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54003, 0xe94 },
|
||||
{ 0x54003, 0xe10 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
|
@ -1066,25 +1081,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
|
|||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x310 },
|
||||
{ 0x54019, 0x36e4 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x36e4 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x3 },
|
||||
{ 0x54032, 0xe400 },
|
||||
{ 0x54033, 0x3336 },
|
||||
{ 0x54033, 0xf336 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0xe400 },
|
||||
{ 0x54039, 0x3336 },
|
||||
{ 0x54039, 0xf336 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1106,25 +1121,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
|
|||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x310 },
|
||||
{ 0x54019, 0x84 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x84 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x3 },
|
||||
{ 0x54032, 0x8400 },
|
||||
{ 0x54033, 0x3300 },
|
||||
{ 0x54033, 0xf300 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0x8400 },
|
||||
{ 0x54039, 0x3300 },
|
||||
{ 0x54039, 0xf300 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1146,25 +1161,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
|
|||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x310 },
|
||||
{ 0x54019, 0x84 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x84 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x3 },
|
||||
{ 0x54032, 0x8400 },
|
||||
{ 0x54033, 0x3300 },
|
||||
{ 0x54033, 0xf300 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0x8400 },
|
||||
{ 0x54039, 0x3300 },
|
||||
{ 0x54039, 0xf300 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1175,7 +1190,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
|
|||
/* P0 2D message block paremeter for training firmware */
|
||||
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54003, 0xe94 },
|
||||
{ 0x54003, 0xe10 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
|
@ -1186,25 +1201,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
|
|||
{ 0x54010, 0x1f7f },
|
||||
{ 0x54012, 0x310 },
|
||||
{ 0x54019, 0x36e4 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401a, 0xf3 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x36e4 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54020, 0xf3 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x3 },
|
||||
{ 0x54032, 0xe400 },
|
||||
{ 0x54033, 0x3336 },
|
||||
{ 0x54033, 0xf336 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0xe400 },
|
||||
{ 0x54039, 0x3336 },
|
||||
{ 0x54039, 0xf336 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
|
@ -1694,9 +1709,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
|
|||
{ 0x400d7, 0x20b },
|
||||
{ 0x2003a, 0x2 },
|
||||
{ 0x200be, 0x3 },
|
||||
{ 0x2000b, 0x419 },
|
||||
{ 0x2000c, 0xe9 },
|
||||
{ 0x2000d, 0x91c },
|
||||
{ 0x2000b, 0x3f4 },
|
||||
{ 0x2000c, 0xe1 },
|
||||
{ 0x2000d, 0x8ca },
|
||||
{ 0x2000e, 0x2c },
|
||||
{ 0x12000b, 0x70 },
|
||||
{ 0x12000c, 0x19 },
|
||||
|
@ -1799,8 +1814,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
|
|||
|
||||
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
||||
{
|
||||
/* P0 3733mts 1D */
|
||||
.drate = 3733,
|
||||
/* P0 3600mts 1D */
|
||||
.drate = 3600,
|
||||
.fw_type = FW_1D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp0_cfg,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
|
||||
|
@ -1820,8 +1835,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
|||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
|
||||
},
|
||||
{
|
||||
/* P0 3733mts 2D */
|
||||
.drate = 3733,
|
||||
/* P0 3600mts 2D */
|
||||
.drate = 3600,
|
||||
.fw_type = FW_2D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp0_2d_cfg,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
||||
|
@ -1840,5 +1855,19 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {
|
|||
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
||||
.ddrphy_pie = ddr_phy_pie,
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3733, 400, 100, },
|
||||
.fsp_table = { 3600, 400, 100, },
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
|
||||
{
|
||||
ddrc_inline_ecc_scrub(0x0,0x7ffffff);
|
||||
ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
|
||||
ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
|
||||
ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
|
||||
ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
|
||||
ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
|
||||
ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
|
||||
ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
|
@ -94,6 +95,11 @@ static int dh_imx8mp_board_power_init(void)
|
|||
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
|
||||
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
|
||||
|
||||
/* DRAM Vdd1 always FPWM */
|
||||
pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
|
||||
/* DRAM Vdd2/Vddq always FPWM */
|
||||
pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
|
||||
|
||||
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
|
||||
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
|
||||
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
|
||||
|
@ -129,8 +135,35 @@ static void spl_dram_init(void)
|
|||
}
|
||||
|
||||
ddr_init(dram_timing_info[memcfg]);
|
||||
|
||||
printf("DDR: Inline ECC %sabled\n",
|
||||
(readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
|
||||
"en" : "dis");
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
|
||||
static const scrub_func_t dram_scrub_fn[8] = {
|
||||
NULL, /* 512 MiB */
|
||||
NULL, /* 1024 MiB */
|
||||
NULL, /* 1536 MiB */
|
||||
dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */
|
||||
NULL, /* 3072 MiB */
|
||||
dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */
|
||||
NULL, /* 6144 MiB */
|
||||
NULL, /* 8192 MiB */
|
||||
};
|
||||
|
||||
void board_dram_ecc_scrub(void)
|
||||
{
|
||||
u8 memcfg = dh_get_memcfg();
|
||||
|
||||
if (!dram_scrub_fn[memcfg])
|
||||
return;
|
||||
|
||||
dram_scrub_fn[memcfg]();
|
||||
}
|
||||
#endif
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
/*
|
||||
|
|
|
@ -36,7 +36,6 @@ CONFIG_DISTRO_DEFAULTS=y
|
|||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_SPL_MAX_SIZE=0x58000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x80a00000
|
||||
|
|
|
@ -118,6 +118,8 @@ CONFIG_POWER_DOMAIN=y
|
|||
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_REGULATOR_TPS62360=y
|
||||
|
|
|
@ -21,5 +21,5 @@ CONFIG_USB_KEYBOARD=y
|
|||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_NO_FB_CLEAR=y
|
||||
CONFIG_VIDEO_SIMPLE=y
|
||||
# CONFIG_GENERATE_SMBIOS_TABLE is not set
|
||||
# CONFIG_SMBIOS is not set
|
||||
CONFIG_LMB_MAX_REGIONS=64
|
||||
|
|
|
@ -122,7 +122,6 @@ CONFIG_CMD_SYSBOOT=y
|
|||
CONFIG_CMD_UUID=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_HASH_VERIFY=y
|
||||
CONFIG_CMD_BTRFS=y
|
||||
|
@ -177,7 +176,6 @@ CONFIG_GPIO_HOG=y
|
|||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_MISC=y
|
||||
CONFIG_USB_HUB_USB251XB=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
|
|
|
@ -128,7 +128,6 @@ CONFIG_CMD_SYSBOOT=y
|
|||
CONFIG_CMD_UUID=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_HASH_VERIFY=y
|
||||
CONFIG_CMD_BTRFS=y
|
||||
|
@ -189,7 +188,6 @@ CONFIG_DM_I2C=y
|
|||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_USB_HUB_USB251XB=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
|
|
|
@ -50,7 +50,7 @@ CONFIG_CONSOLE_MUX=y
|
|||
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_MAX_SIZE=0x25000
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x96fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
|
@ -123,7 +123,6 @@ CONFIG_CMD_SYSBOOT=y
|
|||
CONFIG_CMD_UUID=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_HASH_VERIFY=y
|
||||
CONFIG_CMD_BTRFS=y
|
||||
|
@ -166,6 +165,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
|
|||
CONFIG_SPL_CLK_IMX8MP=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_IMX8M_DRAM_INLINE_ECC=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_TIMEOUT=y
|
||||
CONFIG_DFU_MMC=y
|
||||
|
@ -184,7 +184,6 @@ CONFIG_DM_I2C=y
|
|||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
|
|
|
@ -51,7 +51,7 @@ CONFIG_CONSOLE_MUX=y
|
|||
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_MAX_SIZE=0x25000
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x96fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
|
@ -125,7 +125,6 @@ CONFIG_CMD_SYSBOOT=y
|
|||
CONFIG_CMD_UUID=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_HASH_VERIFY=y
|
||||
CONFIG_CMD_BTRFS=y
|
||||
|
@ -168,6 +167,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
|
|||
CONFIG_SPL_CLK_IMX8MP=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_IMX8M_DRAM_INLINE_ECC=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_TIMEOUT=y
|
||||
CONFIG_DFU_MMC=y
|
||||
|
@ -189,7 +189,6 @@ CONFIG_I2C_MUX_PCA954x=y
|
|||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
|
|
|
@ -18,7 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
|
|||
CONFIG_SYS_I2C_MVTWSI=y
|
||||
CONFIG_SYS_I2C_SLAVE=0x7f
|
||||
CONFIG_SYS_I2C_SPEED=400000
|
||||
CONFIG_AXP305_POWER=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_AXP305_POWER=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
|
|
|
@ -1,58 +0,0 @@
|
|||
SHA1 usage:
|
||||
-----------
|
||||
|
||||
In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated.
|
||||
This SHA1 sum is used, to check, if the U-Boot Image in Flash is not
|
||||
corrupted.
|
||||
|
||||
The following command is available:
|
||||
|
||||
=> help sha1
|
||||
sha1 address len [addr] calculate the SHA1 sum [save at addr]
|
||||
-p calculate the SHA1 sum from the U-Boot image in flash and print
|
||||
-c check the U-Boot image in flash
|
||||
|
||||
"sha1 -p"
|
||||
calculates and prints the SHA1 sum, from the Image stored in Flash
|
||||
|
||||
"sha1 -c"
|
||||
check, if the SHA1 sum from the Image stored in Flash is correct
|
||||
|
||||
|
||||
It is possible to calculate a SHA1 checksum from a memoryrange with:
|
||||
|
||||
"sha1 address len"
|
||||
|
||||
If you want to store a new Image in Flash for the pcs440ep board,
|
||||
which has no SHA1 sum, you can do the following:
|
||||
|
||||
a) cp the new Image on a position in RAM (here 0x300000)
|
||||
(for this example we use the Image from Flash, stored at 0xfffa0000 and
|
||||
0x60000 Bytes long)
|
||||
|
||||
"cp.b fffa0000 300000 60000"
|
||||
|
||||
b) Initialize the SHA1 sum in the Image with 0x00
|
||||
The SHA1 sum is stored in Flash at:
|
||||
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + SHA1_SUM_POS
|
||||
for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20
|
||||
= 0xffffffe0
|
||||
for the example in RAM: 0x300000 + 0x60000 + -0x20
|
||||
= 0x35ffe0
|
||||
|
||||
note: a SHA1 checksum is 20 bytes long.
|
||||
|
||||
"mw.b 35ffe0 0 14"
|
||||
|
||||
c) now calculate the SHA1 sum from the memoryrange and write
|
||||
the calculated checksum at the right place:
|
||||
|
||||
"sha1 300000 60000 35ffe0"
|
||||
|
||||
Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum.
|
||||
|
||||
If you do a "buildman -k pcs440ep" or a "make all" to get the U-Boot image,
|
||||
which will be found in ../current/ipam390/ - the correct SHA1 sum will be
|
||||
automagically included in the U-Boot image.
|
||||
|
||||
Heiko Schocher, 11 Jul 2007
|
|
@ -74,7 +74,7 @@ For the next scheduled release, release candidates were made on::
|
|||
|
||||
* U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
|
||||
|
||||
.. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024.
|
||||
* U-Boot v2024.01-rc6 was released on Wed 03 January 2024.
|
||||
|
||||
Please note that the following dates are planned only and may be deviated from
|
||||
as needed.
|
||||
|
|
|
@ -16,7 +16,8 @@ Description
|
|||
The wget command is used to download a file from an HTTP server.
|
||||
|
||||
wget command will use HTTP over TCP to download files from an HTTP server.
|
||||
Currently it can only download image from an HTTP server hosted on port 80.
|
||||
By default the destination port is 80 and the source port is pseudo-random.
|
||||
The environment variable *httpdstp* can be used to set the destination port.
|
||||
|
||||
address
|
||||
memory address for the data downloaded
|
||||
|
|
|
@ -306,6 +306,10 @@ ethrotate
|
|||
anything other than "no", U-Boot does go through all
|
||||
available network interfaces.
|
||||
|
||||
httpdstp
|
||||
If this is set, the value is used for HTTP's TCP
|
||||
destination port instead of the default port 80.
|
||||
|
||||
netretry
|
||||
When set to "no" each network operation will
|
||||
either succeed or fail without retrying.
|
||||
|
|
|
@ -144,7 +144,7 @@ static int npcm_pspi_set_speed(struct udevice *bus, uint speed)
|
|||
if (speed > priv->max_hz)
|
||||
speed = priv->max_hz;
|
||||
|
||||
divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1);
|
||||
divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed)) - 1;
|
||||
if (divisor > MAX_DIV)
|
||||
divisor = MAX_DIV;
|
||||
|
||||
|
|
|
@ -17,6 +17,5 @@ enum wget_state {
|
|||
};
|
||||
|
||||
#define DEBUG_WGET 0 /* Set to 1 for debug messages */
|
||||
#define SERVER_PORT 80
|
||||
#define WGET_RETRY_COUNT 30
|
||||
#define WGET_TIMEOUT 2000UL
|
||||
|
|
|
@ -58,7 +58,7 @@ config NETCONSOLE
|
|||
bool "NetConsole support"
|
||||
help
|
||||
Support the 'nc' input/output device for networked console.
|
||||
See README.NetConsole for details.
|
||||
See doc/usage/netconsole.rst for details.
|
||||
|
||||
config IP_DEFRAG
|
||||
bool "Support IP datagram reassembly"
|
||||
|
|
14
net/wget.c
14
net/wget.c
|
@ -19,6 +19,9 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* The default, change with environment variable 'httpdstp' */
|
||||
#define SERVER_PORT 80
|
||||
|
||||
static const char bootfile1[] = "GET ";
|
||||
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
|
||||
static const char http_eom[] = "\r\n\r\n";
|
||||
|
@ -134,19 +137,22 @@ static void wget_send_stored(void)
|
|||
int len = retry_len;
|
||||
unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len);
|
||||
unsigned int tcp_seq_num = retry_tcp_ack_num;
|
||||
unsigned int server_port;
|
||||
uchar *ptr, *offset;
|
||||
|
||||
server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff;
|
||||
|
||||
switch (current_wget_state) {
|
||||
case WGET_CLOSED:
|
||||
debug_cond(DEBUG_WGET, "wget: send SYN\n");
|
||||
current_wget_state = WGET_CONNECTING;
|
||||
net_send_tcp_packet(0, SERVER_PORT, our_port, action,
|
||||
net_send_tcp_packet(0, server_port, our_port, action,
|
||||
tcp_seq_num, tcp_ack_num);
|
||||
packets = 0;
|
||||
break;
|
||||
case WGET_CONNECTING:
|
||||
pkt_q_idx = 0;
|
||||
net_send_tcp_packet(0, SERVER_PORT, our_port, action,
|
||||
net_send_tcp_packet(0, server_port, our_port, action,
|
||||
tcp_seq_num, tcp_ack_num);
|
||||
|
||||
ptr = net_tx_packet + net_eth_hdr_size() +
|
||||
|
@ -161,14 +167,14 @@ static void wget_send_stored(void)
|
|||
|
||||
memcpy(offset, &bootfile3, strlen(bootfile3));
|
||||
offset += strlen(bootfile3);
|
||||
net_send_tcp_packet((offset - ptr), SERVER_PORT, our_port,
|
||||
net_send_tcp_packet((offset - ptr), server_port, our_port,
|
||||
TCP_PUSH, tcp_seq_num, tcp_ack_num);
|
||||
current_wget_state = WGET_CONNECTED;
|
||||
break;
|
||||
case WGET_CONNECTED:
|
||||
case WGET_TRANSFERRING:
|
||||
case WGET_TRANSFERRED:
|
||||
net_send_tcp_packet(0, SERVER_PORT, our_port, action,
|
||||
net_send_tcp_packet(0, server_port, our_port, action,
|
||||
tcp_seq_num, tcp_ack_num);
|
||||
break;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue