Commit graph

275 commits

Author SHA1 Message Date
Tom Rini
bb20a105e9 Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_BOOT_RAMDISK_HIGH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 14:01:09 -04:00
Tom Rini
c316ee674f Xilinx changes for v2022.10
cpu:
 - Add driver for microblaze cpu
 
 net:
 - Add support for DM_ETH_PHY to AXI emac and emaclite
 
 xilinx:
 - Switch platforms to DM_ETH_PHY
 - DT chagnes in ZynqMP and Zynq
 - Enable support for SquashFS
 
 zynqmp:
 - Add support for KR260 boards
 - Move BSS from address 0
 - Move platform identification from board code to soc driver
 - Improve zynqmp_psu_init_minimize
 
 versal:
 - Enable loading app at EL1
 
 serial:
 - Setup default address and clock rates for DEBUG uarts
 
 pinctrl:
 - Add support for tri state and output enable properties
 
 relocate-rela:
 - Clean relocate-rela implementation for ARM64
 - Add support for Microblaze
 
 microblaze:
 - Add support for runtime relocation
 - Rework cache handling (wiring, Kconfig) based on cpuinfo
 - Remove interrupt support
 
 timer:
 - Extract axi timer driver from Microblaze to generic location
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Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
2022-06-27 10:15:50 -04:00
Michal Simek
aec051d813 microblaze: Remove interrupt handler
The primary purpose for this code was timer. By converting it to
CONFIG_TIMER there is no code which uses this implementation that's why
remove it. If there is a need to handle interrupts this patch can be
reverted in future.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
2022-06-24 14:16:32 +02:00
Michal Simek
a36d86720f microblaze: Convert axi timer to DM driver
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24 14:16:32 +02:00
Ovidiu Panait
816226d27e cpu: add CPU driver for microblaze
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:

U-Boot-mONStR> cpu list
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR> cpu detail
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
        ID = 0, freq = 50 MHz: L1 cache, MMU

Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
9df16c5937 microblaze: add support for handling PVR data
Add helper code for PVR (Processor Version Register) data handling. It
will be used by the UCLASS_CPU driver to populate cpuinfo fields at
runtime.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
10f6508c07 microblaze: cache: introduce flush_dcache_range()
Align microblaze with the other architectures and provide an
implementation for flush_dcache_range(). Also, remove the microblaze
exception in drivers/core/device.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
95b7a8fd12 microblaze: cache: introduce cpuinfo structure
Introduce a minimal cpuinfo structure to hold cache related info. The
instruction/data cache size and cache line size are initialized early in
the boot to default Kconfig values. They will be overwritten with data
from PVR/dtb if the microblaze UCLASS_CPU driver is enabled.

The cpuinfo struct was placed in global_data to allow the microblaze
UCLASS_CPU driver to also run before relocation (initialized global data
should be read-only before relocation).

gd_cpuinfo() helper macro was added to avoid volatile
"-Wdiscarded-qualifiers" warnings when using the pointer directly.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-10-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/)
2022-06-24 14:16:00 +02:00
Ovidiu Panait
b195134984 microblaze: cache: introduce flush_cache_all()
All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.

Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
84488fc693 microblaze: cache: introduce Kconfig options for icache/dcache sizes
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE

Also, get rid of the hardcoded value in icache_disable().

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
2022-06-24 14:16:00 +02:00
Ovidiu Panait
73b8ee62a0 microblaze: cache: split flush_cache() function
Factor out icache/dcache components from flush_cache() function. Call the
newly added __flush_icache()/__flush_dcache() functions inside
icache_disable() and dcache_disable(), respectively. There is no need to
flush both caches when disabling a particular cache type.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-7-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
8daf89678e microblaze: cache: improve icache Kconfig options
Replace CONFIG_ICACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports
the "wic" (Write to Instruction Cache) instruction. It will be used to
guard "wic" invocations in microblaze cache code.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
ef0a592ae8 microblaze: cache: improve dcache Kconfig options
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.

Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
0ad71dc53a microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHE
XILINX_USE_DCACHE macro was removed in 7556fa09e0 ("microblaze: Simplify
cache handling"), but it was still used in a couple of places.

Replace those occurences with CONFIG_DCACHE.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
130fae2dec microblaze: start.S: remove unused code
in16/out16 routines seem to not be used anywhere in microblaze code, so
remove them.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Michal Simek
d58c007498 microblaze: Add support for run time relocation
Microblaze is using NEEDS_MANUAL_RELOC from the beginnging. This is causing
issues with function pointer arrays which need to be updated manually after
relocation. Building code with -fPIC and linking with -pic will remove this
limitation and there is no longer need to run manual update.

By default still old option is enabled but by disabling NEEDS_MANUAL_RELOC
code will be compiled for full relocation.

The patch does couple of things which are connected to each other.
- Define STATIC_RELA dependency to call relocate-rela to fill sections.
- REMAKE_ELF was already enabled but u-boot file can't be used because
  sections are empty. relocate-rela will fill them and output file is
  u-boot.elf which should be used.
- Add support for full relocation (u-boot.elf)
- Add support for early relocation when u-boot.bin is loaded to different
  address then CONFIG_SYS_TEXT_BASE
- Add rela.dyn and dynsym sections

Disabling NEEDS_MANUAL_RELOC U-Boot size increased by 10% of it's original
size (550kB to 608kB).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a845670b34925859b2e321875f7588a29f6655f9.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:01 +02:00
Michal Simek
07c052be51 microblaze: Create SYM_ADDR macro to deal with symbols
Symbol handling depends on compilation flags. Right now manual relocation
is used that's why symbols can be referenced just by name and there is no
need to find them out. But when position independent code (PIC) is used
symbols need to be described differently. That's why having one macro
change is easier than changing the whole code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d704e9a267c8b536452fb999111dbfbc9d652be5.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
81169ae648 microblaze: Add comment about reset location
Better to add comment to explain why reset vector points all the time to
origin U-Boot location.
If reset happens U-Boot should start from it's origin location.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ca6341b7487708247fe2948d7e496ea6f7c2e02.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
b6fe10afe9 microblaze: Remove _start symbol handling at U-Boot start
Right now U-Boot runs all the time from the same address where it is loaded
but going to full relocation code starting address doesn't need to be fixed
and can be simply discovered from reading PC register. That's why use r20
to get PC address and subtract offset from the beginning to get starting
address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/044b727c33dfbe662f68512d0da0775a4805f360.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
986727ca11 microblaze: Remove code around r20 in relocate_code()
r20 is not used that's why remove logic around it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1b32bab5c050d099b2f6d49bc4896322ed03d788.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
3041b512eb microblaze: Optimize register usage in relocate_code
There are additional operations which can be done simpler that's why
improve logic around relocation address r7 handling and _start symbol.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8b60f72f1605c2ba6b4b7be1893d7e6ec3d8597.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
532ad5f841 microblaze: Change stack protection address to new stack address
SLR low address is still setup to 0 that's why only high limit should be
updated. STACK_SIZE macro is present and could be possible used for
low address alignment but it is not done by this patch.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c00cb843df848703b760a65934ed3ce31fafcf19.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
1918c4166e microblaze: Separate code end substraction
Follow up patch will convert symbol handling that's why it is necessary to
separate logic around symbols to special instruction. It adds 4B for new
instruction but it is worth to do it to have code ready for for full
relocation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/030863fa9a9c1ca0a9b082fe498522da09189fbc.1655299267.git.michal.simek@amd.com
2022-06-24 14:15:00 +02:00
Michal Simek
10fd6d64c7 microblaze: Enable REMAKE_ELF
Enable u-boot.elf recreation from u-boot.bin to prepare for removing manul
relocation. Enable option for big endian configuration but it is not used
too much that's why it is completely untested.
By supporting this system there is a need to define LITTLE/BIG endian
Kconfig options to pass -EL/-EB flags.

Full command line for u-boot.elf recreation looks like this:
microblazeel-xilinx-linux-gnu-objcopy -I binary -B microblaze \
 -O elf32-microblazeel u-boot.bin u-boot-elf.o

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e242a519fcd1c693b9103c5599b515af555ca43.1655299267.git.michal.simek@amd.com
2022-06-24 14:14:59 +02:00
Michal Simek
d896e790cb microblaze: Fix typo in exception.c
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c4ede6dc738c5bd7c518f3bb2c9410b15c102e20.1655299267.git.michal.simek@amd.com
2022-06-24 14:14:59 +02:00
Michal Simek
65a4da947e microblaze: Remove CONFIG_TEXT_BASE from code
Use symbol instead macro to find where U-Boot starts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d5d4c201bee6171e85b47783d916387d84db0456.1655299267.git.michal.simek@amd.com
2022-06-24 14:14:59 +02:00
Michal Simek
aa0799eb67 microblaze: Fix early stack allocation
CONFIG_SYS_INIT_SP_OFFSET macro place stack to TEXT_BASE - SYS_MALLOC_F_LEN
but there is no reason to do it now because board_init_f_alloc_reserve()
returns exact location where stack should be. That's why stack location is
calculated at run time and there is no need to hardcode it via macro. This
change will help with placing U-Boot to any address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e9aee69646e022fd8a96cbee2d2a07ab81fb6e05.1655299267.git.michal.simek@amd.com
2022-06-24 14:14:59 +02:00
Michal Simek
16a18471bb microblaze: Fix stack protection behavior
When U-Boot starts stack protection can be already enabled that's why setup
the lowest possible SLR value which is address 0. And the highest possible
stack in front of U-Boot. That's why you should never load U-Boot to the
beginning of DDR. There must be some space reserved. Code is using this
location for early malloc space, early global data and stack.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/86b9748bad12142659804d6381bc6bbf20be44f1.1655299267.git.michal.simek@amd.com
2022-06-24 14:14:59 +02:00
Michal Simek
7cf236cf1f microblaze: Switch absolute branches to relative
There is no reason to use absolute branches and use just relative. This
change helps with moving binary to different location and start it from
there.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/83a5103b85c1c2220cd3ab4d5365169c6660e40a.1655299267.git.michal.simek@amd.com
2022-06-24 14:14:59 +02:00
Andrew Scull
99e2fbcb69 linker_lists: Rename sections to remove . prefix
Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.

Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.

Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-23 12:58:18 -04:00
Tom Rini
f113d7d303 Convert CONFIG_SPL_STACK to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_STACK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:27 -04:00
Tom Rini
f83f0cb4c7 microblaze: Migrate DCACHE/ICACHE to Kconfig
Move these two options to the arch Kconfig file.

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2022-04-08 10:46:22 -04:00
Michal Simek
d7b5cc89d3 microblaze: Do not place u-boot to reserved memory location
Microblaze can also have reserved space in DT which u-boot has to avoid to
placing self to that location. The same change was done in Zynqmp by commit
ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory location").

This feature was tested with this memory description on kc705:

	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		alloc@b00000000 {
			reg = <0xb0000000 0x10000000>;
			no-map;
		};

		alloc@a8000000 {
			reg = <0xa8000000 0x00010000>;
			no-map;
		};
	};

And in U-Boot log you can check u-boot relocation address and reserved
locations.
U-Boot 2022.01-03974-gb1b4c2dea9b9 (Feb 25 2022 - 11:59:48 +0100)

Model: Xilinx MicroBlaze
DRAM:  1 GiB
Flash: 128 MiB
Loading Environment from nowhere... OK
In:    serial
Out:   serial
Err:   serial
Model: Xilinx MicroBlaze
Net:   AXI EMAC: 40c00000, phyaddr 7, interface gmii
eth0: ethernet@40c00000
U-BOOT for microblaze-generic

U-Boot-mONStR> bdi
...
DRAM bank   = 0x00000000
-> start    = 0x80000000
-> size     = 0x40000000
...
relocaddr   = 0xaff69000
...
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]	[0x80000000-0xbfffffff], 0x40000000 bytes flags: 0
 reserved.cnt  = 0x3
 reserved[0]	[0xa8000000-0xa800ffff], 0x00010000 bytes flags: 4
 reserved[1]	[0xafe87bb0-0xafffffff], 0x00178450 bytes flags: 0
 reserved[2]	[0xb0000000-0xbfffffff], 0x10000000 bytes flags: 4

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/ea0a8ccce723478eb518f6fdceb91d4f129efb68.1646122398.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Tom Rini
24b628a8f8 Xilinx changes for v2022.04-rc3
microblaze:
 - Fix exception handler
 
 zynqmp:
 - Show information about secure images
 - DT changes (som u-boot file removal)
 - Fix zynqmp_pm_cfg_obj_convert.py
 - Fix platform boot
 
 xilinx:
 - Fix bootm_size calculation
 - Remove GPIO_EXTRA_HEADER selection
 
 power:
 - Add zynqmp power management driver
 
 scsi:
 - Add phy support to ceva driver
 
 zynq qspi:
 - Fix unaligned accesses and check baudrate setup
 - Add support for spi memory operations
 
 net:
 - Fix 64bit calculation in axi_emac
 
 video:
 - Add missing gpio dependency for seps driver
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYhOKGwAKCRDKSWXLKUoM
 IQP/AJ9U6inecbFh6LWchwX1ByhHVB0NuQCeLExfpcscdJlVUtNBC8kaRrrdjVM=
 =nq1B
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
2022-02-21 08:32:02 -05:00
Ovidiu Panait
d1114b8340 microblaze: exception: fix unaligned data access register mask
The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
339f489d52 microblaze: exception: move unaligned access printfs inside switch case
The unaligned access messages are only valid in the case of an unaligned
data access exception. Do not print them for other types of hw exceptions.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-5-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
ee8161f7d1 microblaze: exception: fix return address for delay slot exceptions
According to the MicroBlaze reference manual (xilinx2021.2/ug984/page-37):
"""
If an exception is caused by an instruction in a delay slot (that is,
ESR[DS]=1), the exception handler should return execution to
the address stored in BTR instead of the normal exception return
address stored in R17.
"""

Adjust the code to print the proper return address for delay slot
exceptions.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-4-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
7422b41175 microblaze: exception: fix delay slot exception handling
The switch statement in _hw_exception_handler() only covers the
rightmost 5 bits that encode the exception cause:
switch (state & 0x1f)
{
...
}

For this reason, the "0x1000" case will never be reached, because the 13th
bit was zeroed out. To fix this, move delay slot exception handling before
the switch statement (delay slot (DS) bit in Exception Status Register is
independent of the exception cause (EC)).

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-3-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
1669b3d1a0 microblaze: exception: migrate MICROBLAZE_V5 to Kconfig
Also, rename it to XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP, since it only
covers delay slot exception support.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-2-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
4fef0a7b7e microblaze: exception: move privileged instruction exception out of v5 ifdef
The privileged instruction exception seems to have been introduced in
microblaze v7.00 along with MMU support, so having it wrapped in
MICROBLAZE_v5 ifdefs seems incorrect. Move it out of the ifdef, since all
recent microblaze versions support it.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-1-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Rasmus Villemoes
3609e1dc5f dts: automatically build necessary .dtb files
When building for a custom board, it is quite common to maintain a
private branch which include some defconfig and .dts files. But to
hook up those .dts files requires modifying a file "belonging" to
upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch
to a newer upstream then often results in a conflict which, while it
is trivial to resolve by hand, makes it harder to have a CI do "try to
build our board against latest upstream".

The .config usually includes information on precisely what .dtb(s) are
needed, so to avoid having to modify the Makefile, simply add the
files in (SPL_)OF_LIST to dtb-y.

A technicality is that (SPL_)OF_LIST is not always defined, so rework
the Kconfig symbols so that (SPL_)OF_LIST is always defined (when
(SPL_)OF_CONTROL), but only prompted for in the cases which used to be
their "depends on".

nios2 and microblaze already have something like this in their
dts/Makefile, and the rationale in commit 41f59f6853 is similar to
the above. So this simply generalizes existing practice. Followup
patches could remove the logic in those two makefiles, just as there's
potential for moving some common boilerplate from all the
arch/*/dts/Makefile files to the new scripts/Makefile.dts.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09 12:26:12 -07:00
Tom Rini
280db76f15 Pull request doc-2022-04-rc1
Replace @return by Return: in code comments.
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Merge tag 'doc-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request doc-2022-04-rc1

Replace @return by Return: in code comments.
2022-01-20 09:39:45 -05:00
Heinrich Schuchardt
185f812c41 doc: replace @return by Return:
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 18:11:34 +01:00
Ovidiu Panait
fc7220f0c4 microblaze: branch to base vector address on reset
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze using the
CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the
reset routines to branch to this location instead.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
f149ee4c36 microblaze: start.S: add support for configurable vector base address
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze, so update the
__setup_exceptions routine to work with any vector base address.

The r4 register is reserved for the vector base address inside
__setup_exceptions and the function prologe/epilogue are also updated to
save and restore r4.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-9-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
83b175be16 microblaze: migrate CONFIG_SYS_USR_EXCEP to Kconfig
Migrate CONFIG_SYS_USR_EXCEP to Kconfig. Also, rename it to
XILINX_MICROBLAZE0_USR_EXCEP in order to match the naming convention of
microblaze-generic Kconfig options.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-7-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
70c68712ef microblaze: drop CONFIG_SYS_RESET_ADDRESS macro
Microblaze is one the last two users of the CONFIG_SYS_RESET_ADDRESS
macro (the other is arch/powerpc/cpu/mpc8xx/cpu.c, but the macro is not
defined anywhere in powerpc code, so it should be removed there too).

Replace CONFIG_SYS_RESET_ADDRESS usage in start.S with
CONFIG_SYS_TEXT_BASE. If the reset address should really be
user-configurable, a new Kconfig option could be added.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
48039c333f microblaze: start.S: use stack space as scratch memory for endian offset
To simpify the code, use stack space as scratch memory for endian offset
calculation, rather than saving/restoring the first unused MB vector.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-5-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
7a971dfbeb microblaze: Kconfig: SPL dependencies fixup
Enable SPL_LIBCOMMON_SUPPORT and SPL_LIBGENERIC_SUPPORT if CONFIG_SPL=y, in
order to fix the following link failures:
common/spl/spl.o: in function `board_init_r':
common/spl/spl.c:755: undefined reference to `puts'
...
common/spl/spl.o: in function `board_init_r':
common/spl/spl.c:756: undefined reference to `hang'
common/spl/spl.c:740: undefined reference to `memset'

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-4-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
b3fe1e8ff3 microblaze: spl: add board_boot_order() implementation
Microblaze has three boot modes defined in microblaze/include/asm/spl.h,
but only booting from NOR flash is currently useable. Add a custom
board_boot_order() implementation so that RAM and SPI boot modes can also
be selected if the corresponding load-image support is present.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-3-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:02 +01:00