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microblaze: cache: introduce flush_cache_all()

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All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.

Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Ovidiu Panait 2022-05-31 21:14:30 +03:00 • committed by Michal Simek
parent 84488fc693
commit b195134984
4 changed files with 26 additions and 9 deletions
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20
arch/microblaze/cpu/cache.c
View file

@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size)
}
}
void invalidate_icache_all(void)
{
__invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
}
static void __flush_dcache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size)
}
}
void flush_dcache_all(void)
{
__flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
}
int dcache_status(void)
{
int i = 0;
@ -65,7 +75,7 @@ void icache_enable(void)
void icache_disable(void)
{
__invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
invalidate_icache_all();
MSRCLR(0x20);
}
@ -77,7 +87,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
__flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
flush_dcache_all();
MSRCLR(0x80);
}
@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size)
__invalidate_icache(addr, size);
__flush_dcache(addr, size);
}
void flush_cache_all(void)
{
invalidate_icache_all();
flush_dcache_all();
}

8
arch/microblaze/cpu/start.S
View file

@ -98,9 +98,7 @@ uboot_sym_start:
#endif
/* Flush cache before enable cache */
addik r5, r0, 0
addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
brlid r15, flush_cache
brlid r15, flush_cache_all
nop
/* enable instruction and data cache */
@ -349,9 +347,7 @@ relocate_code:
#endif
/* Flush caches to ensure consistency */
addik r5, r0, 0
addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
brlid r15, flush_cache
brlid r15, flush_cache_all
nop
2: addi r5, r31, 0 /* gd is initialized in board_r.c */

5
arch/microblaze/include/asm/cache.h
View file

@ -18,4 +18,9 @@
#define ARCH_DMA_MINALIGN 16
#endif
/**
* flush_cache_all - flush the entire instruction/data caches
*/
void flush_cache_all(void);
#endif /* __MICROBLAZE_CACHE_H__ */

2
arch/microblaze/lib/bootm.c
View file

@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
flush_cache_all();
if (!fake) {
/*