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Author SHA1 Message Date
Simon Glass
7e589bc19b x86: Add a generic Intel GPIO driver
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
74749f1e84 x86: Add a generic Intel pinctrl driver
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same
code.

Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
2206ac248a dm: pci: Allow delaying auto-config until after relocation
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.

This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Rasmus Villemoes
93ce16fd0a doc: really get rid of Documentation/ directory
Commit 656d8da9d2 (doc: Remove duplicated documentation directory) got
rid of most of Documentation/. But there's still an obviously useless
.gitignore left behind.

Also, there's a copy of the linux kernel's net/ethernet.txt binding
imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So
replace the latter by the former, and making Documentation/ finally
empty.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-13 13:01:53 -05:00
Alex Marginean
ee278acdf1 doc: bindings: Aquantia PHY node binding
A couple of optional properties have been introduced for Aquantia PHY
allowing the driver to set up wiring related configuration points that
are otherwise driven by firmware.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
e81031c2b8 doc: bindings: add bindings document for PHY nodes
It defines that PHY nodes must be children on MDIO bus nodes and defines
the only required property in U-Boot, reg.  This property along with the
example provided are copied over from Linux.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Grygorii Strashko
fb6038390e dt-bindings: phy: dp83867: Add documentation for disabling clock output
Based on commit 980066e6d964 ("dt-bindings: phy: dp83867: Add documentation
for disabling clock output") of mainline linux kernel.

The clock output is generally only used for testing and development and not
used to daisy-chain PHYs.  It's just a source of RF noise afterward.

Add a mux value for "off".  I've added it as another enumeration to the
output property.  In the actual PHY, the mux and the output enable are
independently controllable.  However, it doesn't seem useful to be able
to describe the mux setting when the output is disabled.

Document that PHY's default setting will be left as is if the property
is omitted.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Joseph Chen
11406b8f7e dm: regulator: support regulator more state
support parse regulator standard property:
regulator-off-in-suspend;
regulator-init-microvolt;
regulator-suspend-microvolt:
 regulator_get_suspend_enable
 regulator_set_suspend_enable
 regulator_get_suspend_value
 regulator_set_suspend_value

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:31:09 +08:00
Lokesh Vutla
ffb6b8e540 dt-bindings: memory-controller: Introduce J721E DDRSS bindings
Add DT binding documentation for DDR sub system present on J721E device.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
Tom Rini
0c9cc5155c Merge branch '2019-10-11-master-imports'
- Assorted cleanups
- FAT bugfixes
- mediatek platform updates
2019-10-12 10:10:59 -04:00
Tero Kristo
260777fc23 clk: cdce9xx: add support for cdce9xx clock synthesizer
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11 13:32:39 -04:00
Ryder Lee
4024006e52 dt-bindings: phy: add a document for MediaTek tphy
This adds a document for tphy which supports physical layer
functionality for a number of controllers on MediaTek SoCs,
such as, USB2.0, USB3.0, PCIe, and SATA.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11 10:10:18 -04:00
Ryder Lee
825c47ee9d dt-bindings: pcie: add a document for MT7623 PCIe controller
This adds a document for MT7623 PCIe controller.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11 10:10:18 -04:00
Suman Anna
e18fb7dd5c dt-bindings: remoteproc: Add bindings for DSP C66x clusters on TI K3 SoCs
Some Texas Instruments K3 family of SoCs have one of more Digital Signal
Processor (DSP) subsystems that are comprised of either a TMS320C66x
CorePac and/or a next-generation TMS320C71x CorePac processor subsystem.
Add the device tree bindings document for the C66x DSP devices on these
SoCs. The added example illustrates the DT nodes for the first C66x DSP
device present on the K3 J721E family of SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:34 -04:00
Suman Anna
471c2d5e22 dt-bindings: remoteproc: Add bindings for R5F subsystem on TI K3 SoCs
The Texas Instruments K3 family of SoCs have one of more dual-core
Arm Cortex R5F processor subsystems/clusters (R5FSS). Add the device
tree bindings document for these R5F subsystem devices. These R5F
processors do not have an MMU, and so require fixed memory carveout
regions matching the firmware image addresses. The nodes require more
than one memory region, with the first memory region used for DMA
allocations at runtime. The remaining memory regions are reserved
and are used for the loading and running of the R5F remote processors.

The added example illustrates the DT nodes for the single R5FSS device
present on K3 AM65x family of SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:34 -04:00
Alex Marginean
8bd37ce3cd drivers: net: add marvell MDIO driver
This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers based on driver model. There are two
reasons to have a separate driver rather than including it inside
the MAC driver itself:
  *) The MDIO interface is shared by all Ethernet ports, so a driver
     must guarantee non-concurrent accesses to this MDIO interface. The
     most logical way is to have a separate driver that handles this
     single MDIO interface, used by all Ethernet ports.
  *) The MDIO interface is the same between the existing mv643xx_eth
     driver and the new mvneta/mvpp2 driver. Even though it is for now
     only used by the mvneta/mvpp2 driver, it will in the future be
     used by the mv643xx_eth driver as well.

This driver supports SMI IEEE for 802.3 Clause 22 and XSMI for IEEE
802.3 Clause 45.

This patch also adds device tree binding for marvell MDIO driver.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04 11:37:19 -05:00
Alex Marginean
01c9f047ac doc: bindings: add mdio.txt describing generic MDIO properties
Adds a binding document for mdio.  A notable deviation from corresponding
Linux binding is the introduction of device-name optional property, which
can be used to name MDIO buses.  Two reset optional properties described
by Linux binding are also not present as they don't seem to be used in
U-Boot at this time.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-04 11:37:19 -05:00
Patrick Delaunay
17ac2150c3 dt-bindings: clock: stm32mp1: support disabled fixed clock
Add precision for disabled fixed clock in stm32mp1 binding.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 09:36:56 +02:00
Simon Glass
b4bf71456d sound: Add codec enable to the sound bindings
For U-Boot we allow a GPIO to be specified to enable the codec. Add this
to the relevant binding files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Simon Glass
9944d753cb sound: tegra: Add the binding file for tegra-audio
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Simon Glass
e070311ce8 sound: snow: Add the binding file for snow
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:33 -07:00
Heiko Schocher
49b10cb492 gpio: fixes for gpio-hog support
recently added gpio hog patch was "in discussion"
state with Simon Glass. This patch now adds most
of comments from Simon Glass.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-29 09:32:10 -04:00
Lokesh Vutla
c163af6cb8 dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:23 -04:00
Vladimir Oltean
1c8ad08674 net: tsec: Change compatible strings to match Linux
In the case of the tsec network driver, so far there has been no
mainline user of DM_ETH where the DT bindings get used.

In the case of the mdio bus, it looks like the "fsl,tsec-mdio" string
was made up for the documentation, but there is no mainline code that
parses the "compatible" property anyway.

In both cases, there are no DT blobs that contain the old strings.

So change the documentation to "fsl,etsec2" for the Ethernet ports and
"fsl,etsec2-mdio" for the MDIO buses, which are strings that Linux also
uses, at least for LS1021A.  More compatible strings can be added once
other (PowerPC) SoCs are migrated to DM_ETH.

The current ls1021a.dtsi doesn't match what was documented for the MDIO
buses anyway (the "compatible" is "gianfar" currently). This will be
fixed in the next patch.

Fixes: 69a00875e3 ("doc: dt-bindings: Describe Freescale TSEC ethernet controller")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25 13:13:31 -05:00
Alex Marginean
88d2b1abea doc: bindings: Add binding for register driven MDIO muxes
This binding documents two properties that describe the registers used to
perform MUX selection.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25 13:13:30 -05:00
Tom Rini
ff8c23e784 - add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
 - use kernel qspi compatible string for stm32
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Merge tag 'u-boot-stm32-20190723' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
- use kernel qspi compatible string for stm32
2019-07-23 14:16:21 -04:00
Patrice Chotard
a9afaa42ee doc: device-tree-bindings: alignment with v5.2-rc6 for spi-stm32-qspi.txt
Align doc/device-tree-bindings/spi/spi-stm32-qspi.txt with kernel v5.2-rc6

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-07-22 11:04:52 +02:00
Alex Marginean
20af5adf22 doc: bindings: Add description for MDIO MUX dts nodes
Adds a short bindings document describing the expected structure of a MDIO
MUX dts node.  This is based on Linux binding and the example is in fact
copied from there.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-18 16:37:13 -05:00
Tom Rini
a9a3a37f92 - syscon: add support for power off
- stm32mp1: add op-tee config
 - stm32mp1: add specific commands: stboard and stm32key
 - add stm32 mailbox driver
 - solve many stm32 warnings when building with W=1
 - update stm32 gpio driver
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Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- syscon: add support for power off
- stm32mp1: add op-tee config
- stm32mp1: add specific commands: stboard and stm32key
- add stm32 mailbox driver
- solve many stm32 warnings when building with W=1
- update stm32 gpio driver
2019-07-14 09:09:49 -04:00
Heiko Schocher
5fc7cf8c8e gpio: add gpio-hog support
add gpio-hog support. GPIO hogging is a mechanism
providing automatic GPIO request and configuration
as part of the gpio-controller's driver probe function.

for more infos see:
doc/device-tree-bindings/gpio/gpio.txt

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Michal Simek <michal.simek@xilinx.com> (zcu102)
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-13 11:11:30 -04:00
Patrick Delaunay
d3f077b349 dt-bindings: pinctrl: stm32: add new entry for package information
Add "st,package" entry. Possibles values are:
-STM32MP_PKG_AA for LFBGA448 (18*18) package
-STM32MP_PKG_AB for LFBGA354 (16*16) package
-STM32MP_PKG_AC for TFBGA361 (12*12) package
-STM32MP_PKG_AD for TFBGA257 (10*10) package

see Linux commit 966d9b928f626a54a0c27c0fdae1e3dfe9bab416
for v5.2-rc1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:18:53 +02:00
Ramon Fried
c2ccc9e5cb pci_ep: add Cadence PCIe endpoint driver
Add Cadence PCIe endpoint driver supporting configuration
of header, bars and MSI for device.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-11 10:05:15 -04:00
Breno Matheus Lima
656d8da9d2 doc: Remove duplicated documentation directory
Commit ad7061ed74 ("doc: Move device tree bindings documentation to
 doc/device-tree-bindings") moved all device tree binding documentation
to doc/device-tree-bindings directory.

The current U-Boot project still have two documentation directories:

- doc/
- Documentation/

Move all documentation and sphinx files to doc directory so all content
can be in a common place.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-06-20 10:57:08 -04:00
Tom Rini
866a78dc28 - Add various STM32MP1 fixes for serial, env, clk, board, i2c ...
- Add STM32MP1 DDR driver update:
 	These update introduce the DDR interactive mode described in:
 	https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode
 
 	This mode is used by the CubeMX: DDR tuning tool.
 	https://wiki.st.com/stm32mpu/index.php/STM32CubeMX
 
 	The DDR interactive mode is NOT activated by default because
 	it increase the SPL size and slow down the boot time
 	(200ms wait added).
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Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot

- Add various STM32MP1 fixes for serial, env, clk, board, i2c ...

- Add STM32MP1 DDR driver update:
	These update introduce the DDR interactive mode described in:
	https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode

	This mode is used by the CubeMX: DDR tuning tool.
	https://wiki.st.com/stm32mpu/index.php/STM32CubeMX

	The DDR interactive mode is NOT activated by default because
	it increase the SPL size and slow down the boot time
	(200ms wait added).
2019-05-24 08:13:27 -04:00
Angelo Dureghello
b5867b1a7a m68k: add basic set of devicetrees
This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).

Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-23 23:14:38 -04:00
Patrick Delaunay
53bb831658 stm32mp1: ram: update parameter array initialization
Force alignment of the size of parameters array with
the expected value in the binding, that allows compilation
error when the array size change.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23 11:38:10 +02:00
Patrick Delaunay
c60fed14f6 stm32mp1: ram: change ddr speed to kHz
Allow fractional support in DDR tools.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23 11:38:10 +02:00
Patrick Delaunay
3351768ef9 stm32mp1: update RCC binding after kernel realignment
RCC is no more a mfd and add a complete example
and alignment with latest TF-A binding

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23 11:36:46 +02:00
Tien Fong Chee
5c2ae96b60 ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:10 +02:00
James Byrne
83f71ef558 net: phy: micrel: Use correct skew values on KSZ9021
Commit ff7bd212cb ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.

The preceding commit c16e69f702 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).

This commit sorts out the resulting confusion in a consistent way by
making the following changes:

- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.

- Update the Micrel PHY driver to select the appropriate divisor for
both parts.

- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08 17:27:01 -05:00
Philippe Reynes
d00c6a2d56 led: add initial support for bcm6858
The driver add the support of the led IP on bcm6858.
This led IP can drive up to 32 leds, and can handle
blinking.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-22 18:13:24 -04:00
Patrick Delaunay
6fe7dd3327 stm32mp1: add stusb1600 support for DK1 and DK2 board
The DK1 and DK2 boards use the USB Type-C controller STUSB1600.
This patch updates:
- the device tree to add the I2C node in the DT
- the board stm32mp1 to probe this I2C device and use this controller
  to check cable detection.
- the DWC2 driver to support a new dt property
  "u-boot,force-b-session-valid" which forces B session and
  device mode; it is a workaround because the VBUS sensing and
  ID detection isn't available with stusb1600.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21 10:26:52 +02:00
Patrick Delaunay
931e9d7aa7 usb: dwc2: add support for STM32MP1
Add compatible "st,stm32mp1-hsotg" and associated driver data to manage
the usb33d-supply and the ST specific register for VBus sensing.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
# Conflicts:
#	drivers/usb/gadget/dwc2_udc_otg.c
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21 10:26:52 +02:00
Patrick Delaunay
c791c8431c usb: dwc2: convert driver to DM_USB_GADGET
Minimal conversion to driver model by using the uclass
UCLASS_USB_GADGET_GENERIC based on:
- reset uclass
- clock uclass
- generic uclass.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21 10:26:51 +02:00
Patrick Delaunay
c50151d43f phy: usbphyc: Binding update of vdda supply
Move supply vdda1v1 and vdda1v8 in usbphyc node and
no more in port

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Eugeniy Paltsev
15736e288e ARC: dwmmc: Adding DesignWare MMC driver support for ARC devboards
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys
ARC devboards. It is created to switch ARC devboards to use DM_MMC.

It required information such as clocks (Bus Interface Unit clock,
Card Interface Unit clock) and SDIO bus width.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-04-18 09:12:38 +03:00
Tom Rini
216800acf1 Merge branch 'master' of git://git.denx.de/u-boot-spi
Conflicts:
	arch/arm/dts/armada-385-amc.dts
	arch/arm/dts/armada-xp-theadorable.dts
	arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-14 00:03:06 -04:00
Tom Rini
015289580f stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
 - stm32mp1 dts files sync'ed with Linux version
 - add STM32MP1 Discovery boards (DK1 and DK2)
 - add STMFX gpio expander driver
 - misc improvement for stm3mp1 supports
 - rename stpmu1 to stpmic1 (official name)
 - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
 - add STM32 FMC2 NAND flash controller driver
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Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-boot

stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
- stm32mp1 dts files sync'ed with Linux version
- add STM32MP1 Discovery boards (DK1 and DK2)
- add STMFX gpio expander driver
- misc improvement for stm3mp1 supports
- rename stpmu1 to stpmic1 (official name)
- stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
- add STM32 FMC2 NAND flash controller driver
2019-04-12 15:43:19 -04:00
Christophe Kerello
6899385f41 dt-bindings: mtd: stm32_fmc2: add STM32 FMC2 NAND controller documentation
This patch adds the documentation of the device tree bindings for the STM32
FMC2 NAND controller.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Neil Armstrong
5991d0e36d doc: device-tree-bindings: switch from spi-flash to jedec, spi-nor
Since all DTS files has been switched to "jedec,spi-nor", remove
the "spi-flash" compatible from the bindings examples.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Lukasz Majewski
a40fe217d1 DM: I2C: Introduce 'u-boot, i2c-transaction-bytes' property
The 'u-boot,i2c-transaction-bytes' device tree property provides
information regarding number of bytes transferred by a device in a
single transaction.

This change is necessary to avoid hanging devices after soft reset.
One notable example is communication with MC34708 device:

1. Reset when communicating with MC34708 via I2C.

2. The u-boot (after reboot -f) tries to setup the I2C and then calls
force_idle_bus. In the same time MC34708 still has some data to be sent
(as it transfers data in 24 bits chunks).

3. The force_idle_bus() is not able to make the bus idle as 8 SCL
clocks may be not enough to have the full transmission.

4. We end up with I2C inconsistency with MC34708.

This PMIC device requires 24+ SCL cycles to make finish any pending I2C
transmission.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-11 15:21:33 +02:00
Krzysztof Kozlowski
e66d1cb3c2 regulator: Add support for ramp delay
Changing voltage and enabling regulator might require delays so the
regulator stabilizes at expected level.

Add support for "regulator-ramp-delay" binding which can introduce
required time to both enabling the regulator and to changing the
voltage.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Patrick Delaunay
3a29afcbbf doc: binding: rename directory ram to memory-controller
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller

PS: the drivers using RAM u-class should be associated with
    this binding directory

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-28 14:21:46 -05:00
Anup Patel
b630d57d0a clk: Add fixed-factor clock driver
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 09:12:33 +08:00
Simon Glass
2ca471379b sound: Add support for Intel HDA
The Intel High-definition Audio is a newer-generation audio system which
provides for transfer of a large number of audio stream, each containing
up to 16 channels.

Add support for HDA as a library which can be used by other drivers.
U-Boot currently uses only two channels (stereo).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Patrick Delaunay
bbd108a082 clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Lars Povlsen
2a48c15d2e mips: mscc_sgpio: Add DT bindings documentation
This add device tree binding documentation for the MSCC serial GPIO
driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-16 13:56:43 +01:00
Martin Fuzzey
a2e99a71b2 w1: Add driver for i.MX bus master controller
Two variants of controllers are supported:
V1 (bitwise only) found in
	i.MX21, i.MX27, i.MX31, i.MX51
V2 (byte operations) found in
	i.MX25, i.MX35, i.MX50, i.MX53

Only tested on i.MX53 hardware but in both modes
(by modifying the device tree).

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
2019-01-01 14:12:18 +01:00
Philipp Tomsich
dfb0a70a1a power: add FAN53555 family support
This adds a driver for the FAN53555 family of regulators and wraps it
in a PMIC implementation.

While these devices support a 'normal' and 'suspend' mode (controlled
via an external pin) to switch between two programmable voltages, this
incarnation of the driver assumes that the device is always operating
in 'normal' mode.

Only setting/reading the programmed voltage is supported at this time
and the following device functionality remains unsupported:
  - switching the selected voltage (via a GPIO)
  - disabling the voltage output via software-control
This matches the functionality of the Linux driver.

Tested on a RK3399-Q7 (with 'option 5' devices): setting voltages from
the U-Boot shell and verifying output voltages on the board.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-12-10 10:04:45 +01:00
Philipp Tomsich
ebb73de168 bootcount: add uclass for bootcount
The original bootcount methods do not provide an interface to DM and
rely on a static configuration for I2C devices (e.g. bus, chip-addr,
etc. are configured through defines statically).  On a modern system
that exposes multiple devices in a DTS-configurable way, this is less
than optimal and a interface to DM-based devices will be desirable.

This adds a simple driver that is DM-aware and configurable via DTS.
If ambiguous (i.e. multiple bootcount-devices are present) the
/chosen/u-boot,bootcount-device property can be used to select one
bootcount device.

Initially, this provides support for the following DM devices:
 * RTC devices

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-12-10 10:04:44 +01:00
Simon Goldschmidt
2a3a99932b spi: cadence_qspi: use "cdns,qspi-nor" as compatible
Linux uses "cdns,qspi-nor" as compatible string for the cadence
qspi driver, so change driver, docs and all device trees.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Lokesh Vutla
06bda1259f ram: Introduce K3 AM654 DDR Sub System driver
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-16 16:51:58 -05:00
Martin Fuzzey
f9c87adc47 w1-eeprom: Add support for Maxim DS2502 add only memory
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
2018-11-16 16:51:55 -05:00
Stefan Roese
c895ef4650 net: Add MT7628 ethernet driver
This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Janine Hagemann
0f347a0096 net: phy: ti: Add binding for the CLK_OUT pin muxing
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:54 -05:00
Janine Hagemann
fba725f410 net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver
This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping
support in the DP83867 TI's PHY driver") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:53 -05:00
Jens Wiklander
53b6aac7b1 dt/bindings: add bindings for optee
Sync with c8bfafb15944 ("dt/bindings: add bindings for optee")
from Linux kernel.

Introduces linaro prefix and adds bindings for ARM TrustZone based OP-TEE
implementation.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:47:38 -04:00
Tom Rini
592cd5defd Merge branch 'master' of git://git.denx.de/u-boot-spi
This is the PR for SPI-NAND changes along with few spi changes.

[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-02 17:01:46 -04:00
Tom Rini
b592936d35 Merge branch 'master' of git://git.denx.de/u-boot-video
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-29 22:28:44 -04:00
Eugen Hristev
6a984d66b1 dt-bindings: w1-eeprom: eep_sandbox: create bindings
Bindings for sandbox onewire eeprom driver

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:36 -04:00
Eugen Hristev
0fb667ae19 dt-bindings: w1-eeprom: ds24xxx: create bindings
Bindings for Maxim's ds24 onewire EEPROM families driver

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:36 -04:00
Eugen Hristev
e1721ba0e6 dt-bindings: W1: w1-gpio: added bindings for w1-gpio
Added bindings specification for bitbanged gpio driver for Dallas
one wire protocol

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:34 -04:00
Tien Fong Chee
fc5ca3ab54 doc: dtbinding: Add file system firmware loader binding document
Add a document to describe file system firmware loader binding
information.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-28 20:22:33 -04:00
Mario Six
9671f696e5 video_osd: Add ihs_video_out driver
Add a driver for IHS OSDs on IHS FPGAs.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-28 18:26:44 +02:00
Philippe Reynes
b3f8e88f3c pinctrl: bcm6838: add pinctrl support
Add pinctrl support for broadcom bcm6838 SoC.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-22 20:49:59 +02:00
Boris Brezillon
0fa1fc43c8 dt-bindings: Add bindings for SPI NAND devices
Add bindings for SPI NAND chips.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Lokesh Vutla
c365ed7d4b remoteproc: Introduce K3 remoteproc driver
Add support for K3 based remoteproc driver that
communicates with TISCI to start start a remote processor.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
1ad190bf59 remoteproc: Introduce K3 system controller
K3 specific SoCs have a dedicated microcontroller for doing
resource management. Any HLOS/firmware on compute clusters should
load a firmware to this microcontroller before accessing any resource.
Adding support for loading this firmware.

After the K3 system controller got loaded with firmware and started
up it sends out a boot notification message through the secure proxy
facility using the TI SCI protocol. Intercept and receive this message
through the rproc start operation which will need to get invoked
explicitly after the firmware got loaded.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
f9aa41023b mailbox: Introduce K3 Secure Proxy Driver
Secure Proxy module manages hardware threads that are meant
for communication between the processor entities. Adding
support for this driver.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-09-11 08:32:55 -04:00
Andreas Dannenberg
694b052401 sysreset: Add TI System Control Interface (TI SCI) sysreset driver
Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.

This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Andreas Dannenberg
1a88a04e9f power domain: Introduce TI System Control Interface (TI SCI) power domain driver
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a power domain driver that communicates to the system
controller over the TI SCI protocol for performing power management of
various devices present on the SoC. Various power domain functionalities
are achieved by the means of different TI SCI device operations provided
by the TI SCI framework.

This code is loosely based on the drivers/soc/ti/ti_sci_pm_domains.c
driver of the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Andreas Dannenberg
e585bef17f clk: Introduce TI System Control Interface (TI SCI) clock driver
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Andreas Dannenberg
65c8a79811 reset: Introduce TI System Control Interface (TI SCI) reset driver
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management of
various devices present on the SoC. Various reset functionalities are
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/reset/reset-ti-sci.c driver of
the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
32cd25128b firmware: Add basic support for TI System Control Interface (TI SCI) protocol
Texas Instrument's System Control Interface (TI SCI) message protocol is
used in Texas Instrument's System on Chip (SoC) such as those in the K3
family AM654 SoC to communicate between various compute processors with
a central system controller entity.

The TI SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC using the
mailbox client.

This is mostly derived from the TI SCI driver in Linux located at
drivers/firmware/ti_sci.c.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-09-11 08:32:55 -04:00
Peng Fan
39dd00fc5d drivers: regulator: fixed: add u-boot, off-on-delay-us
Add u-boot,off-on-delay-us for fixed regulator.

Depends on board design, the gpio regulator sometimes
connects with a big capacitance. When need to off, then
on the regulator, if there is no enough delay,
the voltage does not drop to 0, so introduce this
property to handle such case.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-19 20:38:39 -04:00
Fabrice Gasnier
fb4e674a4b dt-bindings: Document STM32 ADC DT bindings
This patch adds documentation of device tree bindings for the STM32 ADC.
It's based on linux-v4.18-rc* dt-bindings, at the time of writing:
- Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-03 19:53:10 -04:00
Eugeniy Paltsev
7620ec4df6 CREG GPIO: add device tree bindings
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Breno Lima
ad7061ed74 doc: Move device tree bindings documentation to doc/device-tree-bindings
Currently the U-Boot project contains 2 documentation directories:

- doc/
- Documentation/

The Documentation directory only contains device tree bindings related
content, so move the 3 files to doc/device-tree-bindings/.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2018-07-24 09:25:23 -04:00
Philipp Tomsich
2aa4abc1bd spl: document 'chosen/u-boot, spl-boot-device'
To let the full U-Boot know where it was booted from (i.e. which of
the entries in /chosen/u-boot,spl-boot-order' contained a valid
image), we define (and document) /chosen/u-boot,spl-boot-device as the
property that could/should automatically be injected by SPL.

This commit only contains a documentation change, which documents the
new property and the intended usage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Patrick Delaunay
d219415544 stm32mp1: clk: support digital bypass
HSE and LSE bypass shall support both analog and digital signals.
This patch add a way to select digital bypas case in the device tree
and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register
during clock tree initialization.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:07 -04:00
Michael Pratt
90c08fa038 fdt: Add device tree memory bindings
Support a default memory bank, specified in reg, as well as
board-specific memory banks in subtree board-id nodes.

This allows memory information to be provided in the device tree,
rather than hard-coded in, which will make it simpler to handle
similar devices with different memory banks, as the board-id values
or masks can be used to match devices.

Signed-off-by: Michael Pratt <mpratt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2018-07-09 09:11:00 -06:00
Bin Meng
51050ff0a2 x86: irq: Support discrete PIRQ routing registers via device tree
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Tom Rini
809e0e398a Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-06-04 08:55:00 -04:00
Evan Wang
f246648d37 mvebu: pinctrl: sync compatible string with Linux 4.17-rc4
For pinctrl driver of mvebu, the compatible strings
supported are defined differently from Linux version.
The patch aligned the compatible string with
Linux 4.17-rc4.

Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29 08:33:05 +02:00
Jagan Teki
85187b8073 device-tree-bindings: phy: Sync sun4i-usb-phy bindings
Sync sun4i-usb-phy bindings from Linux, since the
drivers/phy/allwinner/phy-sun4i-usb.c follow similar.

Sync changes from Linux with below commit:
"phy: sun4i-usb: add support for R40 USB PHY"
(sha1: f3d96f8d23d8e6d0b7642ee946b9b2ac3418fb4d)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Miquel Raynal
31b106fc1c doc: device-tree-bindings: add Sandbox TPMv2.0 module info
Add Sandbox TPMv2.0 module bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:00 -04:00
Miquel Raynal
8ee59472cb doc: device-tree-bindings: add TIS TPMv2.0 SPI module info
Add TIS TPMv2.0 SPI module bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:59 -04:00
Fabrice Gasnier
93cf0ae775 power: regulator: Add support for stm32-vrefbuf
Add regulator driver for STM32 voltage reference buffer which can be
used as voltage reference for ADCs, DACs and external components through
dedicated VREF+ pin.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:39 -04:00
Alexander Kochetkov
df8dcac8a3 dm: i2c: dts: Add gpios and pinctrl device tree properties
The commit describe usage of gpios and pinctrl device tree
properties in order to enable gpio-based software deblocking.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
2018-04-11 11:34:17 +02:00
Ken Ma
65b2e66881 doc: a37xx: Introduce pinctrl device tree binding
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30 12:52:48 +02:00
Patrick Delaunay
266fa4df00 clk: stm32mp1: add clock tree initialization
add binding and code for clock tree initialization from device tree

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:22 -04:00
Patrick Delaunay
e70f70aa65 ram: stm32mp1: add driver
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:21 -04:00
Jason Rush
c58f300628 dts: cadence_spi: Update documentation for DT bindings
Update documentation to reflect adopting the Linux DT bindings.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-01-24 12:07:50 +05:30
Miquel Raynal
32466c445c doc: bindings: soft-spi: update documentation to match the code
Linux bindings have been introduced in the code (removing the U-Boot
specific ones) without documentation update. Compatible string has
changed, as well as the four GPIO properties. Reflect this by updating
the soft-spi.txt documentation.

Fixes: 102412c415 ("dm: spi: soft_spi: switch to use linux compatible string")
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-10 12:06:15 +05:30
Felix Brack
bf802f5d54 power: extend prefix match to regulator-name property
This patch extends pmic_bind_children prefix matching. In addition to
the node name the property regulator-name is used while trying to match
prefixes. This allows assigning different drivers to regulator nodes
named regulator@1 and regulator@10 for example.
I have discarded the idea of using other properties then regulator-name
as I do not see any benefit in using property compatible or even
regulator-compatible. Of course I am open to change this if there are
good reasons to do so.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-12-12 19:53:45 -07:00
Eugeniy Paltsev
e80dac0ab8 ARC: clk: introduce HSDK CGU clock driver
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11 11:36:23 +03:00
Philipp Tomsich
ae0d33a729 rockchip: rk3399-puma: add code to allow forcing a power-on reset
The reset circuitry in the RK3399 only resets 'almost all logic' when
a software reset is performed.  To make our software maintenance
easier in the future, we want to have the option (controlled by a DTS
property) to force all reset causes other than a power-on reset to
trigger a power-on reset via a GPIO trigger.

This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7)
board-support and the documentation for the new property
(sysreset-gpio) within the /config-node.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 22:59:54 +01:00
Rick Chen
872cd42e70 dt-bindings: spi: Add andestech atcspi200 spi binding doc
Add a document to describe Andestech atcspi200 spi and
binding information.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 09:45:29 +08:00
Rick Chen
410d129e8c dt-bindings: timer: Add andestech atcpit100 timer
Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30 09:39:12 +08:00
Tien Fong Chee
772f8765d7 ARM: socfpga: add bindings doc for arria10 fpga manager
This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113

Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-By: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2017-11-26 02:34:10 +01:00
Faiz Abbas
8502f9f6d7 thermal: ti-bandgap: Add support for temperature sensor
The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-21 08:03:38 -05:00
Jorge Ramirez-Ortiz
c9e87ba665 env: Save environment at the end of an MMC partition
Allow the platform to define a partition by name at the end of which
the environment data will be located.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-11-17 07:44:13 -05:00
Felix Brack
bd2259e3c4 doc: Fix statements on case sensitivity for regulator prefix
The regulator bindings state that regulator prefixes are allowd to be
in upper or lower case. However pmic_bind_children from pmic_uclass uses
strncmp to compare DT node name against prefix. This comparison is case
sensitive hence the regulator driver prefix case matters.

Signed-off-by: Felix Brack <fb@ltec.ch>
2017-10-06 11:28:17 -04:00
Philipp Tomsich
80e9f88e67 rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-order
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on.  To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.

This commit adds:
 - documentation for the new board_spl_was_booted_from() function that
   individual SoCs/boards should provide, if they can determine where
   the SPL was booted from
 - implements the new board_spl_was_booted_from() stub function
 - adds support for handling the 'same-as-spl' specifier and calling
   into the per-SoC/per-board support code.

This also updates the documentation for the 'u-boot,spl-boot-order'
property.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Patrice Chotard
23a0641685 dm: reset: add stm32 reset driver
This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:01 -04:00
Patrice Chotard
4c3aebd56a dm: clk: add clk driver support for stm32h7 SoCs
This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:40:01 -04:00
Patrice Chotard
40d1a31e63 usb: dwc3: Add dwc3 glue driver support for STi
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.

Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:59 -04:00
Patrice Chotard
b7ca56dcda usb: phy: Add STi USB2 PHY
This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22 07:39:57 -04:00
Patrice Chotard
4fadcaf097 i2c: add i2c driver for stm32
Add i2c driver which can be used on both STM32F7 and STM32H7.
This I2C block supports the following features:
 _ Slave and master modes
 _ Multimaster capability
 _ Standard-mode (up to 100 kHz)
 _ Fast-mode (up to 400 kHz)
 _ Fast-mode Plus (up to 1 MHz)
 _ 7-bit and 10-bit addressing mode
 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
 _ All 7-bit addresses acknowledge mode
 _ General call
 _ Programmable setup and hold times
 _ Easy to use event management
 _ Optional clock stretching
 _ Software reset

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-23 07:04:40 +02:00
Philipp Tomsich
403e9cbcd5 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Patrice Chotard
f303aaf21b ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:15 -04:00
Bin Meng
f8f291b096 x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05 08:55:22 +08:00
Bin Meng
5e74e5a682 x86: baytrail: Use macros instead of magic numbers for FSP settings
Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05 08:55:22 +08:00
Bin Meng
6702488cfa x86: baytrail: Remove "serial-debug-port-*" settings
"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05 08:55:22 +08:00
Philipp Tomsich
de59d10cd0 doc: document u-boot, mmc-env-offset and u-boot, mmc-env-offset-redund
Adding documentation on the new config properties:
       'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
       'u-boot,mmc-env-offset-redundant'
                               - overrides CONFIG_ENV_OFFSET_REDUND

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-05-29 17:28:52 +09:00
Philipp Tomsich
f222b36751 doc: document /config/u-boot, spl-payload-offset property
This adds documentation on the u-boot,spl-payload-offset property
(which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in
the SPL stage, if present).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-11 22:03:40 -04:00
Tom Rini
1f5541c881 Merge git://git.denx.de/u-boot-rockchip
This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.
2017-05-10 17:40:11 -04:00
Kever Yang
1df7ee573e doc: dtbinding: add pwm binding file
This is a copy from kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Álvaro Fernández Rojas
632889cfe5 dm: led: add BCM6358 led driver
This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
28300dc526 dm: led: add BCM6328 led driver
This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c,
simplified to remove HW leds and blink fallbacks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Vikas Manocha
fd198ee1a8 ARM: DT: stm32f7: add sdram pin contol node
Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:03 -04:00
Songjun Wu
e6a419c5f7 at91: video: DT binding for HLCDC driver
DT binding documentation for atmel HLCDC driver.

Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
2017-04-14 15:42:42 +02:00
Philipp Tomsich
d02d11f8ae rockchip: rk3399: spl: make SPL boot-order configurable via /chosen
The RK3399 does not have any boot selection pins and the BootROM probes
the boot interfaces using the following boot-order:
    1. SPI
    2. eMMC (sdhci in DTS)
    3. SD card (sdmmc in DTS)
    4. USB loader
For ease of deployment, the SPL stage should mirror the boot order of
the ROM and use the same probing order (assuming that valid images can
be detected by SPL) unless instructed otherwise.  The boot-order can
then be configured via the 'u-boot,spl-boot-order' property in the
chosen-node of the DTS.

While this approach is easily extensible to other boards, it is only
implemented for the RK3399 for now, as the large SRAM on the RK3399
makes this easy to fit the needed infrastructure into SPL and our
production setup already runs with DM, OF_CONTROL and BLK in SPL.

The new boot-order property is expected to be used in conjunction with
FIT images (and all legacy image formats disabled via Kconfig).

A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Hannes Schmelzer
db40c1aa1c drivers/net/phy: add fixed-phy / fixed-link support
This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).

For this purpose we introduce a new phy-driver, called "Fixed PHY".

Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.

Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).

During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-03-26 09:58:26 -05:00
Tom Rini
5cf618ee60 Merge git://git.denx.de/u-boot-arc
This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit Timer's clock from CPU's clock s they really run
synchronously.
2017-03-24 08:19:30 -04:00
Vlad Zakharov
ad9b5f77df drivers: timer: Introduce ARC timer driver
This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-24 14:20:55 +03:00
Konstantin Porotchkin
81192b7966 mvebu: usb: xhci: Add VBUS regulator supply to the host driver
The USB device should linked to VBUS regulator through "vbus-supply"
DTS property.
This patch adds handling for "vbus-supply" property inside the USB
device entry for turning on the VBUS regulator upon the host adapter probe.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:45:25 +01:00
Konstantin Porotchkin
130b53ec79 mvebu: pcie: Add support for GPIO reset for PCIe device
Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:45:25 +01:00
Philipp Tomsich
e7dd02e377 part_efi: document device-tree binding for part_efi configuration
This adds documentation on the u-boot,efi-partition-entries-offset
property (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if
present).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-20 18:04:40 -04:00
Philipp Tomsich
399f3afa37 doc: move documentation for /config node into a separate file
This moves the description of the /config node from README.fdt-control
into a separate file doc/device-tree-bindings/config.txt.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-20 18:04:35 -04:00
Tom Rini
f9515756b6 Merge git://git.denx.de/u-boot-rockchip
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
2017-03-17 14:15:17 -04:00
Vikas Manocha
94d5308412 PINCTRL: stm32f7: add pin control driver
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-17 14:15:14 -04:00
Vikas Manocha
712f99a5dd clk: stm32f7: add clock driver for stm32f7 family
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-17 14:15:12 -04:00
Kever Yang
fa437430ad rockchip: arm64: rk3399: add ddr controller driver
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Added rockchip: tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:45 -06:00
Michael Kurz
b1a8de7e07 ARM: DTS: stm32: add stm32f746-disco device tree files
This patch adds the DTS source files needed for stm32f746-disco board
The files are based on the stm32f429/469 files from current linux
kernel.

Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi"

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-01-28 14:04:42 -05:00
Vignesh R
bd2e9714c8 regulator: fixed: Add support to handle enable-active-high DT property
Add support to handle enable-active-high DT property. This property is
used to drive the gpio controlling fixed regulator as active high when
claiming gpio line.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-12-27 08:22:57 -05:00
Konstantin Porotchkin
f99386c5b1 arm64: mvebu: Add pin control nodes to A8K family DTS files
Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Konstantin Porotchkin
656e6cc86b arm64: mvebu: pinctrl: Add pin control driver for A8K family
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Fabian Vogt
165316e38f serial: pl01x: expose skip_init platdata option in DT
To be able to represent the skip-init platdata element with OF_CONTROL,
it needs to be read from the device tree as well and put into the platform data.

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-28 20:09:47 -05:00
Fabian Vogt
9f755f5d09 serial: bcm283x_mu: add device tree support
This patch adds device tree support for the bcm283x mini-uart driver.

Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-28 20:09:46 -05:00
Fabian Vogt
4faf5f93c6 gpio: bcm2835: add device tree support
This patch adds device tree support for the bcm2835 GPIO driver.

Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-28 20:09:45 -05:00
Jagan Teki
6645fd2c18 sf: Rename sf_params.c to spi_flash_ids.c
Now the flash params table as renamed to spi_flash_ids structure,
so rename the sf_params.c to spi_flash_ids.c and remove the legacy.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2016-11-18 13:04:54 +05:30
Stephen Warren
afb970f78a dt: net: add DWC EQoS binding
The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which
supports multiple options for bus type, clocking and reset structure, and
feature list.

This patch imports the binding from the Linux kernel, including my V3
patch to extend the binding to cover the Tegra186, which is applied for
next-20160912. So far, my changes have been acked by Lars Persson, the
original author of the binding.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-07 11:28:15 -06:00
Stefan Agner
c571d6828d power: pmic: add Ricoh RN5T567 PMIC support
Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used
on Colibri iMX7.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-07 12:26:15 +02:00
Stefan Agner
a99546ab62 dm: imx: serial: support device tree
Support instatiation through device tree. Also parse the fsl,dte-mode
property to determine whether DTE mode shall be used.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-07 12:26:14 +02:00
John Keeping
7302fbb31d regulator: fixed: obey startup delay
When enabling a fixed regulator, it may take some time to rise to the
correct voltage.  If we do not delay here then subsequent operations
will fail.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-06 13:18:21 -04:00
Wenyou Yang
256a3f2466 atmel: Bring in at91 pio4 device tree file and bindings
Bring in required device tree file and bindings from Linux.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-15 22:58:04 +02:00
Songjun Wu
e3b7599be7 i2c: atmel: DT binding for i2c driver
DT binding documentation for atmel i2c driver.

Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2016-08-15 22:12:00 +02:00
Vignesh R
5746b0df9c gpio: Add driver for TI PCF8575 I2C GPIO expander
TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os should be high before being used as inputs.
Read the device documentation for more details[1].

This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.

[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-08-08 13:32:53 -04:00
Stephen Warren
6e7a11e64e dt-bindings: add Tegra186 BPMP I2C binding
In Tegra186, the BPMP (Boot and Power Management Processor) owns certain
HW devices, such as the I2C controller for the power management I2C bus.
Software running on other CPUs must perform IPC to the BPMP in order to
execute transactions on that I2C bus. This binding describes an I2C bus
that is accessed in such a fashion.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
390ae57c76 dt-bindings: allow child nodes inside the Tegra BPMP
The BPMP implements some services which must be represented by separate
nodes. For example, it can provide access to certain I2C controllers, and
the I2C bindings represent each I2C controller as a device tree node.
Update the binding to describe how the BPMP supports this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:59 -07:00
Stephen Warren
7b9cb49405 ARM: tegra: add BPMP DT bindings
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. These bindings dictate how to represent the BPMP in device tree.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:58 -07:00
Stephen Warren
729c2db7a9 ARM: tegra: adapt to latest HSP DT binding
The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:58 -07:00
Yoshinori Sato
747431b9d5 serial_sh: Add standrad SCI (w/o FIFO) support
Add support for standard type SCI (without FIFO) port.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2016-07-09 05:51:57 +09:00
Yoshinori Sato
359787cfe4 serial_sh: Device Tree support
Add Device Tree bindings.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2016-07-09 05:51:57 +09:00
Stephen Warren
89c1e2da78 Add a reset driver framework/uclass
A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.

This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.

The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-06-19 17:05:55 -06:00
Bin Meng
2600ba6de0 x86: Update x86-pinctrl driver device-tree-bindings doc
This updates the device-tree-bindings doc for x86-pinctrl driver:

 - clarify "gpio-offset" is required only when "mode-gpio" is set
 - correct property name "pull-strength"
 - use tab instead of space at several places

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
Stephen Warren
074a1fdd27 gpio: add Tegra186 GPIO driver
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.

The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org> # v1
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-31 09:54:24 -07:00
Stephen Warren
6238935d01 Add a mailbox driver framework/uclass
A mailbox is a hardware mechanism for transferring small message and/or
notifications between the CPU on which U-Boot runs and some other device
such as an auxilliary CPU running firmware or a hardware module.

This patch defines a standard API that connects mailbox clients to mailbox
providers (drivers). Initially, DT is the only supported method for
connecting the two.

The DT binding specification (mailbox.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-05-26 20:48:31 -06:00
Tom Rini
2ee490a024 Merge branch 'master' of git://git.denx.de/u-boot-net
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/zynq_gem.c
2016-05-24 11:59:02 -04:00
Dan Murphy
c7ba7bdc9d net: phy: dp83867: Add device tree bindings and documentation
Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.

The original document was from:
    [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Tom Rini
6d54868eeb Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-05-23 18:32:47 -04:00
Bin Meng
d4e61f505b x86: irq: Enable SCI on IRQ9
By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2016-05-23 15:18:00 +08:00
Wills Wang
b85dc46072 drivers: spi: add spi support for QCA/Atheros ath79 SOCs
This patch add a compatible spi driver for ath79 series SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:25:50 +02:00
Wills Wang
60b49761e9 drivers: serial: add serial driver for ar933x SOC
This patch add support for ar933x serial.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-21 01:25:50 +02:00
Moritz Fischer
17573c2791 i2c: Describe Cadence I2C devicetree bindings
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:07 +02:00
York Sun
3c1d218a1d armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-06 10:26:46 -07:00
Mateusz Kulikowski
120800df72 gpio: Add support for Qualcomm PM8916 gpios
This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:13 -04:00
Mateusz Kulikowski
c2f74c8f53 pmic: Add support for Qualcomm PM8916 PMIC
This PMIC is connected on SPMI bus so needs SPMI support enabled.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:13 -04:00
Mateusz Kulikowski
5b47271c18 drivers: spmi: Add support for Qualcomm SPMI bus driver
Support SPMI arbiter on Qualcomm Snapdragon devices.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:12 -04:00
Mateusz Kulikowski
d33776e43d spmi: Add sandbox test driver
This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:12 -04:00
Mateusz Kulikowski
5a8221181e ehci: Add support for Qualcomm EHCI
This driver is able to reconfigure OTG controller into HOST mode.
Board can add board-specific initialization as board_prepare_usb().
It requires USB_ULPI_VIEWPORT enabled in board configuration.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:11 -04:00
Mateusz Kulikowski
9d11d12a16 mmc: Add support for Qualcomm SDHCI controller
Add support for SD/eMMC controller present on some Qualcomm Snapdragon
devices. This controller implements SDHCI 2.0 interface but requires
vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:08 -04:00
Mateusz Kulikowski
81a87e1894 gpio: Add support for Qualcomm gpio controller
Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:07 -04:00
Mateusz Kulikowski
142a20c367 serial: Add support for Qualcomm serial port
This driver works in "new" Data Mover UART mode, so
will be compatible with modern Qualcomm chips only.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:07 -04:00
Vagrant Cascadian
a6f70a3d14 Fix spelling of "transferred".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:16 -04:00
Simon Glass
b24f5c4f27 x86: broadwell: Add a pinctrl driver
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
c13dcb3dc7 x86: dts: Update the pinctrl binding a little
Make a few minor updates to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
7ac99be6e2 x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Jacob Chen
c87c30e3ba doc: dt-bindings: Describe rockchip LVDS interface
I didn't have a common board to enable LVDS.
So add this dcocument to help others who want to enable LVDS in their board.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:24:44 +01:00
Paul Thacker
9e160ee823 drivers: serial: add driver for Microchip PIC32 UART controller.
This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:00 +01:00
Purna Chandra Mandal
a0e7908326 drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:00 +01:00
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Dinh Nguyen
c16e69f702 net: phy: micrel: add documentation for Micrel KSZ90x1 binding
Add the DTS documentation for the Micrel KSZ90x1 binding.

The original document was from:
[commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel]

This takes the original document and adds a clarification on how the skew
values are represented in the code.

References:

Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf

Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:29 -06:00
Bin Meng
a1c76c1508 net: tsec: Use priv->tbiaddr to initialize TBI PHY address
Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver,
it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we
can get this from device tree. Update the bindings doc as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:23:19 -06:00
Bin Meng
69a00875e3 doc: dt-bindings: Describe Freescale TSEC ethernet controller
Adapted from the same file name in the kernel device tree bindings
documentation, to use with U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:23:10 -06:00
Tom Rini
4b5a4a0535 Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-01-28 10:07:22 -05:00
Stefan Roese
9b5dbe1358 x86: baytrail: Add documentation for FSP memory-down values
This patch adds the documentation for the memory-down parameters
of the Intel FSP. To configure a board without SPD DDR DIMM but
with onboard DDR chips. The values are taken from the coreboot
header:

	src/soc/intel/fsp_baytrail/chip.h

(git ID da1a70ea from 2016-01-16 as reference).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Andrew Bradford <andrew.bradford@kodakalaris.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:29 +08:00
Michal Simek
93768393d7 serial: uartlite: Move driver to DM
Enable SPL DM too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
2016-01-27 15:55:49 +01:00
Thomas Chou
75219d57ef ns16550: replace with binding files from Linux kernel
Replace ns16550.txt with binding files from Linux kernel. As suggested
by Stephen Warren, we should keep the directory structure, filenames,
and file content identical to the bindings in the Linux kernel.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-25 10:40:03 -05:00