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ARM: tegra: adapt to latest HSP DT binding
The DT binding for the Tegra186 HSP module apparently wasn't quite final when I posted initial U-Boot support for it. Add the final DT binding doc and adapt all code and DT files to match it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren
Tom Warren
parent
e1efe43c71
commit
729c2db7a9
5 changed files with 113 additions and 29 deletions
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@ -1,7 +1,7 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra-hsp.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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/ {
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compatible = "nvidia,tegra186";
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@ -45,12 +45,8 @@
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,num-SM = <0x8>;
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nvidia,num-AS = <0x2>;
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nvidia,num-SS = <0x2>;
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nvidia,num-DB = <0x7>;
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nvidia,num-SI = <0x8>;
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#mbox-cells = <1>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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gpio@c2f0000 {
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52
doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt
Normal file
52
doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt
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@ -0,0 +1,52 @@
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NVIDIA Tegra Hardware Synchronization Primitives (HSP)
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The HSP modules are used for the processors to share resources and communicate
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together. It provides a set of hardware synchronization primitives for
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interprocessor communication. So the interprocessor communication (IPC)
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protocols can use hardware synchronization primitives, when operating between
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two processors not in an SMP relationship.
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The features that HSP supported are shared mailboxes, shared semaphores,
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arbitrated semaphores and doorbells.
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Required properties:
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- name : Should be hsp
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- compatible
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Array of strings.
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one of:
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- "nvidia,tegra186-hsp"
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- reg : Offset and length of the register set for the device.
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- interrupt-names
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Array of strings.
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Contains a list of names for the interrupts described by the interrupt
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property. May contain the following entries, in any order:
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- "doorbell"
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Users of this binding MUST look up entries in the interrupt property
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by name, using this interrupt-names property to do so.
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- interrupts
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Array of interrupt specifiers.
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Must contain one entry per entry in the interrupt-names property,
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in a matching order.
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- #mbox-cells : Should be 2.
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The mbox specifier of the "mboxes" property in the client node should
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contain two data. The first one should be the HSP type and the second
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one should be the ID that the client is going to use. Those information
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can be found in the following file.
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- <dt-bindings/mailbox/tegra186-hsp.h>.
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Example:
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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client {
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...
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mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_XXX>;
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};
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@ -8,7 +8,19 @@
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#include <asm/io.h>
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#include <dm.h>
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#include <mailbox-uclass.h>
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#include <dt-bindings/mailbox/tegra-hsp.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#define TEGRA_HSP_INT_DIMENSIONING 0x380
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#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16
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#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12
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#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8
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#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4
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#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0
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#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf
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#define TEGRA_HSP_DB_REG_TRIGGER 0x0
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#define TEGRA_HSP_DB_REG_ENABLE 0x4
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@ -51,7 +63,7 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
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static int tegra_hsp_db_id(ulong chan_id)
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{
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switch (chan_id) {
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case TEGRA_HSP_MASTER_BPMP:
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case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
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return TEGRA_HSP_DB_ID_BPMP;
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default:
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debug("Invalid channel ID\n");
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@ -59,6 +71,21 @@ static int tegra_hsp_db_id(ulong chan_id)
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}
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}
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static int tegra_hsp_of_xlate(struct mbox_chan *chan,
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struct fdtdec_phandle_args *args)
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{
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debug("%s(chan=%p)\n", __func__, chan);
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if (args->args_count != 2) {
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debug("Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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chan->id = (args->args[0] << 16) | args->args[1];
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return 0;
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}
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static int tegra_hsp_request(struct mbox_chan *chan)
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{
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int db_id;
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@ -121,6 +148,7 @@ static int tegra_hsp_bind(struct udevice *dev)
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static int tegra_hsp_probe(struct udevice *dev)
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{
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struct tegra_hsp *thsp = dev_get_priv(dev);
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u32 val;
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int nr_sm, nr_ss, nr_as;
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debug("%s(dev=%p)\n", __func__, dev);
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@ -129,12 +157,14 @@ static int tegra_hsp_probe(struct udevice *dev)
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if (thsp->regs == FDT_ADDR_T_NONE)
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return -ENODEV;
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nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM",
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0);
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nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS",
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0);
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nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS",
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0);
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val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING);
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nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) &
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TEGRA_HSP_INT_DIMENSIONING_NSM_MASK;
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nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) &
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TEGRA_HSP_INT_DIMENSIONING_NSS_MASK;
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nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) &
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TEGRA_HSP_INT_DIMENSIONING_NAS_MASK;
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thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
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return 0;
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@ -146,6 +176,7 @@ static const struct udevice_id tegra_hsp_ids[] = {
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};
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struct mbox_ops tegra_hsp_mbox_ops = {
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.of_xlate = tegra_hsp_of_xlate,
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.request = tegra_hsp_request,
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.free = tegra_hsp_free,
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.send = tegra_hsp_send,
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@ -1,14 +0,0 @@
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/*
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* This header provides constants for binding nvidia,tegra186-hsp.
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*
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* The number with TEGRA_HSP_MASTER prefix indicates the bit that is
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* associated with a master ID in the doorbell registers.
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*/
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#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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#define TEGRA_HSP_MASTER_CCPLEX 17
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#define TEGRA_HSP_MASTER_BPMP 19
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#endif
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19
include/dt-bindings/mailbox/tegra186-hsp.h
Normal file
19
include/dt-bindings/mailbox/tegra186-hsp.h
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@ -0,0 +1,19 @@
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/*
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* This header provides constants for binding nvidia,tegra186-hsp.
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*
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* The number with HSP_DB_MASTER prefix indicates the bit that is
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* associated with a master ID in the doorbell registers.
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*/
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#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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#define HSP_MBOX_TYPE_DB 0x0
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#define HSP_MBOX_TYPE_SM 0x1
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#define HSP_MBOX_TYPE_SS 0x2
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#define HSP_MBOX_TYPE_AS 0x3
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#define HSP_DB_MASTER_CCPLEX 17
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#define HSP_DB_MASTER_BPMP 19
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#endif
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