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doc: a37xx: Introduce pinctrl device tree binding
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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Ken Ma
Stefan Roese
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doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
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doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
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* Marvell Armada 37xx SoC pin and GPIO controller
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Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
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South Bridge and the other for the North Bridge.
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GPIO and pin controller:
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------------------------
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Main node:
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Refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning
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of the phrase "pin configuration node".
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Required properties for pinctrl driver:
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- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
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for the South Bridge
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"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
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for the North Bridge
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- reg: The first set of registers is for pinctrl/GPIO and the second
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set is for the interrupt controller
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- interrupts: list of interrupts used by the GPIO
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Available groups and functions for the North Bridge:
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group: jtag
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- pins 20-24
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- functions jtag, gpio
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group sdio0
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- pins 8-10
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- functions sdio, gpio
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group emmc_nb
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- pins 27-35
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- functions emmc, gpio
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group pwm0
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- pin 11 (GPIO1-11)
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- functions pwm, gpio
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group pwm1
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- pin 12
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- functions pwm, gpio
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group pwm2
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- pin 13
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- functions pwm, gpio
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group pwm3
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- pin 14
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- functions pwm, gpio
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group pmic1
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- pin 7
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- functions pmic, gpio
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group pmic0
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- pin 6
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- functions pmic, gpio
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group i2c2
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- pins 2-3
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- functions i2c, gpio
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group i2c1
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- pins 0-1
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- functions i2c, gpio
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group spi_cs1
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- pin 17
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- functions spi, gpio
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group spi_cs2
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- pin 18
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- functions spi, gpio
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group spi_cs3
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- pin 19
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- functions spi, gpio
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group onewire
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- pin 4
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- functions onewire, gpio
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group uart1
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- pins 25-26
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- functions uart, gpio
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group spi_quad
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- pins 15-16
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- functions spi, gpio
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group uart_2
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- pins 9-10
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- functions uart, gpio
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Available groups and functions for the South Bridge:
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group usb32_drvvbus0
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- pin 36
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- functions drvbus, gpio
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group usb2_drvvbus1
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- pin 37
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- functions drvbus, gpio
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group sdio_sb
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- pins 60-65
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- functions sdio, gpio
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group rgmii
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- pins 42-53
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- functions mii, gpio
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group pcie1
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- pins 39-41
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- functions pcie, gpio
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group smi
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- pins 54-55
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- functions smi, gpio
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group ptp
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- pins 56-58
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- functions ptp, gpio
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group ptp_clk
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- pin 57
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- functions ptp, mii
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group ptp_trig
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- pin 58
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- functions ptp, mii
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group mii_col
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- pin 59
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- functions mii, mii_err
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GPIO subnode:
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Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property
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and the common GPIO bindings used by client devices.
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Required properties for the GPIO driver under the gpio subnode:
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- interrupts: List of interrupt specifiers for the controllers interrupt.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Should be 2. The first cell is the GPIO number and the
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second cell specifies GPIO flags, as defined in
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<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
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GPIO_ACTIVE_LOW flags are supported.
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- gpio-ranges: Range of pins managed by the GPIO controller.
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Example:
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pinctrl_sb: pinctrl-sb@18800 {
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compatible = "marvell,armada3710-sb-pinctrl",
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"syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpiosb: gpiosb {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 30>;
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gpio-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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rgmii_pins: mii-pins {
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groups = "rgmii";
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function = "mii";
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};
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sdio_pins: sdio-pins {
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groups = "sdio_sb";
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function = "sdio";
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};
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pcie_pins: pcie-pins {
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groups = "pcie1";
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function = "pcie";
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};
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};
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