Commit graph

73330 commits

Author SHA1 Message Date
Joseph Chen
2d46775287 rockchip: rk3568: Add sdram driver
Add the driver for rk3568 u-boot to get sdram capacity.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Joseph Chen
636ffbd25c arm: dts: rockchip: Add dts for rk3568 evb
Add dts for rk3568 evb, sync from the linux kernel
upstream list [0].

[0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Joseph Chen
a4a9ce1660 arm: dts: Sync rockchip-pinconf.dtsi from kernel
Sync from linux kernel:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Artem Lapkin
c52c362e64 rk3399_common: setup fdtoverlay_addr_r value
fdtoverlay (pxe_utils) require define fdtoverlay_addr_r env variable
for example sunxi-common.h meson64.h already have it.

Signed-off-by: Artem Lapkin <art@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:07 +08:00
Elaine Zhang
4a262feba3 rockchip: rk3568: add clock driver
Add rk3568 clock driver and cru structure definition.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:06 +08:00
Elaine Zhang
19ec205de0 rockchip: rk3568: add device tree file
Add dts binding header for rk3568, files origin from kernel.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:34:48 +08:00
Tom Rini
a94b2aad05 First set of u-boot-atmel features for the 2021.10 cycle
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Merge tag 'u-boot-atmel-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for the 2021.10 cycle:

This feature set converts the boards pm9261 and pm9263 Ethernet support
to DM; enables hash command for all SAM boards; fixes the NAND pmecc
bit-flips correction; adds Falcon boot for sama5d3_xplained board; and
other minor adjustments.
2021-06-17 11:46:44 -04:00
Tom Rini
e87a933406 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
- K210 updates
2021-06-17 11:46:23 -04:00
Sean Anderson
446b4f346e test: Add K210 PLL tests to sandbox defconfigs
This adds the unit test for the K210 PLL to the sandbox defconfigs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-17 09:40:58 +08:00
Sean Anderson
55dac94ab8 k210: Don't imply CCF
Now that the k210 clock driver does not depend on CCF, we should no longer
imply it (and probably should not have in the first place). We can also
reduce the pre-relocation malloc arena back to something sensible.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:58 +08:00
Sean Anderson
9cd637f84b k210: dts: Set PLL1 to the same rate as PLL0
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:58 +08:00
Sean Anderson
493110cc49 clk: k210: Move k210 clock out of its own subdirectory
Now that we have only one clock driver, we don't need to have our own
subdirectory. Move the driver back with the rest of the clock drivers.

The MAINTAINERS for kendryte pinctrl is also fixed since it has always been
wrong.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:58 +08:00
Sean Anderson
c29efc157d clk: k210: Remove bypass driver
This driver no longer serves a purpose now that we have moved away from
CCF. Drop it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:57 +08:00
Sean Anderson
df79e2b48b clk: k210: Don't set PLL rates if we are already at the correct rate
This speeds up boot by preventing multiple reconfigurations of the PLLs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:57 +08:00
Sean Anderson
29e3067d91 clk: k210: Re-add support for setting rate
This adds support for setting clock rates, which was left out of the
initial CCF expunging. There are several tricky bits here, mostly related
to the PLLS:

* The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
  will be stopped.
* PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
  stopping the CPU while we configure PLL0's rate, ACLK is reparented
  to IN0 while PLL0 is disabled.
* PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
  so we instead just disallow changing PLL1's rate after relocation (when
  we are using the AISRAM).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:57 +08:00
Sean Anderson
612a8334cd clk: k210: Implement soc_clk_dump
Since we are no longer using CCF we cannot use the default soc_clk_dump.
Instead, implement our own.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:57 +08:00
Sean Anderson
af9f997436 clk: k210: Move pll into the rest of the driver
Now that there no separate PLL driver, we can no longer make the PLL
functions static. By moving the PLL driver in with the rest of the clock
code, we can make these functions static again. We still keep the pll
header for unit testing, but it is pretty reduced.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:57 +08:00
Sean Anderson
609bd60b94 clk: k210: Rewrite to remove CCF
This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary. It also takes up less memory
at runtime (since we don't have to create 40 udevices). In general, I am
much happier with this driver as much of the complexity and late binding
has been removed.

The k210_*_params structs which were previously used to initialize CCF
clocks are now used as the complete configuration. Since we can write our
own division logic, we can now do away with several "half" clocks which
only existed to provide constant factors of two.

The clock IDs have been renumbered to remove unused clocks. This may not be
the last time they are renumbered, since we have diverged with Linux. There
are also still a few clocks left out which may need to be added back in.

In general, I have tried to leave out behavioral changes. However, there is
a small bugfix regarding ACLK. According to the technical reference manual,
its mux comes *after* its divider (which is present only for PLL0). This
would have required yet another intermediate clock to fix with CCF, but
with the new driver it is just 2 lines of code :)

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:57 +08:00
Sean Anderson
6e33eba59f clk: Allow force setting clock defaults before relocation
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
state for SPL only") it has been impossible to set clock defaults before
relocation. This is annoying on boards without SPL, since there is no way
to set clock defaults before U-Boot proper. In particular, the aisram rate
must be changed before relocation on the K210, since U-Boot will hang if we
try and change the rate while we are using aisram.

To get around this, extend the stage parameter to allow force setting
defaults, even if they would be otherwise postponed for later. A device
tree property was decided against because of the concerns in the original
commit thread about the overhead of repeatedly parsing the device tree.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-17 09:40:57 +08:00
Michael Opdenacker
ea83ea5afd board: sama5d3_xplained: add Falcon boot support
This supports Falcon boot support for Microchip SAMA5D3 Xplained,
tested on raw MMC, and on raw NAND.

spl_start_uboot() is has the simplest possible implementation.
It doesn't test the environment because enabling environment support
currently causes the SPL to exceed its maximum size (64 KiB).
It doesn't check the serial for incoming characters either because
this functionality currently doesn't seem to work from the SPL
on this board.

Settings for Falcon boot from at FAT partition are also added to
avoid compile failures when CONFIG_SPL_OS_BOOT is enabled, but this
particular case is currently not functional as adding FAT and
partition support cause the SPL to be too big again.

Signed-off-by: Michael Opdenacker <michael.opdenacker@bootlin.com>
2021-06-14 12:28:03 +03:00
Eugen Hristev
86ce3737ed configs: sam boards: add hash command
Add hash and hash verify commands. These would be useful for
verifying copied data.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-06-14 11:57:09 +03:00
Tom Rini
173c3bcd7d Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next
- HSM re-architecture support for all K3 platforms
- AM64 USB support
- Driver model support for Davinci RTC
2021-06-13 07:48:22 -04:00
Vignesh Raghavendra
5abb694d60 dma: ti: k3-udma: Add support for native configuration of chan/flow
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers.
Add support for the same.

Note that we still need to send chan/flow cfg message to TIFS via TISCI
client driver in order to open up firewalls around chan/flow but setting
up of cfg registers is handled locally.

U-Boot specific code is in a separate file included in main driver so
as to maintain similarity with kernel driver in order to ease porting of
code in future.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-8-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
86e58800fd soc: ti: k3-navss-ringacc: Add support for native configuration of rings
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup Ring Cfg registers. Add support for
the same.

Note that we still need to send RING_CFG message to TIFS via TISCI
client driver in order to open up firewalls around Rings.

U-Boot specific code is in a separate file included in main driver so
as to maintain similarity with kernel driver in order to ease porting of
code in future.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-7-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
2af181b53e ARM: dts: k3: Add cfg register space for ringacc and udmap
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Note that these registers are present within respective IPs but are
not populated in Linux DT nodes (as they are configured via TISCI APIs)
and hence are added to -u-boot.dtsi for now.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
00d6fc9c71 ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node
Add DM firmware node which will provide DM services during R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
5d5a699855 firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.
On J721e and J7200, MCU R5 core (boot master) itself would run Device
Manager (DM) Firmware and interact with TI Foundational Security (TIFS)
firmware to enable DMA and such other Resource Management (RM) services.
So, during R5 SPL stage there is no such RM service available and ti_sci
driver will have to directly interact with TIFS using DM to DMSC
channels to request RM resources.

Therefore add DT binding and driver for the same. This driver will
handle Resource Management services at R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
0e81158b76 firmware: ti_sci: Implement GET_RANGE with static data
In case of R5 SPL, GET_RANGE API service is not available (as DM
services are not yet up), therefore service such calls locally using
per SoC static data.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-3-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
5d80f1becf mailbox: k3-sec-proxy: Add DM to DMSC communication thread
R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads.
Mark these as valid threads in the driver.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-2-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Tero Kristo
bb318d8dc8 arm: dts: k3-j72xx: correct MCU timer1 frequency
MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
c3ebc56e2d board: ti: j72xx: README: update build instructions and image formats
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
6cfb6ff337 configs: j7200_evm_r5: Enable raw access power management features
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
a95f8c0781 configs: j721e_evm_r5: Enable raw access power management features
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
61305e00c7 arm: mach-k3: j721e_init: Force early probe of clk-k3 driver
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reported-by: Keerthy <j-keerthy@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
925698daac arm: mach-k3: sysfw-loader: pass boardcfg to sciserver
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
7acd4d7142 arm: mach-k3: common: Drop main r5 start
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
0714580346 arm: mach-k3: do board config for PM only if supported
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
547b277cd9 arm: mach-k3: add support for detecting firmware images from FIT
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
277729eaf3 arm: mach-k3: Add platform data for j721e and j7200
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
df5363a67f tools: k3_fit_atf: add DM binary to the FIT image
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
f79753c3de cmd: ti: pd: Add debug command for K3 power domains
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-11 16:34:52 +05:30
Tero Kristo
144464bd2c power: domain: Introduce driver for raw TI K3 PDs
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-11 16:34:52 +05:30
Tero Kristo
b4a72a9f5b clk: add support for TI K3 SoC clocks
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
0aa2930ca1 clk: add support for TI K3 SoC PLL
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
6b7fd3128f clk: fix set_rate to clean up cached rates for the hierarchy
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
1e1fab0be5 clk: fix assigned-clocks to pass with deferring provider
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
c319572abd clk: sci-clk: fix return value of set_rate
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
7ab418fbe6 clk: add support for setting clk rate from cmdline
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.

Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
920ea5a7f8 clk: do not attempt to fetch clock pointer with null device
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:

  dev_get_uclass_priv: null device

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
1a725e2290 clk: fix clock tree dump to properly dump out every registered clock
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30