Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next

- HSM re-architecture support for all K3 platforms - AM64 USB support - Driver model support for Davinci RTC
2024-11-10 15:14:43 +00:00 · 2021-06-13 07:48:22 -04:00 · 2021-06-13 07:48:22 -04:00 · 173c3bcd7d
commit 173c3bcd7d
parent e8f720ee17 5abb694d60
83 changed files with 5164 additions and 355 deletions
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@ -398,3 +398,8 @@
 &sham {
 	status = "okay";
 };
+
+&rtc {
+	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+	clock-names = "ext-clk", "int-clk";
+};
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@ -762,3 +762,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dcan1_pins_default>;
 };
+
+&rtc {
+	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+	clock-names = "ext-clk", "int-clk";
+};
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@ -724,3 +724,8 @@
 &lcdc {
      status = "okay";
 };
+
+&rtc {
+	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+	clock-names = "ext-clk", "int-clk";
+};
--- a/arch/arm/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/dts/am335x-osd335x-common.dtsi
@ -122,3 +122,9 @@
 &sham {
 	status = "okay";
 };
+
+&rtc {
+	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+	clock-names = "ext-clk", "int-clk";
+	system-power-controller;
+};
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@ -14,7 +14,7 @@
 		ranges = <0x0 0x00 0x70000000 0x200000>;

 		atf-sram@0 {
-			reg = <0x0 0x1a000>;
+			reg = <0x1a0000 0x1c000>;
 		};
 	};

@ -499,6 +499,36 @@
 		clock-names = "gpio";
 	};

+	usbss0: cdns-usb@f900000{
+		compatible = "ti,am64-usb", "ti,j721e-usb";
+		reg = <0x00 0xf900000 0x00 0x100>;
+		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
+		clock-names = "ref", "lpm";
+		assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
+		assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		usb0: usb@f400000{
+			compatible = "cdns,usb3";
+			reg = <0x00 0xf400000 0x00 0x10000>,
+			      <0x00 0xf410000 0x00 0x10000>,
+			      <0x00 0xf420000 0x00 0x10000>;
+			reg-names = "otg",
+				    "xhci",
+				    "dev";
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+			interrupt-names = "host",
+					  "peripheral",
+					  "otg";
+			maximum-speed = "super-speed";
+			dr_mode = "otg";
+		};
+	};
+
 	main_gpio1: gpio@601000 {
 		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 		reg = <0x00 0x00601000 0x00 0x100>;
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@ -50,6 +50,19 @@
 	u-boot,dm-spl;
 };

+&usb0 {
+	dr_mode="peripheral";
+	u-boot,dm-spl;
+};
+
+&usbss0 {
+	u-boot,dm-spl;
+};
+
+&main_usb0_pins_default {
+	u-boot,dm-spl;
+};
+
 &dmss {
 	u-boot,dm-spl;
 };
--- a/arch/arm/dts/k3-am642-evm.dts
+++ b/arch/arm/dts/k3-am642-evm.dts
@ -201,6 +201,12 @@
 			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
 		>;
 	};
+
+	main_usb0_pins_default: main-usb0-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+		>;
+	};
 };

 &main_uart0 {
@ -337,3 +343,15 @@
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
 };
+
+&usbss0 {
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usb0_pins_default>;
+};
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@ -141,6 +141,12 @@
 			AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7)	/* (L18) OSPI0_CSN1.GPIO0_12 */
 		>;
 	};
+
+	main_usb0_pins_default: main-usb0-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+		>;
+	};
 };

 &dmsc {
@ -201,4 +207,16 @@
 	/delete-property/ power-domains;
 };

+&usbss0 {
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usb0_pins_default>;
+};
+
 #include "k3-am642-evm-u-boot.dtsi"
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@ -35,11 +35,25 @@
 		u-boot,dm-spl;

 		ringacc@2b800000 {
+			reg =	<0x0 0x2b800000 0x0 0x400000>,
+				<0x0 0x2b000000 0x0 0x400000>,
+				<0x0 0x28590000 0x0 0x100>,
+				<0x0 0x2a500000 0x0 0x40000>,
+				<0x0 0x28440000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 			u-boot,dm-spl;
 			ti,dma-ring-reset-quirk;
 		};

 		dma-controller@285c0000 {
+			reg =	<0x0 0x285c0000 0x0 0x100>,
+				<0x0 0x284c0000 0x0 0x4000>,
+				<0x0 0x2a800000 0x0 0x40000>,
+				<0x0 0x284a0000 0x0 0x4000>,
+				<0x0 0x2aa00000 0x0 0x40000>,
+				<0x0 0x28400000 0x0 0x2000>;
+			reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+					    "tchanrt", "rflow";
 			u-boot,dm-spl;
 		};
 	};
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@ -33,13 +33,39 @@
 		compatible = "ti,omap5430-timer";
 		reg = <0x0 0x40400000 0x0 0x80>;
 		ti,timer-alwon;
-		clock-frequency = <25000000>;
+		clock-frequency = <250000000>;
 		u-boot,dm-spl;
 	};

 	chipid@43000014 {
 		u-boot,dm-spl;
 	};
+
+	mcu-navss{
+		u-boot,dm-spl;
+
+		ringacc@2b800000 {
+			reg =	<0x0 0x2b800000 0x0 0x400000>,
+				<0x0 0x2b000000 0x0 0x400000>,
+				<0x0 0x28590000 0x0 0x100>,
+				<0x0 0x2a500000 0x0 0x40000>,
+				<0x0 0x28440000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+			u-boot,dm-spl;
+		};
+
+		dma-controller@285c0000 {
+			reg =	<0x0 0x285c0000 0x0 0x100>,
+				<0x0 0x284c0000 0x0 0x4000>,
+				<0x0 0x2a800000 0x0 0x40000>,
+				<0x0 0x284a0000 0x0 0x4000>,
+				<0x0 0x2aa00000 0x0 0x40000>,
+				<0x0 0x28400000 0x0 0x2000>;
+			reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+					    "tchanrt", "rflow";
+			u-boot,dm-spl;
+		};
+	};
 };

 &secure_proxy_main {
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@ -1,13 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.3.0
- * This file was generated on 06/08/2020
- * Includes hand edits
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
+ * This file was generated on 08/07/2020
+ * Includes hand-edits
 */

 #define DDRSS_PLL_FHS_CNT 10
-#define DDRSS_PLL_FREQUENCY_1 400000000
-#define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_PLL_FREQUENCY_1 666500000
+#define DDRSS_PLL_FREQUENCY_2 666500000

 #define DDRSS_CTL_00_DATA 0x00000B00
 #define DDRSS_CTL_01_DATA 0x00000000
@ -20,14 +21,14 @@
 #define DDRSS_CTL_08_DATA 0x000186A0
 #define DDRSS_CTL_09_DATA 0x00000005
 #define DDRSS_CTL_10_DATA 0x00000064
-#define DDRSS_CTL_11_DATA 0x00027100
-#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_11_DATA 0x000411AB
+#define DDRSS_CTL_12_DATA 0x0028B0AB
 #define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000640
-#define DDRSS_CTL_15_DATA 0x00027100
-#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_14_DATA 0x00000A6B
+#define DDRSS_CTL_15_DATA 0x000411AB
+#define DDRSS_CTL_16_DATA 0x0028B0AB
 #define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_18_DATA 0x00000A6B
 #define DDRSS_CTL_19_DATA 0x01010000
 #define DDRSS_CTL_20_DATA 0x02011001
 #define DDRSS_CTL_21_DATA 0x02010000
@ -37,66 +38,66 @@
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
 #define DDRSS_CTL_27_DATA 0x02020200
-#define DDRSS_CTL_28_DATA 0x00002020
+#define DDRSS_CTL_28_DATA 0x00003636
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
 #define DDRSS_CTL_31_DATA 0x00000000
 #define DDRSS_CTL_32_DATA 0x00000000
 #define DDRSS_CTL_33_DATA 0x00000000
 #define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x081C081C
+#define DDRSS_CTL_35_DATA 0x0C300C30
 #define DDRSS_CTL_36_DATA 0x00050804
 #define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x08000204
-#define DDRSS_CTL_39_DATA 0x0B240034
-#define DDRSS_CTL_40_DATA 0x08001910
-#define DDRSS_CTL_41_DATA 0x0B240034
-#define DDRSS_CTL_42_DATA 0x20001910
+#define DDRSS_CTL_38_DATA 0x0D000204
+#define DDRSS_CTL_39_DATA 0x113C0057
+#define DDRSS_CTL_40_DATA 0x0D00291B
+#define DDRSS_CTL_41_DATA 0x113C0057
+#define DDRSS_CTL_42_DATA 0x2000291B
 #define DDRSS_CTL_43_DATA 0x000A0A09
 #define DDRSS_CTL_44_DATA 0x040006DB
-#define DDRSS_CTL_45_DATA 0x0C0A0904
-#define DDRSS_CTL_46_DATA 0x06006DB0
-#define DDRSS_CTL_47_DATA 0x0C0A0906
-#define DDRSS_CTL_48_DATA 0x06006DB0
-#define DDRSS_CTL_49_DATA 0x02030406
-#define DDRSS_CTL_50_DATA 0x11040500
-#define DDRSS_CTL_51_DATA 0x08121112
+#define DDRSS_CTL_45_DATA 0x130E0B04
+#define DDRSS_CTL_46_DATA 0x0A00B6D0
+#define DDRSS_CTL_47_DATA 0x130E0B0A
+#define DDRSS_CTL_48_DATA 0x0A00B6D0
+#define DDRSS_CTL_49_DATA 0x0203040A
+#define DDRSS_CTL_50_DATA 0x1C040500
+#define DDRSS_CTL_51_DATA 0x081D1C1D
 #define DDRSS_CTL_52_DATA 0x14000D0A
 #define DDRSS_CTL_53_DATA 0x02010A0A
 #define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x04222208
-#define DDRSS_CTL_56_DATA 0x04131304
-#define DDRSS_CTL_57_DATA 0x00001313
+#define DDRSS_CTL_55_DATA 0x04383808
+#define DDRSS_CTL_56_DATA 0x041F1F04
+#define DDRSS_CTL_57_DATA 0x00001F1F
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
 #define DDRSS_CTL_60_DATA 0x00000E08
 #define DDRSS_CTL_61_DATA 0x000000BB
-#define DDRSS_CTL_62_DATA 0x000000E0
-#define DDRSS_CTL_63_DATA 0x00000C28
-#define DDRSS_CTL_64_DATA 0x000000E0
-#define DDRSS_CTL_65_DATA 0x00000C28
+#define DDRSS_CTL_62_DATA 0x00000176
+#define DDRSS_CTL_63_DATA 0x00001448
+#define DDRSS_CTL_64_DATA 0x00000176
+#define DDRSS_CTL_65_DATA 0x00001448
 #define DDRSS_CTL_66_DATA 0x00000005
 #define DDRSS_CTL_67_DATA 0x00030000
-#define DDRSS_CTL_68_DATA 0x00380010
-#define DDRSS_CTL_69_DATA 0x0038017E
-#define DDRSS_CTL_70_DATA 0x0040017E
+#define DDRSS_CTL_68_DATA 0x005D0010
+#define DDRSS_CTL_69_DATA 0x005D0282
+#define DDRSS_CTL_70_DATA 0x00400282
 #define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x00060005
-#define DDRSS_CTL_73_DATA 0x14080006
-#define DDRSS_CTL_74_DATA 0x05050114
-#define DDRSS_CTL_75_DATA 0x0201030A
-#define DDRSS_CTL_76_DATA 0x030C0605
-#define DDRSS_CTL_77_DATA 0x06050201
-#define DDRSS_CTL_78_DATA 0x0001030C
+#define DDRSS_CTL_72_DATA 0x000A0005
+#define DDRSS_CTL_73_DATA 0x1F08000A
+#define DDRSS_CTL_74_DATA 0x0505011F
+#define DDRSS_CTL_75_DATA 0x0301030A
+#define DDRSS_CTL_76_DATA 0x03130A07
+#define DDRSS_CTL_77_DATA 0x0A070301
+#define DDRSS_CTL_78_DATA 0x00010313
 #define DDRSS_CTL_79_DATA 0x000F000F
-#define DDRSS_CTL_80_DATA 0x00E600E6
-#define DDRSS_CTL_81_DATA 0x00E600E6
+#define DDRSS_CTL_80_DATA 0x01800180
+#define DDRSS_CTL_81_DATA 0x01800180
 #define DDRSS_CTL_82_DATA 0x03050505
 #define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x0C050605
-#define DDRSS_CTL_85_DATA 0x03020603
-#define DDRSS_CTL_86_DATA 0x0C050605
-#define DDRSS_CTL_87_DATA 0x03020603
+#define DDRSS_CTL_84_DATA 0x14070A07
+#define DDRSS_CTL_85_DATA 0x03030A03
+#define DDRSS_CTL_86_DATA 0x14070A07
+#define DDRSS_CTL_87_DATA 0x03030A03
 #define DDRSS_CTL_88_DATA 0x03010000
 #define DDRSS_CTL_89_DATA 0x00010000
 #define DDRSS_CTL_90_DATA 0x00000000
@ -118,20 +119,20 @@
 #define DDRSS_CTL_106_DATA 0x00002EC0
 #define DDRSS_CTL_107_DATA 0x00000000
 #define DDRSS_CTL_108_DATA 0x0000051D
-#define DDRSS_CTL_109_DATA 0x00030A00
-#define DDRSS_CTL_110_DATA 0x00030A00
-#define DDRSS_CTL_111_DATA 0x00030A00
-#define DDRSS_CTL_112_DATA 0x00030A00
-#define DDRSS_CTL_113_DATA 0x00030A00
+#define DDRSS_CTL_109_DATA 0x00051200
+#define DDRSS_CTL_110_DATA 0x00051200
+#define DDRSS_CTL_111_DATA 0x00051200
+#define DDRSS_CTL_112_DATA 0x00051200
+#define DDRSS_CTL_113_DATA 0x00051200
 #define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00005518
-#define DDRSS_CTL_116_DATA 0x00030A00
-#define DDRSS_CTL_117_DATA 0x00030A00
-#define DDRSS_CTL_118_DATA 0x00030A00
-#define DDRSS_CTL_119_DATA 0x00030A00
-#define DDRSS_CTL_120_DATA 0x00030A00
+#define DDRSS_CTL_115_DATA 0x00008DF8
+#define DDRSS_CTL_116_DATA 0x00051200
+#define DDRSS_CTL_117_DATA 0x00051200
+#define DDRSS_CTL_118_DATA 0x00051200
+#define DDRSS_CTL_119_DATA 0x00051200
+#define DDRSS_CTL_120_DATA 0x00051200
 #define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00005518
+#define DDRSS_CTL_122_DATA 0x00008DF8
 #define DDRSS_CTL_123_DATA 0x00000000
 #define DDRSS_CTL_124_DATA 0x00000000
 #define DDRSS_CTL_125_DATA 0x00000000
@ -140,8 +141,8 @@
 #define DDRSS_CTL_128_DATA 0x00000000
 #define DDRSS_CTL_129_DATA 0x00000000
 #define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x05030500
-#define DDRSS_CTL_132_DATA 0x00030503
+#define DDRSS_CTL_131_DATA 0x07030500
+#define DDRSS_CTL_132_DATA 0x00030703
 #define DDRSS_CTL_133_DATA 0x0A090000
 #define DDRSS_CTL_134_DATA 0x0A090701
 #define DDRSS_CTL_135_DATA 0x0900000E
@ -176,23 +177,23 @@
 #define DDRSS_CTL_164_DATA 0x000A0000
 #define DDRSS_CTL_165_DATA 0x000D0005
 #define DDRSS_CTL_166_DATA 0x000D0404
-#define DDRSS_CTL_167_DATA 0x005000A0
-#define DDRSS_CTL_168_DATA 0x060600C8
-#define DDRSS_CTL_169_DATA 0x00A000C8
-#define DDRSS_CTL_170_DATA 0x00C80050
-#define DDRSS_CTL_171_DATA 0x00C80606
+#define DDRSS_CTL_167_DATA 0x0086010B
+#define DDRSS_CTL_168_DATA 0x0A0A014E
+#define DDRSS_CTL_169_DATA 0x010B014E
+#define DDRSS_CTL_170_DATA 0x014E0086
+#define DDRSS_CTL_171_DATA 0x014E0A0A
 #define DDRSS_CTL_172_DATA 0x00000000
 #define DDRSS_CTL_173_DATA 0x00000000
 #define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x12A40084
-#define DDRSS_CTL_176_DATA 0x2B0012A4
+#define DDRSS_CTL_175_DATA 0x24C40084
+#define DDRSS_CTL_176_DATA 0x2B0024C4
 #define DDRSS_CTL_177_DATA 0x00002B2B
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
 #define DDRSS_CTL_181_DATA 0x00000000
 #define DDRSS_CTL_182_DATA 0x00841515
-#define DDRSS_CTL_183_DATA 0x12A412A4
+#define DDRSS_CTL_183_DATA 0x24C424C4
 #define DDRSS_CTL_184_DATA 0x2B2B2B00
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00363600
@ -270,12 +271,12 @@
 #define DDRSS_CTL_258_DATA 0x00320040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00180320
+#define DDRSS_CTL_261_DATA 0x00280536
 #define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x03200040
-#define DDRSS_CTL_264_DATA 0x00000018
-#define DDRSS_CTL_265_DATA 0x00280003
-#define DDRSS_CTL_266_DATA 0x01000028
+#define DDRSS_CTL_263_DATA 0x05360040
+#define DDRSS_CTL_264_DATA 0x00000028
+#define DDRSS_CTL_265_DATA 0x00430003
+#define DDRSS_CTL_266_DATA 0x01000043
 #define DDRSS_CTL_267_DATA 0x00000000
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
@ -327,14 +328,14 @@
 #define DDRSS_CTL_315_DATA 0x01000101
 #define DDRSS_CTL_316_DATA 0x01010001
 #define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05050503
-#define DDRSS_CTL_319_DATA 0x08080C0C
-#define DDRSS_CTL_320_DATA 0x00090308
-#define DDRSS_CTL_321_DATA 0x000C030F
-#define DDRSS_CTL_322_DATA 0x000C0311
-#define DDRSS_CTL_323_DATA 0x0C090011
+#define DDRSS_CTL_318_DATA 0x05070703
+#define DDRSS_CTL_319_DATA 0x0A081414
+#define DDRSS_CTL_320_DATA 0x0009030A
+#define DDRSS_CTL_321_DATA 0x080C030F
+#define DDRSS_CTL_322_DATA 0x080C0306
+#define DDRSS_CTL_323_DATA 0x0C090006
 #define DDRSS_CTL_324_DATA 0x0100000C
-#define DDRSS_CTL_325_DATA 0x03020301
+#define DDRSS_CTL_325_DATA 0x05020501
 #define DDRSS_CTL_326_DATA 0x00000002
 #define DDRSS_CTL_327_DATA 0x00000000
 #define DDRSS_CTL_328_DATA 0x00010000
@ -396,7 +397,7 @@
 #define DDRSS_CTL_384_DATA 0x00000000
 #define DDRSS_CTL_385_DATA 0x00000000
 #define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x26261B00
+#define DDRSS_CTL_387_DATA 0x2E2E1B00
 #define DDRSS_CTL_388_DATA 0x000A0000
 #define DDRSS_CTL_389_DATA 0x00000176
 #define DDRSS_CTL_390_DATA 0x00000200
@ -406,22 +407,22 @@
 #define DDRSS_CTL_394_DATA 0x00000462
 #define DDRSS_CTL_395_DATA 0x00000E9C
 #define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00001850
+#define DDRSS_CTL_397_DATA 0x00002890
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x00000200
 #define DDRSS_CTL_400_DATA 0x00000200
 #define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000048F0
-#define DDRSS_CTL_403_DATA 0x0000F320
-#define DDRSS_CTL_404_DATA 0x00000408
-#define DDRSS_CTL_405_DATA 0x00001850
+#define DDRSS_CTL_402_DATA 0x000079B0
+#define DDRSS_CTL_403_DATA 0x000195A0
+#define DDRSS_CTL_404_DATA 0x0000080E
+#define DDRSS_CTL_405_DATA 0x00002890
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
 #define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000048F0
-#define DDRSS_CTL_411_DATA 0x0000F320
-#define DDRSS_CTL_412_DATA 0x02020408
+#define DDRSS_CTL_410_DATA 0x000079B0
+#define DDRSS_CTL_411_DATA 0x000195A0
+#define DDRSS_CTL_412_DATA 0x0202080E
 #define DDRSS_CTL_413_DATA 0x03030202
 #define DDRSS_CTL_414_DATA 0x00000022
 #define DDRSS_CTL_415_DATA 0x00000000
@ -432,13 +433,13 @@
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
 #define DDRSS_CTL_422_DATA 0x0006001E
-#define DDRSS_CTL_423_DATA 0x000E0026
-#define DDRSS_CTL_424_DATA 0x000E0026
+#define DDRSS_CTL_423_DATA 0x0013002B
+#define DDRSS_CTL_424_DATA 0x0013002B
 #define DDRSS_CTL_425_DATA 0x00000000
 #define DDRSS_CTL_426_DATA 0x00000000
 #define DDRSS_CTL_427_DATA 0x02000000
 #define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x01080108
+#define DDRSS_CTL_429_DATA 0x05120512
 #define DDRSS_CTL_430_DATA 0x00000105
 #define DDRSS_CTL_431_DATA 0x00010101
 #define DDRSS_CTL_432_DATA 0x00010101
@ -447,8 +448,8 @@
 #define DDRSS_CTL_435_DATA 0x02000201
 #define DDRSS_CTL_436_DATA 0x02010000
 #define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x10060000
-#define DDRSS_CTL_439_DATA 0x00000110
+#define DDRSS_CTL_438_DATA 0x18060000
+#define DDRSS_CTL_439_DATA 0x00000118
 #define DDRSS_CTL_440_DATA 0xFFFFFFFF
 #define DDRSS_CTL_441_DATA 0xFFFFFFFF
 #define DDRSS_CTL_442_DATA 0x00000000
@ -504,10 +505,10 @@
 #define DDRSS_PI_32_DATA 0x00000000
 #define DDRSS_PI_33_DATA 0x01010102
 #define DDRSS_PI_34_DATA 0x00000000
-#define DDRSS_PI_35_DATA 0x000000AA
-#define DDRSS_PI_36_DATA 0x00000055
-#define DDRSS_PI_37_DATA 0x000000B5
-#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_35_DATA 0x55555A5A
+#define DDRSS_PI_36_DATA 0x5555A5A5
+#define DDRSS_PI_37_DATA 0x00005A5A
+#define DDRSS_PI_38_DATA 0x0000A5A5
 #define DDRSS_PI_39_DATA 0x00000056
 #define DDRSS_PI_40_DATA 0x000000A9
 #define DDRSS_PI_41_DATA 0x000000A9
@ -515,12 +516,12 @@
 #define DDRSS_PI_43_DATA 0x00000000
 #define DDRSS_PI_44_DATA 0x00000000
 #define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_46_DATA 0x00000017
 #define DDRSS_PI_47_DATA 0x000007D0
 #define DDRSS_PI_48_DATA 0x00000300
 #define DDRSS_PI_49_DATA 0x00000000
 #define DDRSS_PI_50_DATA 0x00000000
-#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_51_DATA 0x04080000
 #define DDRSS_PI_52_DATA 0x00010101
 #define DDRSS_PI_53_DATA 0x00000000
 #define DDRSS_PI_54_DATA 0x00030000
@ -632,18 +633,18 @@
 #define DDRSS_PI_160_DATA 0x00000000
 #define DDRSS_PI_161_DATA 0x00010000
 #define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x10100100
+#define DDRSS_PI_163_DATA 0x1B1B0100
 #define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x00000043
-#define DDRSS_PI_166_DATA 0x00020043
+#define DDRSS_PI_165_DATA 0x00000051
+#define DDRSS_PI_166_DATA 0x00020051
 #define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x1C080C04
-#define DDRSS_PI_169_DATA 0x000E1C08
+#define DDRSS_PI_168_DATA 0x300C0C04
+#define DDRSS_PI_169_DATA 0x000E300C
 #define DDRSS_PI_170_DATA 0x000000BB
-#define DDRSS_PI_171_DATA 0x000000E0
-#define DDRSS_PI_172_DATA 0x00000C28
-#define DDRSS_PI_173_DATA 0x000000E0
-#define DDRSS_PI_174_DATA 0x04000C28
+#define DDRSS_PI_171_DATA 0x00000176
+#define DDRSS_PI_172_DATA 0x00001448
+#define DDRSS_PI_173_DATA 0x00000176
+#define DDRSS_PI_174_DATA 0x04001448
 #define DDRSS_PI_175_DATA 0x01010404
 #define DDRSS_PI_176_DATA 0x00001501
 #define DDRSS_PI_177_DATA 0x00150015
@ -652,82 +653,82 @@
 #define DDRSS_PI_180_DATA 0x00000000
 #define DDRSS_PI_181_DATA 0x01010101
 #define DDRSS_PI_182_DATA 0x00000101
-#define DDRSS_PI_183_DATA 0x00000000
-#define DDRSS_PI_184_DATA 0x00000000
-#define DDRSS_PI_185_DATA 0x08040000
-#define DDRSS_PI_186_DATA 0x04040208
+#define DDRSS_PI_183_DATA 0x00000100
+#define DDRSS_PI_184_DATA 0x00000100
+#define DDRSS_PI_185_DATA 0x0E040100
+#define DDRSS_PI_186_DATA 0x0808020E
 #define DDRSS_PI_187_DATA 0x00040402
 #define DDRSS_PI_188_DATA 0x000C8034
-#define DDRSS_PI_189_DATA 0x0014003C
-#define DDRSS_PI_190_DATA 0x0014003C
+#define DDRSS_PI_189_DATA 0x00198041
+#define DDRSS_PI_190_DATA 0x00198041
 #define DDRSS_PI_191_DATA 0x01010101
 #define DDRSS_PI_192_DATA 0x0002000D
-#define DDRSS_PI_193_DATA 0x000200C8
-#define DDRSS_PI_194_DATA 0x010000C8
+#define DDRSS_PI_193_DATA 0x0002014E
+#define DDRSS_PI_194_DATA 0x0100014E
 #define DDRSS_PI_195_DATA 0x000E000E
-#define DDRSS_PI_196_DATA 0x00C90100
-#define DDRSS_PI_197_DATA 0x010000C9
-#define DDRSS_PI_198_DATA 0x00C900C9
+#define DDRSS_PI_196_DATA 0x014F0100
+#define DDRSS_PI_197_DATA 0x0100014F
+#define DDRSS_PI_198_DATA 0x014F014F
 #define DDRSS_PI_199_DATA 0x32103200
 #define DDRSS_PI_200_DATA 0x01013210
 #define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x0D09070D
-#define DDRSS_PI_203_DATA 0x0D09070D
-#define DDRSS_PI_204_DATA 0x0000C00D
+#define DDRSS_PI_202_DATA 0x140D080D
+#define DDRSS_PI_203_DATA 0x140D0810
+#define DDRSS_PI_204_DATA 0x0000C010
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x0016000D
-#define DDRSS_PI_209_DATA 0x001600C8
-#define DDRSS_PI_210_DATA 0x001100C8
+#define DDRSS_PI_208_DATA 0x001C000D
+#define DDRSS_PI_209_DATA 0x001C014E
+#define DDRSS_PI_210_DATA 0x0011014E
 #define DDRSS_PI_211_DATA 0x32000056
 #define DDRSS_PI_212_DATA 0x00000301
-#define DDRSS_PI_213_DATA 0x00580020
+#define DDRSS_PI_213_DATA 0x005A002A
 #define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00002000
-#define DDRSS_PI_216_DATA 0x32120058
+#define DDRSS_PI_215_DATA 0x00002A00
+#define DDRSS_PI_216_DATA 0x3212005A
 #define DDRSS_PI_217_DATA 0x09000301
 #define DDRSS_PI_218_DATA 0x04010504
 #define DDRSS_PI_219_DATA 0x0400062B
 #define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x1113090A
-#define DDRSS_PI_222_DATA 0x0000120C
-#define DDRSS_PI_223_DATA 0x240062B8
-#define DDRSS_PI_224_DATA 0x0C0C2003
-#define DDRSS_PI_225_DATA 0x1113090A
-#define DDRSS_PI_226_DATA 0x0000120C
-#define DDRSS_PI_227_DATA 0x240062B8
-#define DDRSS_PI_228_DATA 0x0C0C2003
-#define DDRSS_PI_229_DATA 0x0001760A
+#define DDRSS_PI_221_DATA 0x1C1F0B0A
+#define DDRSS_PI_222_DATA 0x00001D12
+#define DDRSS_PI_223_DATA 0x3C00A488
+#define DDRSS_PI_224_DATA 0x13142005
+#define DDRSS_PI_225_DATA 0x1C1F0B0E
+#define DDRSS_PI_226_DATA 0x00001D12
+#define DDRSS_PI_227_DATA 0x3C00A488
+#define DDRSS_PI_228_DATA 0x13142005
+#define DDRSS_PI_229_DATA 0x0001760E
 #define DDRSS_PI_230_DATA 0x00000E9C
-#define DDRSS_PI_231_DATA 0x00001850
-#define DDRSS_PI_232_DATA 0x0000F320
-#define DDRSS_PI_233_DATA 0x00001850
-#define DDRSS_PI_234_DATA 0x0000F320
-#define DDRSS_PI_235_DATA 0x00E6000F
-#define DDRSS_PI_236_DATA 0x030300E6
+#define DDRSS_PI_231_DATA 0x00002890
+#define DDRSS_PI_232_DATA 0x000195A0
+#define DDRSS_PI_233_DATA 0x00002890
+#define DDRSS_PI_234_DATA 0x000195A0
+#define DDRSS_PI_235_DATA 0x0180000F
+#define DDRSS_PI_236_DATA 0x03030180
 #define DDRSS_PI_237_DATA 0x00271003
 #define DDRSS_PI_238_DATA 0x000186A0
 #define DDRSS_PI_239_DATA 0x00000005
 #define DDRSS_PI_240_DATA 0x00000064
 #define DDRSS_PI_241_DATA 0x0000000F
-#define DDRSS_PI_242_DATA 0x00027100
+#define DDRSS_PI_242_DATA 0x000411AB
 #define DDRSS_PI_243_DATA 0x000186A0
 #define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000640
-#define DDRSS_PI_246_DATA 0x000000E6
-#define DDRSS_PI_247_DATA 0x00027100
+#define DDRSS_PI_245_DATA 0x00000A6B
+#define DDRSS_PI_246_DATA 0x00000180
+#define DDRSS_PI_247_DATA 0x000411AB
 #define DDRSS_PI_248_DATA 0x000186A0
 #define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000640
-#define DDRSS_PI_251_DATA 0x010000E6
+#define DDRSS_PI_250_DATA 0x00000A6B
+#define DDRSS_PI_251_DATA 0x01000180
 #define DDRSS_PI_252_DATA 0x00320040
 #define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x03200040
-#define DDRSS_PI_255_DATA 0x00010018
-#define DDRSS_PI_256_DATA 0x03200040
-#define DDRSS_PI_257_DATA 0x00000318
-#define DDRSS_PI_258_DATA 0x00280028
+#define DDRSS_PI_254_DATA 0x05360040
+#define DDRSS_PI_255_DATA 0x00010028
+#define DDRSS_PI_256_DATA 0x05360040
+#define DDRSS_PI_257_DATA 0x00000328
+#define DDRSS_PI_258_DATA 0x00430043
 #define DDRSS_PI_259_DATA 0x00040404
 #define DDRSS_PI_260_DATA 0x00000055
 #define DDRSS_PI_261_DATA 0x55003C5A
@ -746,27 +747,27 @@
 #define DDRSS_PI_274_DATA 0x00000000
 #define DDRSS_PI_275_DATA 0x002B0084
 #define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x362B12A4
+#define DDRSS_PI_277_DATA 0x362B24C4
 #define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x362B12A4
+#define DDRSS_PI_279_DATA 0x362B24C4
 #define DDRSS_PI_280_DATA 0x00150F27
 #define DDRSS_PI_281_DATA 0x002B0084
 #define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x362B12A4
+#define DDRSS_PI_283_DATA 0x362B24C4
 #define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x362B12A4
+#define DDRSS_PI_285_DATA 0x362B24C4
 #define DDRSS_PI_286_DATA 0x00150F27
 #define DDRSS_PI_287_DATA 0x002B0084
 #define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x362B12A4
+#define DDRSS_PI_289_DATA 0x362B24C4
 #define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x362B12A4
+#define DDRSS_PI_291_DATA 0x362B24C4
 #define DDRSS_PI_292_DATA 0x00150F27
 #define DDRSS_PI_293_DATA 0x002B0084
 #define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x362B12A4
+#define DDRSS_PI_295_DATA 0x362B24C4
 #define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x362B12A4
+#define DDRSS_PI_297_DATA 0x362B24C4
 #define DDRSS_PI_298_DATA 0x00150F27
 #define DDRSS_PI_299_DATA 0x00000000

@ -788,10 +789,10 @@
 #define DDRSS_PHY_15_DATA 0x00030066
 #define DDRSS_PHY_16_DATA 0x00000000
 #define DDRSS_PHY_17_DATA 0x00000301
-#define DDRSS_PHY_18_DATA 0x0000AAAA
-#define DDRSS_PHY_19_DATA 0x00005555
-#define DDRSS_PHY_20_DATA 0x0000B5B5
-#define DDRSS_PHY_21_DATA 0x00004A4A
+#define DDRSS_PHY_18_DATA 0x55555A5A
+#define DDRSS_PHY_19_DATA 0x5555A5A5
+#define DDRSS_PHY_20_DATA 0x00005A5A
+#define DDRSS_PHY_21_DATA 0x0000A5A5
 #define DDRSS_PHY_22_DATA 0x00005656
 #define DDRSS_PHY_23_DATA 0x0000A9A9
 #define DDRSS_PHY_24_DATA 0x0000A9A9
@ -862,7 +863,7 @@
 #define DDRSS_PHY_89_DATA 0x10100303
 #define DDRSS_PHY_90_DATA 0x10101010
 #define DDRSS_PHY_91_DATA 0x10101010
-#define DDRSS_PHY_92_DATA 0x00011010
+#define DDRSS_PHY_92_DATA 0x00021010
 #define DDRSS_PHY_93_DATA 0x00100010
 #define DDRSS_PHY_94_DATA 0x00100010
 #define DDRSS_PHY_95_DATA 0x00100010
@ -872,18 +873,18 @@
 #define DDRSS_PHY_99_DATA 0x31C06000
 #define DDRSS_PHY_100_DATA 0x07AB0340
 #define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x05040001
+#define DDRSS_PHY_102_DATA 0x09080001
 #define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C053E42
-#define DDRSS_PHY_105_DATA 0x0F0C1D01
+#define DDRSS_PHY_104_DATA 0x0C063E42
+#define DDRSS_PHY_105_DATA 0x0F0C2701
 #define DDRSS_PHY_106_DATA 0x01000140
-#define DDRSS_PHY_107_DATA 0x0C000420
-#define DDRSS_PHY_108_DATA 0x000001CC
+#define DDRSS_PHY_107_DATA 0x04000420
+#define DDRSS_PHY_108_DATA 0x00000255
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
 #define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x00052010
+#define DDRSS_PHY_113_DATA 0x00092010
 #define DDRSS_PHY_114_DATA 0x76543210
 #define DDRSS_PHY_115_DATA 0x00000008
 #define DDRSS_PHY_116_DATA 0x02800280
@ -900,8 +901,8 @@
 #define DDRSS_PHY_127_DATA 0x00A000A0
 #define DDRSS_PHY_128_DATA 0x00A000A0
 #define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x011900A0
-#define DDRSS_PHY_131_DATA 0x01A00002
+#define DDRSS_PHY_130_DATA 0x01C400A0
+#define DDRSS_PHY_131_DATA 0x01A00003
 #define DDRSS_PHY_132_DATA 0x00000000
 #define DDRSS_PHY_133_DATA 0x00000000
 #define DDRSS_PHY_134_DATA 0x00080200
@ -1044,10 +1045,10 @@
 #define DDRSS_PHY_271_DATA 0x00030066
 #define DDRSS_PHY_272_DATA 0x00000000
 #define DDRSS_PHY_273_DATA 0x00000301
-#define DDRSS_PHY_274_DATA 0x0000AAAA
-#define DDRSS_PHY_275_DATA 0x00005555
-#define DDRSS_PHY_276_DATA 0x0000B5B5
-#define DDRSS_PHY_277_DATA 0x00004A4A
+#define DDRSS_PHY_274_DATA 0x55555A5A
+#define DDRSS_PHY_275_DATA 0x5555A5A5
+#define DDRSS_PHY_276_DATA 0x00005A5A
+#define DDRSS_PHY_277_DATA 0x0000A5A5
 #define DDRSS_PHY_278_DATA 0x00005656
 #define DDRSS_PHY_279_DATA 0x0000A9A9
 #define DDRSS_PHY_280_DATA 0x0000A9A9
@ -1118,7 +1119,7 @@
 #define DDRSS_PHY_345_DATA 0x10100303
 #define DDRSS_PHY_346_DATA 0x10101010
 #define DDRSS_PHY_347_DATA 0x10101010
-#define DDRSS_PHY_348_DATA 0x00011010
+#define DDRSS_PHY_348_DATA 0x00021010
 #define DDRSS_PHY_349_DATA 0x00100010
 #define DDRSS_PHY_350_DATA 0x00100010
 #define DDRSS_PHY_351_DATA 0x00100010
@ -1128,18 +1129,18 @@
 #define DDRSS_PHY_355_DATA 0x31C06000
 #define DDRSS_PHY_356_DATA 0x07AB0340
 #define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x05040001
+#define DDRSS_PHY_358_DATA 0x09080001
 #define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C053E42
-#define DDRSS_PHY_361_DATA 0x0F0C1D01
+#define DDRSS_PHY_360_DATA 0x0C063E42
+#define DDRSS_PHY_361_DATA 0x0F0C2701
 #define DDRSS_PHY_362_DATA 0x01000140
-#define DDRSS_PHY_363_DATA 0x0C000420
-#define DDRSS_PHY_364_DATA 0x000001CC
+#define DDRSS_PHY_363_DATA 0x04000420
+#define DDRSS_PHY_364_DATA 0x00000255
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
 #define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x00052010
+#define DDRSS_PHY_369_DATA 0x00092010
 #define DDRSS_PHY_370_DATA 0x76543210
 #define DDRSS_PHY_371_DATA 0x00000008
 #define DDRSS_PHY_372_DATA 0x02800280
@ -1156,8 +1157,8 @@
 #define DDRSS_PHY_383_DATA 0x00A000A0
 #define DDRSS_PHY_384_DATA 0x00A000A0
 #define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x011900A0
-#define DDRSS_PHY_387_DATA 0x01A00002
+#define DDRSS_PHY_386_DATA 0x01C400A0
+#define DDRSS_PHY_387_DATA 0x01A00003
 #define DDRSS_PHY_388_DATA 0x00000000
 #define DDRSS_PHY_389_DATA 0x00000000
 #define DDRSS_PHY_390_DATA 0x00080200
@ -1300,10 +1301,10 @@
 #define DDRSS_PHY_527_DATA 0x00030066
 #define DDRSS_PHY_528_DATA 0x00000000
 #define DDRSS_PHY_529_DATA 0x00000301
-#define DDRSS_PHY_530_DATA 0x0000AAAA
-#define DDRSS_PHY_531_DATA 0x00005555
-#define DDRSS_PHY_532_DATA 0x0000B5B5
-#define DDRSS_PHY_533_DATA 0x00004A4A
+#define DDRSS_PHY_530_DATA 0x55555A5A
+#define DDRSS_PHY_531_DATA 0x5555A5A5
+#define DDRSS_PHY_532_DATA 0x00005A5A
+#define DDRSS_PHY_533_DATA 0x0000A5A5
 #define DDRSS_PHY_534_DATA 0x00005656
 #define DDRSS_PHY_535_DATA 0x0000A9A9
 #define DDRSS_PHY_536_DATA 0x0000A9A9
@ -1374,7 +1375,7 @@
 #define DDRSS_PHY_601_DATA 0x10100303
 #define DDRSS_PHY_602_DATA 0x10101010
 #define DDRSS_PHY_603_DATA 0x10101010
-#define DDRSS_PHY_604_DATA 0x00011010
+#define DDRSS_PHY_604_DATA 0x00021010
 #define DDRSS_PHY_605_DATA 0x00100010
 #define DDRSS_PHY_606_DATA 0x00100010
 #define DDRSS_PHY_607_DATA 0x00100010
@ -1384,18 +1385,18 @@
 #define DDRSS_PHY_611_DATA 0x31C06000
 #define DDRSS_PHY_612_DATA 0x07AB0340
 #define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x05040001
+#define DDRSS_PHY_614_DATA 0x09080001
 #define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C053E42
-#define DDRSS_PHY_617_DATA 0x0F0C1D01
+#define DDRSS_PHY_616_DATA 0x0C063E42
+#define DDRSS_PHY_617_DATA 0x0F0C2701
 #define DDRSS_PHY_618_DATA 0x01000140
-#define DDRSS_PHY_619_DATA 0x0C000420
-#define DDRSS_PHY_620_DATA 0x000001CC
+#define DDRSS_PHY_619_DATA 0x04000420
+#define DDRSS_PHY_620_DATA 0x00000255
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
 #define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x00052010
+#define DDRSS_PHY_625_DATA 0x00092010
 #define DDRSS_PHY_626_DATA 0x76543210
 #define DDRSS_PHY_627_DATA 0x00000008
 #define DDRSS_PHY_628_DATA 0x02800280
@ -1412,8 +1413,8 @@
 #define DDRSS_PHY_639_DATA 0x00A000A0
 #define DDRSS_PHY_640_DATA 0x00A000A0
 #define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x011900A0
-#define DDRSS_PHY_643_DATA 0x01A00002
+#define DDRSS_PHY_642_DATA 0x01C400A0
+#define DDRSS_PHY_643_DATA 0x01A00003
 #define DDRSS_PHY_644_DATA 0x00000000
 #define DDRSS_PHY_645_DATA 0x00000000
 #define DDRSS_PHY_646_DATA 0x00080200
@ -1556,10 +1557,10 @@
 #define DDRSS_PHY_783_DATA 0x00030066
 #define DDRSS_PHY_784_DATA 0x00000000
 #define DDRSS_PHY_785_DATA 0x00000301
-#define DDRSS_PHY_786_DATA 0x0000AAAA
-#define DDRSS_PHY_787_DATA 0x00005555
-#define DDRSS_PHY_788_DATA 0x0000B5B5
-#define DDRSS_PHY_789_DATA 0x00004A4A
+#define DDRSS_PHY_786_DATA 0x55555A5A
+#define DDRSS_PHY_787_DATA 0x5555A5A5
+#define DDRSS_PHY_788_DATA 0x00005A5A
+#define DDRSS_PHY_789_DATA 0x0000A5A5
 #define DDRSS_PHY_790_DATA 0x00005656
 #define DDRSS_PHY_791_DATA 0x0000A9A9
 #define DDRSS_PHY_792_DATA 0x0000A9A9
@ -1630,7 +1631,7 @@
 #define DDRSS_PHY_857_DATA 0x10100303
 #define DDRSS_PHY_858_DATA 0x10101010
 #define DDRSS_PHY_859_DATA 0x10101010
-#define DDRSS_PHY_860_DATA 0x00011010
+#define DDRSS_PHY_860_DATA 0x00021010
 #define DDRSS_PHY_861_DATA 0x00100010
 #define DDRSS_PHY_862_DATA 0x00100010
 #define DDRSS_PHY_863_DATA 0x00100010
@ -1640,18 +1641,18 @@
 #define DDRSS_PHY_867_DATA 0x31C06000
 #define DDRSS_PHY_868_DATA 0x07AB0340
 #define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x05040001
+#define DDRSS_PHY_870_DATA 0x09080001
 #define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C053E42
-#define DDRSS_PHY_873_DATA 0x0F0C1D01
+#define DDRSS_PHY_872_DATA 0x0C063E42
+#define DDRSS_PHY_873_DATA 0x0F0C2701
 #define DDRSS_PHY_874_DATA 0x01000140
-#define DDRSS_PHY_875_DATA 0x0C000420
-#define DDRSS_PHY_876_DATA 0x000001CC
+#define DDRSS_PHY_875_DATA 0x04000420
+#define DDRSS_PHY_876_DATA 0x00000255
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
 #define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x00052010
+#define DDRSS_PHY_881_DATA 0x00092010
 #define DDRSS_PHY_882_DATA 0x76543210
 #define DDRSS_PHY_883_DATA 0x00000008
 #define DDRSS_PHY_884_DATA 0x02800280
@ -1668,13 +1669,13 @@
 #define DDRSS_PHY_895_DATA 0x00A000A0
 #define DDRSS_PHY_896_DATA 0x00A000A0
 #define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x011900A0
-#define DDRSS_PHY_899_DATA 0x01A00002
+#define DDRSS_PHY_898_DATA 0x01C400A0
+#define DDRSS_PHY_899_DATA 0x01A00003
 #define DDRSS_PHY_900_DATA 0x00000000
 #define DDRSS_PHY_901_DATA 0x00000000
 #define DDRSS_PHY_902_DATA 0x00080200
 #define DDRSS_PHY_903_DATA 0x00000000
-#define DDRSS_PHY_904_DATA 0x20202010
+#define DDRSS_PHY_904_DATA 0x20202000
 #define DDRSS_PHY_905_DATA 0x20202020
 #define DDRSS_PHY_906_DATA 0xF0F02020
 #define DDRSS_PHY_907_DATA 0x00000000
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-j7200-som-p0.dtsi"
-#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
+#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
 #include "k3-j721e-ddr.dtsi"

 / {
@ -79,6 +79,16 @@
 		mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
 		mbox-names = "tx", "rx";
 	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <3>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&mcu_secproxy 21>,
+			<&mcu_secproxy 23>;
+		u-boot,dm-spl;
+	};
 };

 &dmsc {
@ -276,4 +286,11 @@
 	};
 };

+&mcu_ringacc {
+	ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+	ti,sci = <&dm_tifs>;
+};
 #include "k3-j7200-common-proc-board-u-boot.dtsi"
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@ -46,7 +46,7 @@
 		compatible = "ti,omap5430-timer";
 		reg = <0x0 0x40400000 0x0 0x80>;
 		ti,timer-alwon;
-		clock-frequency = <25000000>;
+		clock-frequency = <250000000>;
 		u-boot,dm-spl;
 	};

@ -54,10 +54,24 @@
 		u-boot,dm-spl;

 		ringacc@2b800000 {
+			reg =	<0x0 0x2b800000 0x0 0x400000>,
+				<0x0 0x2b000000 0x0 0x400000>,
+				<0x0 0x28590000 0x0 0x100>,
+				<0x0 0x2a500000 0x0 0x40000>,
+				<0x0 0x28440000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 			u-boot,dm-spl;
 		};

 		dma-controller@285c0000 {
+			reg =	<0x0 0x285c0000 0x0 0x100>,
+				<0x0 0x284c0000 0x0 0x4000>,
+				<0x0 0x2a800000 0x0 0x40000>,
+				<0x0 0x284a0000 0x0 0x4000>,
+				<0x0 0x2aa00000 0x0 0x40000>,
+				<0x0 0x28400000 0x0 0x2000>;
+			reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+					    "tchanrt", "rflow";
 			u-boot,dm-spl;
 		};
 	};
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@ -76,6 +76,16 @@
 		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 		#thermal-sensor-cells = <1>;
 	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <3>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&mcu_secproxy 21>,
+			<&mcu_secproxy 23>;
+		u-boot,dm-spl;
+	};
 };

 &cbass_main {
@ -345,3 +355,11 @@
 		u-boot,dm-spl;
 	};
 };
+
+&mcu_ringacc {
+	ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+	ti,sci = <&dm_tifs>;
+};
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@ -147,6 +147,24 @@ config SYS_K3_SPL_ATF
 	  Enabling this will try to start Cortex-A (typically with ATF)
 	  after SPL from R5.

+config K3_ATF_LOAD_ADDR
+	hex "Load address of ATF image"
+	default 0x70000000
+	help
+	  The load address for the ATF image. This value defaults to 0x70000000
+	  if not provided in the board defconfig file.
+
+config K3_DM_FW
+	bool "Separate DM firmware image"
+	depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+	default y
+	help
+	  Enabling this will indicate that the system has separate DM
+	  and TIFS firmware images in place, instead of a single SYSFW
+	  firmware. Due to DM being executed on the same core as R5 SPL
+	  bootloader, it makes RM and PM services not being available
+	  during R5 SPL execution time.
+
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/j721e/Kconfig"
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@ -4,7 +4,7 @@
 #	Lokesh Vutla <lokeshvutla@ti.com>

 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
 obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@ -8,6 +8,7 @@
 */

 #include <common.h>
+#include <fdt_support.h>
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
@ -106,6 +107,38 @@ void do_dt_magic(void)
 }
 #endif

+#if CONFIG_IS_ENABLED(USB_STORAGE)
+static int fixup_usb_boot(const void *fdt_blob)
+{
+	int ret = 0;
+
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_USB:
+		/*
+		 * If the boot mode is host, fixup the dr_mode to host
+		 * before cdns3 bind takes place
+		 */
+		ret = fdt_find_and_setprop((void *)fdt_blob,
+					   "/bus@f4000/cdns-usb@f900000/usb@f400000",
+					   "dr_mode", "host", 5, 0);
+		if (ret)
+			printf("%s: fdt_find_and_setprop() failed:%d\n",
+			       __func__, ret);
+		fallthrough;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+	/* Can use the pointer from the function parameters */
+	return fixup_usb_boot(fdt_blob);
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
 #if defined(CONFIG_K3_LOAD_SYSFW)
@ -192,8 +225,11 @@ static u32 __get_backup_bootmedia(u32 main_devstat)
 	case BACKUP_BOOT_DEVICE_UART:
 		return BOOT_DEVICE_UART;

-	case BACKUP_BOOT_DEVICE_USB:
-		return BOOT_DEVICE_USB;
+	case BACKUP_BOOT_DEVICE_DFU:
+		if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+			return BOOT_DEVICE_USB;
+		return BOOT_DEVICE_DFU;
+

 	case BACKUP_BOOT_DEVICE_ETHERNET:
 		return BOOT_DEVICE_ETHERNET;
@ -245,6 +281,12 @@ static u32 __get_primary_bootmedia(u32 main_devstat)
 			return BOOT_DEVICE_MMC2;
 		return BOOT_DEVICE_MMC1;

+	case BOOT_DEVICE_DFU:
+		if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+		    MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+			return BOOT_DEVICE_USB;
+		return BOOT_DEVICE_DFU;
+
 	case BOOT_DEVICE_NOBOOT:
 		return BOOT_DEVICE_RAM;
 	}
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@ -28,6 +28,27 @@
 #include <elf.h>
 #include <soc.h>

+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
+enum {
+	IMAGE_ID_ATF,
+	IMAGE_ID_OPTEE,
+	IMAGE_ID_SPL,
+	IMAGE_ID_DM_FW,
+	IMAGE_AMT,
+};
+
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
+static const char *image_os_match[IMAGE_AMT] = {
+	"arm-trusted-firmware",
+	"tee",
+	"U-Boot",
+	"DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
 	struct udevice *dev;
@ -107,7 +128,7 @@ int early_console_init(void)
 }
 #endif

-#ifdef CONFIG_SYS_K3_SPL_ATF
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)

 void init_env(void)
 {
@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	typedef void __noreturn (*image_entry_noargs_t)(void);
 	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 	u32 loadaddr = 0;
-	int ret, size;
+	int ret, size = 0;

 	/* Release all the exclusive devices held by SPL before starting ATF */
 	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@ -191,16 +212,22 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 		panic("rproc failed to be initialized (%d)\n", ret);

 	init_env();
-	start_non_linux_remote_cores();
-	size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
-			     &loadaddr);

+	if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+		start_non_linux_remote_cores();
+		size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+				     &loadaddr);
+	}

 	/*
 	 * It is assumed that remoteproc device 1 is the corresponding
 	 * Cortex-A core which runs ATF. Make sure DT reflects the same.
 	 */
-	ret = rproc_load(1, spl_image->entry_point, 0x200);
+	if (!fit_image_info[IMAGE_ID_ATF].image_start)
+		fit_image_info[IMAGE_ID_ATF].image_start =
+			spl_image->entry_point;
+
+	ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
 	if (ret)
 		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);

@ -210,7 +237,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	ret = rproc_start(1);
 	if (ret)
 		panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
-	if (!(size > 0 && valid_elf_image(loadaddr))) {
+	if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+	    !(size > 0 && valid_elf_image(loadaddr))) {
 		debug("Shutting down...\n");
 		release_resources_for_core_shutdown();

@ -218,13 +246,54 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 			asm volatile("wfe");
 	}

-	image_entry_noargs_t image_entry =
-		(image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+	if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+		loadaddr = load_elf_image_phdr(loadaddr);
+	} else {
+		loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+		if (valid_elf_image(loadaddr))
+			loadaddr = load_elf_image_phdr(loadaddr);
+	}
+
+	debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+	image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;

 	image_entry();
 }
 #endif

+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
+{
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
+	int len;
+	int i;
+	const char *os;
+	u32 addr;
+
+	os = fdt_getprop(fit, node, "os", &len);
+	addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+	debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+	      addr, *p_size, os);
+
+	for (i = 0; i < IMAGE_AMT; i++) {
+		if (!strcmp(os, image_os_match[i])) {
+			fit_image_info[i].image_start = addr;
+			fit_image_info[i].image_len = *p_size;
+			debug("%s: matched image for ID %d\n", __func__, i);
+			break;
+		}
+	}
+#endif
+
+#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
+	ti_secure_image_post_process(p_image, p_size);
+#endif
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT)
 int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
 {
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@ -28,3 +28,4 @@ void k3_sysfw_print_ver(void);
 void spl_enable_dcache(void);
 void mmr_unlock(phys_addr_t base, u32 partition);
 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
+void ti_secure_image_post_process(void **p_image, size_t *p_size);
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@ -49,6 +49,10 @@ endif

 ifdef CONFIG_ARM64

+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 SPL_ITS := u-boot-spl-k3_HS.its
 $(SPL_ITS): export IS_HS=1
@ -67,6 +71,7 @@ endif
 quiet_cmd_k3_mkits = MKITS   $@
 cmd_k3_mkits = \
 	$(srctree)/tools/k3_fit_atf.sh \
+	$(CONFIG_K3_ATF_LOAD_ADDR) \
 	$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@

 $(SPL_ITS): FORCE
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@ -7,8 +7,6 @@
 #ifndef __ASM_ARCH_AM64_HARDWARE_H
 #define __ASM_ARCH_AM64_HARDWARE_H

-#include <config.h>
-
 #define CTRL_MMR0_BASE					0x43000000
 #define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)

@ -30,6 +28,11 @@
 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT		2
 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK		0x04

+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT		1
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK		0x02
+
+#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK		0x01
+
 /*
 * The CTRL_MMR and PADCFG_MMR memory space is divided into several
 * equally-spaced partitions, so defining the partition size allows us to
@ -49,7 +52,7 @@

 #define ROM_ENTENDED_BOOT_DATA_INFO			0x701beb00

-/* Use Last 1K as Scratch pad */
-#define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x701bfc00
+/* Use Last 2K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x7019f800

 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */
--- a/arch/arm/mach-k3/include/mach/am64_spl.h
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@ -19,7 +19,8 @@
 #define BOOT_DEVICE_MMC			0x08
 #define BOOT_DEVICE_EMMC		0x09

-#define BOOT_DEVICE_USB			0x0A
+#define BOOT_DEVICE_USB			0x2A
+#define BOOT_DEVICE_DFU			0x0A
 #define BOOT_DEVICE_GPMC_NOR		0x0C
 #define BOOT_DEVICE_PCIE		0x0D
 #define BOOT_DEVICE_XSPI		0x0E
@ -32,12 +33,13 @@
 #define BOOT_DEVICE_MMC2_2		0x1F

 /* Backup BootMode devices */
-#define BACKUP_BOOT_DEVICE_USB		0x01
+#define BACKUP_BOOT_DEVICE_DFU		0x01
 #define BACKUP_BOOT_DEVICE_UART		0x03
 #define BACKUP_BOOT_DEVICE_ETHERNET	0x04
 #define BACKUP_BOOT_DEVICE_MMC		0x05
 #define BACKUP_BOOT_DEVICE_SPI		0x06
 #define BACKUP_BOOT_DEVICE_I2C		0x07
+#define BACKUP_BOOT_DEVICE_USB		0x09

 #define K3_PRIMARY_BOOTMODE		0x0

--- a/arch/arm/mach-k3/j7200/Makefile
+++ b/arch/arm/mach-k3/j7200/Makefile
@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
--- a/arch/arm/mach-k3/j7200/clk-data.c
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+	"osc_19_2_mhz",
+	"osc_20_mhz",
+	"osc_24_mhz",
+	"osc_25_mhz",
+	"osc_26_mhz",
+	"osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+	"board_0_mcu_ospi0_dqs_out",
+	"fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+	"wkup_fref_clksel_out0",
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const wkup_obsclk_mux_out0_parents[] = {
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+	NULL,
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout1_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout2_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout2_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout3_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+	"gluelogic_hfosc0_clkout",
+	"board_0_wkup_lf_clkin_out",
+};
+
+static const char * const main_pll4_xref_sel_out0_parents[] = {
+	"main_pll_hfosc_sel_out4",
+	"board_0_ext_refclk1_out",
+};
+
+static const char * const mcu_clkout_mux_out0_parents[] = {
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+	"main_pll_hfosc_sel_out0",
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const mcu_obsclk_outmux_out0_parents[] = {
+	"mcu_obsclk_div_out0",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const clkout_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout0_clk",
+	"hsdiv4_16fft_main_3_hsdivout0_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv2_16fft_main_0_hsdivout6_clk",
+	"board_0_mcu_cpts0_rft_clk_out",
+	"board_0_cpts0_rft_clk_out",
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const obsclk1_mux_out0_parents[] = {
+	NULL,
+	"hsdiv0_16fft_main_8_hsdivout0_clk",
+	NULL,
+	NULL,
+};
+
+static const char * const gpmc_fclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout3_clk",
+	"hsdiv4_16fft_main_2_hsdivout1_clk",
+	"hsdiv4_16fft_main_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const audio_refclko_mux_out0_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv2_16fft_main_4_hsdivout2_clk",
+	NULL,
+	NULL,
+	NULL,
+};
+
+static const char * const audio_refclko_mux_out1_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv2_16fft_main_4_hsdivout2_clk",
+	NULL,
+	NULL,
+	NULL,
+};
+
+static const char * const obsclk0_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+	"hsdiv4_16fft_main_1_hsdivout0_clk",
+	"hsdiv4_16fft_main_2_hsdivout0_clk",
+	"hsdiv4_16fft_main_3_hsdivout0_clk",
+	"hsdiv2_16fft_main_4_hsdivout0_clk",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv0_16fft_main_12_hsdivout0_clk",
+	"obsclk1_mux_out0",
+	"hsdiv1_16fft_main_14_hsdivout0_clk",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+	"board_0_wkup_lf_clkin_out",
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+	"board_0_hfosc1_clk_out",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const struct clk_data clk_list[] = {
+	CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+	CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+	CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+	CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+	CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+	CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0),
+	CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
+	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+	CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
+	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
+	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
+	CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
+	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+	CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+	CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+	CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
+	CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
+	CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0),
+	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
+	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+	CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
+	CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
+	CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
+	CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
+	CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
+	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
+	CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
+	CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
+	CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
+	CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+	CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+	CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
+	CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
+	CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
+	CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
+	CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
+	CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0),
+	CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0),
+	CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
+	CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+	DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
+	DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+	DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+	DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+	DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
+	DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+	DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
+	DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
+	DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
+	DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"),
+	DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+	DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"),
+	DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
+	DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"),
+	DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"),
+	DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"),
+	DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"),
+	DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"),
+	DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"),
+	DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(149, 2, "mcuusart_clk_sel_out0"),
+	DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+	DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"),
+	DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(157, 5, "osbclk0_div_out0"),
+	DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+	DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"),
+	DEV_CLK(157, 15, "mcu_obsclk_div_out0"),
+	DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(157, 35, "clkout_mux_out0"),
+	DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+	DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+	DEV_CLK(157, 38, "osbclk0_div_out0"),
+	DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
+	DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+	DEV_CLK(157, 69, "mcu_clkout_mux_out0"),
+	DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(157, 77, "audio_refclko_mux_out1"),
+	DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"),
+	DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
+	DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"),
+	DEV_CLK(157, 131, "audio_refclko_mux_out0"),
+	DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"),
+	DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"),
+	DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
+	DEV_CLK(157, 184, "gpmc_fclk_sel_out0"),
+	DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(157, 192, "osbclk0_div_out0"),
+	DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+	DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+	DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"),
+	DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+	DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"),
+	DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+	DEV_CLK(157, 206, "obsclk1_mux_out0"),
+	DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"),
+	DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"),
+	DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+	DEV_CLK(157, 223, "board_0_hfosc1_clk_out"),
+	DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"),
+	DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"),
+	DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
+	DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(288, 12, "usb0_refclk_sel_out0"),
+	DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
+	DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata j7200_clk_platdata = {
+	.clk_list = clk_list,
+	.clk_list_cnt = 108,
+	.soc_dev_clk_data = soc_dev_clk_data,
+	.soc_dev_clk_data_cnt = 127,
+};
--- a/arch/arm/mach-k3/j7200/dev-data.c
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific device platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+	[0] = PSC(0, 0x00400000),
+	[1] = PSC(1, 0x42000000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+	[0] = PSC_PD(0, &soc_psc_list[0], NULL),
+	[1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]),
+	[2] = PSC_PD(14, &soc_psc_list[0], NULL),
+	[3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]),
+	[4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]),
+	[5] = PSC_PD(0, &soc_psc_list[1], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[14]),
+	[2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
+	[3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[6] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[7] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL),
+	[8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL),
+	[9] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
+	[10] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+	[11] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[8]),
+	[12] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[13] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[14] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[15] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[16] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[5], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(30, &soc_lpsc_list[0]),
+	PSC_DEV(61, &soc_lpsc_list[1]),
+	PSC_DEV(90, &soc_lpsc_list[2]),
+	PSC_DEV(8, &soc_lpsc_list[3]),
+	PSC_DEV(288, &soc_lpsc_list[4]),
+	PSC_DEV(92, &soc_lpsc_list[5]),
+	PSC_DEV(91, &soc_lpsc_list[6]),
+	PSC_DEV(146, &soc_lpsc_list[7]),
+	PSC_DEV(4, &soc_lpsc_list[8]),
+	PSC_DEV(4, &soc_lpsc_list[9]),
+	PSC_DEV(202, &soc_lpsc_list[10]),
+	PSC_DEV(203, &soc_lpsc_list[11]),
+	PSC_DEV(102, &soc_lpsc_list[12]),
+	PSC_DEV(103, &soc_lpsc_list[12]),
+	PSC_DEV(104, &soc_lpsc_list[12]),
+	PSC_DEV(154, &soc_lpsc_list[12]),
+	PSC_DEV(149, &soc_lpsc_list[12]),
+	PSC_DEV(113, &soc_lpsc_list[13]),
+	PSC_DEV(197, &soc_lpsc_list[13]),
+	PSC_DEV(103, &soc_lpsc_list[14]),
+	PSC_DEV(104, &soc_lpsc_list[15]),
+	PSC_DEV(102, &soc_lpsc_list[16]),
+};
+
+const struct ti_k3_pd_platdata j7200_pd_platdata = {
+	.psc = soc_psc_list,
+	.pd = soc_pd_list,
+	.lpsc = soc_lpsc_list,
+	.devs = soc_dev_list,
+	.num_psc = 2,
+	.num_pd = 6,
+	.num_lpsc = 17,
+	.num_devs = 22,
+};
--- a/arch/arm/mach-k3/j721e/Makefile
+++ b/arch/arm/mach-k3/j721e/Makefile
@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
--- a/arch/arm/mach-k3/j721e/clk-data.c
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+	"osc_19_2_mhz",
+	"osc_20_mhz",
+	"osc_24_mhz",
+	"osc_25_mhz",
+	"osc_26_mhz",
+	"osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+	"board_0_mcu_ospi0_dqs_out",
+	"fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
+	"board_0_mcu_ospi1_dqs_out",
+	"fss_mcu_0_ospi_1_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+	"wkup_fref_clksel_out0",
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll25_hfosc_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out13_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out15_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out16_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out17_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out18_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out19_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out23_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out5_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out6_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const usb1_refclk_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_hfosc1_clk_out",
+};
+
+static const char * const wkup_obsclk_mux_out0_parents[] = {
+	"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+	NULL,
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout1_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout2_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+	"j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout2_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout3_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+	"gluelogic_hfosc0_clkout",
+	"gluelogic_lpxosc_clkout",
+};
+
+static const char * const main_pll15_xref_sel_out0_parents[] = {
+	"main_pll_hfosc_sel_out15",
+	"board_0_ext_refclk1_out",
+};
+
+static const char * const main_pll24_hfosc_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"board_0_mlb0_mlbcp_out",
+};
+
+static const char * const main_pll4_xref_sel_out0_parents[] = {
+	"main_pll_hfosc_sel_out4",
+	"board_0_ext_refclk1_out",
+};
+
+static const char * const mcu_clkout_mux_out0_parents[] = {
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+	"main_pll_hfosc_sel_out0",
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const mcu_obsclk_outmux_out0_parents[] = {
+	"mcu_obsclk_div_out0",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const obsclk1_mux_out0_parents[] = {
+	"hsdiv0_16fft_main_7_hsdivout0_clk",
+	"hsdiv0_16fft_main_8_hsdivout0_clk",
+	"hsdiv3_16fft_main_13_hsdivout0_clk",
+	NULL,
+};
+
+static const char * const clkout_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout0_clk",
+	"hsdiv4_16fft_main_3_hsdivout0_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_2_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_2_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv3_16fft_main_0_hsdivout6_clk",
+	"board_0_mcu_cpts0_rft_clk_out",
+	"board_0_cpts0_rft_clk_out",
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const gpmc_fclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout3_clk",
+	"hsdiv4_16fft_main_2_hsdivout1_clk",
+	"hsdiv4_16fft_main_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const mcasp_ahclko_mux_out0_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv3_16fft_main_4_hsdivout2_clk",
+	"hsdiv3_16fft_main_15_hsdivout2_clk",
+	NULL,
+	NULL,
+	"board_0_audio_ext_refclk0_out",
+};
+
+static const char * const mcasp_ahclko_mux_out1_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv3_16fft_main_4_hsdivout2_clk",
+	"hsdiv3_16fft_main_15_hsdivout2_clk",
+	NULL,
+	NULL,
+	"board_0_audio_ext_refclk1_out",
+};
+
+static const char * const mcasp_ahclko_mux_out2_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv3_16fft_main_4_hsdivout2_clk",
+	"hsdiv3_16fft_main_15_hsdivout2_clk",
+	NULL,
+	NULL,
+	"board_0_audio_ext_refclk2_out",
+};
+
+static const char * const mcasp_ahclko_mux_out3_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv3_16fft_main_4_hsdivout2_clk",
+	"hsdiv3_16fft_main_15_hsdivout2_clk",
+	NULL,
+	NULL,
+	"board_0_audio_ext_refclk3_out",
+};
+
+static const char * const obsclk0_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+	"hsdiv4_16fft_main_1_hsdivout0_clk",
+	"hsdiv4_16fft_main_2_hsdivout0_clk",
+	"hsdiv4_16fft_main_3_hsdivout0_clk",
+	"hsdiv3_16fft_main_4_hsdivout0_clk",
+	"hsdiv3_16fft_main_5_hsdivout0_clk",
+	"hsdiv0_16fft_main_6_hsdivout0_clk",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv0_16fft_main_12_hsdivout0_clk",
+	"obsclk1_mux_out0",
+	"hsdiv1_16fft_main_14_hsdivout0_clk",
+	"hsdiv3_16fft_main_15_hsdivout0_clk",
+	"hsdiv1_16fft_main_16_hsdivout0_clk",
+	"hsdiv1_16fft_main_17_hsdivout0_clk",
+	"hsdiv1_16fft_main_18_hsdivout0_clk",
+	"hsdiv1_16fft_main_19_hsdivout0_clk",
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv1_16fft_main_23_hsdivout0_clk",
+	"hsdiv0_16fft_main_24_hsdivout0_clk",
+	"hsdiv1_16fft_main_25_hsdivout0_clk",
+	NULL,
+	"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+	"gluelogic_lpxosc_clkout",
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+	"board_0_hfosc1_clk_out",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const struct clk_data clk_list[] = {
+	CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+	CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+	CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+	CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
+	CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+	CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
+	CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
+	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+	CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
+	CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+	CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
+	CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
+	CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
+	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+	CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+	CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+	CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+	CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0),
+	CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
+	CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
+	CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0),
+	CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0),
+	CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0),
+	CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0),
+	CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0),
+	CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0),
+	CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0),
+	CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
+	CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
+	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
+	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
+	CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+	CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
+	CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
+	CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
+	CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0),
+	CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0),
+	CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
+	CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
+	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0),
+	CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0),
+	CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0),
+	CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
+	CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
+	CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
+	CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
+	CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
+	CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+	CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+	CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
+	CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
+	CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0),
+	CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0),
+	CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0),
+	CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
+	CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
+	CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0),
+	CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0),
+	CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0),
+	CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0),
+	CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
+	CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
+	DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+	DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+	DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+	DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
+	DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+	DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+	DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
+	DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
+	DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
+	DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"),
+	DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+	DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"),
+	DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+	DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+	DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
+	DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"),
+	DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"),
+	DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"),
+	DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"),
+	DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"),
+	DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"),
+	DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+	DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"),
+	DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
+	DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(149, 0, "mcuusart_clk_sel_out0"),
+	DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+	DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
+	DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+	DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+	DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"),
+	DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
+	DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+	DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"),
+	DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"),
+	DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
+	DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+	DEV_CLK(157, 104, "gpmc_fclk_sel_out0"),
+	DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"),
+	DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"),
+	DEV_CLK(157, 113, "osbclk0_div_out0"),
+	DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+	DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+	DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"),
+	DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+	DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"),
+	DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"),
+	DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"),
+	DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+	DEV_CLK(157, 127, "obsclk1_mux_out0"),
+	DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"),
+	DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"),
+	DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"),
+	DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"),
+	DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"),
+	DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"),
+	DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"),
+	DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"),
+	DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"),
+	DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"),
+	DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+	DEV_CLK(157, 144, "board_0_hfosc1_clk_out"),
+	DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(157, 146, "obsclk1_mux_out0"),
+	DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"),
+	DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"),
+	DEV_CLK(157, 153, "mcu_obsclk_div_out0"),
+	DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
+	DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
+	DEV_CLK(157, 172, "clkout_mux_out0"),
+	DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+	DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+	DEV_CLK(157, 175, "mcu_clkout_mux_out0"),
+	DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"),
+	DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+	DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+	DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"),
+	DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"),
+	DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+	DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+	DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"),
+	DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"),
+	DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+	DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+	DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"),
+	DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"),
+	DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+	DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+	DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"),
+	DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"),
+	DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+	DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"),
+	DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
+	DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(288, 15, "usb0_refclk_sel_out0"),
+	DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(288, 17, "board_0_hfosc1_clk_out"),
+	DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
+	DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(289, 15, "usb1_refclk_sel_out0"),
+	DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(289, 17, "board_0_hfosc1_clk_out"),
+	DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata j721e_clk_platdata = {
+	.clk_list = clk_list,
+	.clk_list_cnt = 156,
+	.soc_dev_clk_data = soc_dev_clk_data,
+	.soc_dev_clk_data_cnt = 171,
+};
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E specific device platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+	[0] = PSC(0, 0x00400000),
+	[1] = PSC(1, 0x42000000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+	[0] = PSC_PD(0, &soc_psc_list[0], NULL),
+	[1] = PSC_PD(14, &soc_psc_list[0], NULL),
+	[2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]),
+	[3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]),
+	[4] = PSC_PD(0, &soc_psc_list[1], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
+	[3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[5] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[6] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[7] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL),
+	[9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
+	[10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+	[11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[15] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[4], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(30, &soc_lpsc_list[0]),
+	PSC_DEV(61, &soc_lpsc_list[0]),
+	PSC_DEV(146, &soc_lpsc_list[1]),
+	PSC_DEV(90, &soc_lpsc_list[2]),
+	PSC_DEV(47, &soc_lpsc_list[3]),
+	PSC_DEV(288, &soc_lpsc_list[4]),
+	PSC_DEV(289, &soc_lpsc_list[5]),
+	PSC_DEV(92, &soc_lpsc_list[6]),
+	PSC_DEV(91, &soc_lpsc_list[7]),
+	PSC_DEV(4, &soc_lpsc_list[8]),
+	PSC_DEV(202, &soc_lpsc_list[9]),
+	PSC_DEV(203, &soc_lpsc_list[10]),
+	PSC_DEV(102, &soc_lpsc_list[11]),
+	PSC_DEV(103, &soc_lpsc_list[11]),
+	PSC_DEV(104, &soc_lpsc_list[11]),
+	PSC_DEV(154, &soc_lpsc_list[11]),
+	PSC_DEV(149, &soc_lpsc_list[11]),
+	PSC_DEV(113, &soc_lpsc_list[12]),
+	PSC_DEV(197, &soc_lpsc_list[12]),
+	PSC_DEV(103, &soc_lpsc_list[13]),
+	PSC_DEV(104, &soc_lpsc_list[14]),
+	PSC_DEV(102, &soc_lpsc_list[15]),
+};
+
+const struct ti_k3_pd_platdata j721e_pd_platdata = {
+	.psc = soc_psc_list,
+	.pd = soc_pd_list,
+	.lpsc = soc_lpsc_list,
+	.devs = soc_dev_list,
+	.num_psc = 2,
+	.num_pd = 5,
+	.num_lpsc = 16,
+	.num_devs = 22,
+};
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@ -180,6 +180,18 @@ void board_init_f(ulong dummy)
 	k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 			k3_mmc_stop_clock, k3_mmc_restart_clock);

+	/*
+	 * Force probe of clk_k3 driver here to ensure basic default clock
+	 * configuration is always done.
+	 */
+	if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+		ret = uclass_get_device_by_driver(UCLASS_CLK,
+						  DM_DRIVER_GET(ti_clk),
+						  &dev);
+		if (ret)
+			panic("Failed to initialize clk-k3!\n");
+	}
+
 	/* Prepare console output */
 	preloader_console_init();

--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@ -18,7 +18,7 @@
 #include <spl.h>
 #include <asm/arch/sys_proto.h>

-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void ti_secure_image_post_process(void **p_image, size_t *p_size)
 {
 	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR;
 */
 #define K3_SYSTEM_CONTROLLER_RPROC_ID	0

+#define COMMON_HEADER_ADDRESS		0x41cffb00
+#define BOARDCFG_ADDRESS		0x41c80000
+
+#define COMP_TYPE_SBL_DATA		0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX	0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX	0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE	0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE	0x000e
+
+struct extboot_comp {
+	u32 comp_type;
+	u32 boot_core;
+	u32 comp_opts;
+	u64 dest_addr;
+	u32 comp_size;
+};
+
+struct extboot_header {
+	u8 magic[8];
+	u32 num_comps;
+	struct extboot_comp comps[5];
+	u32 reserved;
+};
+
+struct bcfg_desc {
+	u16 type;
+	u16 offset;
+	u16 size;
+	u8 devgrp;
+	u8 reserved;
+} __packed;
+
+struct bcfg_header {
+	u8 num_elems;
+	u8 sw_rev;
+	struct bcfg_desc descs[4];
+	u16 reserved;
+} __packed;
+
 static bool sysfw_loaded;
 static void *sysfw_load_address;

@ -131,6 +171,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
 	const void *cfg_fragment_addr;
 	size_t cfg_fragment_size;
 	int ret;
+	u8 *buf;
+	struct extboot_header *common_header;
+	struct bcfg_header *bcfg_header;
+	struct extboot_comp *comp;
+	struct bcfg_desc *desc;
+	u32 addr;
+	bool copy_bcfg = false;

 	/* Find the node holding the images information */
 	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@ -159,11 +206,53 @@ static void k3_sysfw_configure_using_fit(void *fit,
 		      ret);

 	/* Apply power/clock (PM) specific configuration to SYSFW */
-	ret = board_ops->board_config_pm(ti_sci,
-					 (u64)(u32)cfg_fragment_addr,
-					 (u32)cfg_fragment_size);
-	if (ret)
-		panic("Failed to set board PM configuration (%d)\n", ret);
+	if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+		ret = board_ops->board_config_pm(ti_sci,
+						 (u64)(u32)cfg_fragment_addr,
+						 (u32)cfg_fragment_size);
+		if (ret)
+			panic("Failed to set board PM configuration (%d)\n", ret);
+	} else {
+		/* Initialize shared memory boardconfig buffer */
+		buf = (u8 *)COMMON_HEADER_ADDRESS;
+		common_header = (struct extboot_header *)buf;
+
+		/* Check if we have a struct populated by ROM in memory already */
+		if (strcmp((char *)common_header->magic, "EXTBOOT"))
+			copy_bcfg = true;
+
+		if (copy_bcfg) {
+			strcpy((char *)common_header->magic, "EXTBOOT");
+			common_header->num_comps = 1;
+
+			comp = &common_header->comps[0];
+
+			comp->comp_type = COMP_TYPE_SBL_DATA;
+			comp->boot_core = 0x10;
+			comp->comp_opts = 0;
+			addr = (u32)BOARDCFG_ADDRESS;
+			comp->dest_addr = addr;
+			comp->comp_size = sizeof(*bcfg_header);
+
+			bcfg_header = (struct bcfg_header *)addr;
+
+			bcfg_header->num_elems = 2;
+			bcfg_header->sw_rev = 0;
+
+			desc = &bcfg_header->descs[0];
+
+			desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+			desc->offset = sizeof(*bcfg_header);
+			desc->size = cfg_fragment_size;
+			comp->comp_size += desc->size;
+			desc->devgrp = 0;
+			desc->reserved = 0;
+			memcpy((u8 *)bcfg_header + desc->offset,
+			       cfg_fragment_addr, cfg_fragment_size);
+
+			bcfg_header->descs[1].offset = desc->offset + desc->size;
+		}
+	}

 	/* Extract resource management (RM) specific configuration from FIT */
 	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@ -172,6 +261,18 @@ static void k3_sysfw_configure_using_fit(void *fit,
 		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
 		      ret);

+	if (copy_bcfg) {
+		desc = &bcfg_header->descs[1];
+
+		desc->type = BOARD_CONFIG_RM_DESC_TYPE;
+		desc->size = cfg_fragment_size;
+		comp->comp_size += desc->size;
+		desc->devgrp = 0;
+		desc->reserved = 0;
+		memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+		       cfg_fragment_size);
+	}
+
 	/* Apply resource management (RM) configuration to SYSFW */
 	ret = board_ops->board_config_rm(ti_sci,
 					 (u64)(u32)cfg_fragment_addr,
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
 	return  result;
 }

-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	int result = 0;
 	void *image = *p_image;
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@ -103,7 +103,8 @@ __weak int board_fit_config_name_match(const char *name)
 #endif

 #if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
 		if (socfpga_vendor_authentication(p_image, p_size))
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@ -26,6 +26,7 @@
 #include <env.h>
 #include <init.h>
 #include <watchdog.h>
+#include <wdt.h>
 #include <malloc.h>
 #include <twl4030.h>
 #include <i2c.h>
@ -487,20 +488,20 @@ static unsigned long int twl_wd_time; /* last time of watchdog reset */
 static unsigned long int twl_i2c_lock;

 /*
- * Routine: hw_watchdog_reset
+ * Routine: rx51_watchdog_reset
 * Description: Reset timeout of twl4030 watchdog.
 */
-void hw_watchdog_reset(void)
+static int rx51_watchdog_reset(struct udevice *dev)
 {
 	u8 timeout = 0;

 	/* do not reset watchdog too often - max every 4s */
 	if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
-		return;
+		return 0;

 	/* localy lock twl4030 i2c bus */
 	if (test_and_set_bit(0, &twl_i2c_lock))
-		return;
+		return 0;

 	/* read actual watchdog timeout */
 	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
@ -517,8 +518,32 @@ void hw_watchdog_reset(void)

 	/* localy unlock twl4030 i2c bus */
 	test_and_clear_bit(0, &twl_i2c_lock);
+
+	return 0;
 }

+static int rx51_watchdog_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+	return 0;
+}
+
+static int rx51_watchdog_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct wdt_ops rx51_watchdog_ops = {
+	.start = rx51_watchdog_start,
+	.reset = rx51_watchdog_reset,
+};
+
+U_BOOT_DRIVER(rx51_watchdog) = {
+	.name = "rx51_watchdog",
+	.id = UCLASS_WDT,
+	.ops = &rx51_watchdog_ops,
+	.probe = rx51_watchdog_probe,
+};
+
 /*
 * TWL4030 keypad handler for cfb_console
 */
@ -722,3 +747,7 @@ U_BOOT_DRVINFOS(rx51_i2c) = {
 	{ "i2c_omap", &rx51_i2c[1] },
 	{ "i2c_omap", &rx51_i2c[2] },
 };
+
+U_BOOT_DRVINFOS(rx51_watchdog) = {
+	{ "rx51_watchdog" },
+};
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@ -960,7 +960,8 @@ int board_fit_config_name_match(const char *name)
 #endif

 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@ -896,7 +896,8 @@ int embedded_dtb_select(void)
 #endif

 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@ -1199,7 +1199,8 @@ static int board_bootmode_has_emmc(void)
 #endif

 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@ -152,3 +152,17 @@ int board_late_init(void)
 	return 0;
 }
 #endif
+
+#define CTRLMMR_USB0_PHY_CTRL	0x43004008
+#define CORE_VOLTAGE		0x80000000
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	u32 val;
+	/* Set USB PHY core voltage to 0.85V */
+	val = readl(CTRLMMR_USB0_PHY_CTRL);
+	val &= ~(CORE_VOLTAGE);
+	writel(val, CTRLMMR_USB0_PHY_CTRL);
+}
+#endif
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
 #endif

 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow:
 |    |         |         |   +-------------+     |                       |                       |
 |    |         |<--------|---| Start A72   |     |                       |                       |
 |    |         |         |   | and jump to |     |                       |                       |
-|    |         |         |   | next image  |     |                       |                       |
+|    |         |         |   | DM fw image |     |                       |                       |
 |    |         |         |   +-------------+     |                       |                       |
 |    |         |         |                       |     +-----------+     |                       |
 |    |         |---------|-----------------------|---->| Reset rls |     |                       |
 |    |         |         |                       |     +-----------+     |                       |
-|    |  DMSC   |         |                       |          :            |                       |
+|    |  TIFS   |         |                       |          :            |                       |
 |    |Services |         |                       |     +-----------+     |                       |
 |    |         |<--------|-----------------------|---->|*ATF/OPTEE*|     |                       |
 |    |         |         |                       |     +-----------+     |                       |
@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5

 4.2. A72:
 $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to DM firmware image> O=/tmp/a72

 Target Images
 --------------
@ -197,6 +197,9 @@ Image formats:
                | |     A72 OPTEE     | |
                | +-------------------+ |
                | |                   | |
+                | |      R5 DM FW     | |
+                | +-------------------+ |
+                | |                   | |
                | |      A72 SPL      | |
                | +-------------------+ |
                | |                   | |
--- a/cmd/clk.c
+++ b/cmd/clk.c
@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
 {
 	int i, is_last;
 	struct udevice *child;
-	struct clk *clkp;
+	struct clk *clkp, *parent;
 	u32 rate;

 	clkp = dev_get_clk_ptr(dev);
 	if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+		parent = clk_get_parent(clkp);
+		if (!IS_ERR(parent) && depth == -1)
+			return;
 		depth++;
 		rate = clk_get_rate(clkp);

@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
 	}

 	list_for_each_entry(child, &dev->child_head, sibling_node) {
+		if (child == dev)
+			continue;
+
 		is_last = list_is_last(&child->sibling_node, &dev->child_head);
 		show_clks(child, depth, (last_flag << 1) | is_last);
 	}
@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)

 int __weak soc_clk_dump(void)
 {
-	struct udevice *root;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;

-	root = dm_root();
-	if (root) {
-		printf(" Rate               Usecnt      Name\n");
-		printf("------------------------------------------\n");
-		show_clks(root, -1, 0);
-	}
+	ret = uclass_get(UCLASS_CLK, &uc);
+	if (ret)
+		return ret;
+
+	printf(" Rate               Usecnt      Name\n");
+	printf("------------------------------------------\n");
+
+	uclass_foreach_dev(dev, uc)
+		show_clks(dev, -1, 0);

 	return 0;
 }
@ -87,8 +98,56 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 	return ret;
 }

+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
+struct udevice *clk_lookup(const char *name)
+{
+	int i = 0;
+	struct udevice *dev;
+
+	do {
+		uclass_get_device(UCLASS_CLK, i++, &dev);
+		if (!strcmp(name, dev->name))
+			return dev;
+	} while (dev);
+
+	return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	struct clk *clk = NULL;
+	s32 freq;
+	struct udevice *dev;
+
+	freq = simple_strtoul(argv[2], NULL, 10);
+
+	dev = clk_lookup(argv[1]);
+
+	if (dev)
+		clk = dev_get_clk_ptr(dev);
+
+	if (!clk) {
+		printf("clock '%s' not found.\n", argv[1]);
+		return -EINVAL;
+	}
+
+	freq = clk_set_rate(clk, freq);
+	if (freq < 0) {
+		printf("set_rate failed: %d\n", freq);
+		return CMD_RET_FAILURE;
+	}
+
+	printf("set_rate returns %u\n", freq);
+	return 0;
+}
+#endif
+
 static struct cmd_tbl cmd_clk_sub[] = {
 	U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
+	U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
+#endif
 };

 static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@ -113,7 +172,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,

 #ifdef CONFIG_SYS_LONGHELP
 static char clk_help_text[] =
-	"dump - Print clock frequencies";
+	"dump - Print clock frequencies\n"
+	"setfreq [clk] [freq] - Set clock frequency";
 #endif

-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@ -7,4 +7,12 @@ config CMD_DDR3
 	   supports memory verification, memory comapre and ecc
 	   verification if supported.

+config CMD_PD
+	bool "command for verifying power domains"
+	depends on TI_POWER_DOMAIN
+	help
+	   Debug command for K3 power domains. For this to work, the
+	   K3 power domain driver must be enabled for the u-boot; by
+	   default it is only enabled for SPL.
+
 endmenu
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@ -5,4 +5,5 @@ obj- += dummy.o

 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
 endif
--- a/cmd/ti/pd.c
+++ b/cmd/ti/pd.c
@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <k3-dev.h>
+
+static const struct udevice_id ti_pd_of_match[] = {
+	{ .compatible = "ti,sci-pm-domain" },
+	{ /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+	struct udevice *dev;
+	int i = 0;
+
+	while (1) {
+		uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev);
+		if (!dev)
+			return NULL;
+
+		if (device_is_compatible(dev,
+					 ti_pd_of_match[0].compatible))
+			return  dev_get_priv(dev);
+	}
+
+	return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+	int i;
+	struct ti_lpsc *lpsc;
+	u8 state;
+	static const char * const lpsc_states[] = {
+		"swrstdis", "syncrst", "disable", "enable", "autosleep",
+		"autowake", "unknown",
+	};
+
+	for (i = 0; i < data->num_lpsc; i++) {
+		lpsc = &data->lpsc[i];
+		if (lpsc->pd != pd)
+			continue;
+		state = lpsc_get_state(lpsc);
+		if (state > ARRAY_SIZE(lpsc_states))
+			state = ARRAY_SIZE(lpsc_states) - 1;
+		printf("    LPSC%d: state=%s, usecount=%d\n",
+		       lpsc->id, lpsc_states[state], lpsc->usecount);
+	}
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+	int i;
+	struct ti_pd *pd;
+	u8 state;
+	static const char * const pd_states[] = {
+		"off", "on", "unknown"
+	};
+
+	for (i = 0; i < data->num_pd; i++) {
+		pd = &data->pd[i];
+		if (pd->psc != psc)
+			continue;
+		state = ti_pd_state(pd);
+		if (state > ARRAY_SIZE(pd_states))
+			state = ARRAY_SIZE(pd_states) - 1;
+		printf("  PD%d: state=%s, usecount=%d:\n",
+		       pd->id, pd_states[state], pd->usecount);
+		dump_lpsc(data, pd);
+	}
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+	int i;
+	struct ti_psc *psc;
+
+	for (i = 0; i < data->num_psc; i++) {
+		psc = &data->psc[i];
+		printf("PSC%d [%p]:\n", psc->id, psc->base);
+		dump_pd(data, psc);
+	}
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	struct ti_k3_pd_platdata *data;
+
+	data = ti_pd_find_data();
+	if (!data)
+		return CMD_RET_FAILURE;
+
+	dump_psc(data);
+
+	return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+{
+	u32 psc_id;
+	u32 lpsc_id;
+	int i;
+	struct ti_k3_pd_platdata *data;
+	struct ti_lpsc *lpsc;
+	int ret;
+
+	if (argc < 3)
+		return CMD_RET_FAILURE;
+
+	data = ti_pd_find_data();
+	if (!data)
+		return CMD_RET_FAILURE;
+
+	psc_id = simple_strtoul(argv[1], NULL, 10);
+	lpsc_id = simple_strtoul(argv[2], NULL, 10);
+
+	for (i = 0; i < data->num_lpsc; i++) {
+		lpsc = &data->lpsc[i];
+		if (lpsc->pd->psc->id != psc_id)
+			continue;
+		if (lpsc->id != lpsc_id)
+			continue;
+		printf("%s pd [PSC:%d,LPSC:%d]...\n",
+		       state == MDSTAT_STATE_ENABLE ? "Enabling" : "Disabling",
+		       psc_id, lpsc_id);
+		ret = ti_lpsc_transition(lpsc, state);
+		if (ret)
+			return CMD_RET_FAILURE;
+		else
+			return 0;
+	}
+
+	printf("No matching psc/lpsc found.\n");
+
+	return CMD_RET_FAILURE;
+}
+
+static int do_pd_enable(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	return do_pd_endis(argc, argv, MDSTAT_STATE_ENABLE);
+}
+
+static int do_pd_disable(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	return do_pd_endis(argc, argv, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct cmd_tbl cmd_pd[] = {
+	U_BOOT_CMD_MKENT(dump, 1, 0, do_pd_dump, "", ""),
+	U_BOOT_CMD_MKENT(enable, 3, 0, do_pd_enable, "", ""),
+	U_BOOT_CMD_MKENT(disable, 3, 0, do_pd_disable, "", ""),
+};
+
+static int ti_do_pd(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct cmd_tbl *c;
+
+	argc--;
+	argv++;
+
+	c = find_cmd_tbl(argv[0], cmd_pd, ARRAY_SIZE(cmd_pd));
+	if (c)
+		return c->cmd(cmdtp, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(pd, 4, 1, ti_do_pd,
+	   "TI power domain control",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+	   "dump                 - show power domain status\n"
+	   "enable [psc] [lpsc]  - enable power domain\n"
+	   "disable [psc] [lpsc] - disable power domain\n"
+#endif
+);
--- a/common/image-fit.c
+++ b/common/image-fit.c
@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,

 	/* perform any post-processing on the image data */
 	if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
-		board_fit_image_post_process(&buf, &size);
+		board_fit_image_post_process(fit, noffset, &buf, &size);

 	len = (ulong)size;

--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@ -320,7 +320,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 	}

 	if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS))
-		board_fit_image_post_process(&src, &length);
+		board_fit_image_post_process(fit, node, &src, &length);

 	load_ptr = map_sysmem(load_addr, length);
 	if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@ -5,6 +5,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SOC_K3_AM642=y
+CONFIG_K3_ATF_LOAD_ADDR=0x701a0000
 CONFIG_TARGET_AM642_A53_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
@ -22,6 +23,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
@ -29,12 +31,17 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
@ -101,3 +108,36 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_USB=y
+CONFIG_DFU=y
+CONFIG_DFU_OVER_USB=y
+# CONFIG_DFU_TFTP is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DFU_VIRT is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x20000
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
-CONFIG_SPL_TEXT_BASE=0x70020000
+CONFIG_SPL_TEXT_BASE=0x70000000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
@ -31,19 +32,30 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@ -52,8 +64,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk"
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
@ -64,6 +74,10 @@ CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
 CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_DM_I2C=y
@ -101,4 +115,22 @@ CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@ -110,7 +110,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_DM_RESET=y
@ -142,3 +142,13 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@ -102,7 +102,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65941=y
 CONFIG_DM_REGULATOR=y
@ -140,3 +140,11 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@ -67,4 +67,6 @@ CONFIG_CFB_CONSOLE=y
 CONFIG_CFB_CONSOLE_ANSI=y
 # CONFIG_VGA_AS_SINGLE_DEVICE is not set
 CONFIG_SPLASH_SCREEN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=31000
+CONFIG_WDT=y
 # CONFIG_GZIP is not set
--- a/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
+++ b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
@ -0,0 +1,32 @@
+Bindings for Texas Instruments System Control Interface (TI-SCI) Message
+Protocol for Device Manager(DM) to TI Foundational Security(TIFS)
+Firmware communication
+
+Required properties:
+--------------------
+- compatible: should be "ti,j721e-dm-sci"
+- mbox-names:
+	"rx" - Mailbox corresponding to receive path
+	"tx" - Mailbox corresponding to transmit path
+
+- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
+	  property should contain a phandle to the mailbox controller device
+	  node and an args specifier that will be the phandle to the intended
+	  sub-mailbox child node to be used for communication.
+
+- ti,host-id: Host ID to use for communication.
+
+Optional Properties:
+--------------------
+- ti,secure-host: If the host is defined as secure.
+
+Example:
+--------
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <3>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&mcu_secproxy 21>,
+			<&mcu_secproxy 23>;
+	};
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@ -241,6 +241,15 @@ static int clk_set_default_parents(struct udevice *dev, int stage)

 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
+		/*
+		 * If the clock provider is not ready yet, let it handle
+		 * the re-programming later.
+		 */
+		if (ret == -EPROBE_DEFER) {
+			ret = 0;
+			continue;
+		}
+
 		if (ret) {
 			debug("%s: could not get assigned clock %d for %s\n",
 			      __func__, index, dev_read_name(dev));
@ -309,6 +318,15 @@ static int clk_set_default_rates(struct udevice *dev, int stage)

 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
+		/*
+		 * If the clock provider is not ready yet, let it handle
+		 * the re-programming later.
+		 */
+		if (ret == -EPROBE_DEFER) {
+			ret = 0;
+			continue;
+		}
+
 		if (ret) {
 			dev_dbg(dev,
 				"could not get assigned clock %d (err = %d)\n",
@ -502,6 +520,8 @@ struct clk *clk_get_parent(struct clk *clk)
 		return NULL;

 	pdev = dev_get_parent(clk->dev);
+	if (!pdev)
+		return ERR_PTR(-ENODEV);
 	pclk = dev_get_clk_ptr(pdev);
 	if (!pclk)
 		return ERR_PTR(-ENODEV);
@ -548,6 +568,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
 	return ops->round_rate(clk, rate);
 }

+static void clk_clean_rate_cache(struct clk *clk)
+{
+	struct udevice *child_dev;
+	struct clk *clkp;
+
+	if (!clk)
+		return;
+
+	clk->rate = 0;
+
+	list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+		clkp = dev_get_clk_ptr(child_dev);
+		clk_clean_rate_cache(clkp);
+	}
+}
+
 ulong clk_set_rate(struct clk *clk, ulong rate)
 {
 	const struct clk_ops *ops;
@ -560,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
 	if (!ops->set_rate)
 		return -ENOSYS;

+	/* Clean up cached rates for us and all child clocks */
+	clk_clean_rate_cache(clk);
+
 	return ops->set_rate(clk, rate);
 }

--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@ -9,6 +9,9 @@
 #include <dm/device-internal.h>
 #include <linux/clk-provider.h>

+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
 	return to_clk_fixed_rate(clk->dev)->fixed_rate;
@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
 	clk->enable_count = 0;
 }

+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+	return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+	.get_rate = clk_fixed_rate_raw_get_rate,
+};
+
 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 {
 	clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@ -47,6 +59,32 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 	return 0;
 }

+#if CONFIG_IS_ENABLED(CLK_CCF)
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+				    ulong rate)
+{
+	struct clk *clk;
+	struct clk_fixed_rate *fixed;
+	int ret;
+
+	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+	if (!fixed)
+		return ERR_PTR(-ENOMEM);
+
+	fixed->fixed_rate = rate;
+
+	clk = &fixed->clk;
+
+	ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+	if (ret) {
+		kfree(fixed);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+#endif
+
 static const struct udevice_id clk_fixed_rate_match[] = {
 	{
 		.compatible = "fixed-clock",
@ -63,3 +101,10 @@ U_BOOT_DRIVER(fixed_clock) = {
 	.ops = &clk_fixed_rate_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+	.name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+	.id = UCLASS_CLK,
+	.ops = &clk_fixed_rate_raw_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@ -41,3 +41,27 @@ config CLK_TI_SCI
 	  This enables the clock driver support over TI System Control Interface
 	  available on some new TI's SoCs. If you wish to use clock resources
 	  managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+	bool "PLL clock support for K3 SoC family of devices"
+	depends on CLK && LIB_RATIONAL
+	help
+	  Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+	bool "PLL clock support for K3 SoC family of devices"
+	depends on CLK && LIB_RATIONAL && SPL
+	help
+	  Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+	bool "Clock support for K3 SoC family of devices"
+	depends on CLK
+	help
+	  Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+	bool "Clock support for K3 SoC family of devices"
+	depends on CLK && SPL
+	help
+	  Enables the clock translation layer from DT to device clocks.
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@ -11,3 +11,5 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
 obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
--- a/drivers/clk/ti/clk-k3-pll.c
+++ b/drivers/clk/ti/clk-k3-pll.c
@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+#include <linux/rational.h>
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG			0x08
+#define PLL_KICK0			0x10
+#define PLL_KICK1			0x14
+#define PLL_16FFT_CTRL			0x20
+#define PLL_16FFT_STAT			0x24
+#define PLL_16FFT_FREQ_CTRL0		0x30
+#define PLL_16FFT_FREQ_CTRL1		0x34
+#define PLL_16FFT_DIV_CTRL		0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN	BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN		BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN		BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCK		BIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK	0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK		0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS	24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN          BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE				0x68ef3490
+#define PLL_KICK1_VALUE				0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+	struct clk	clk;
+	void __iomem	*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 stat;
+	int i;
+
+	for (i = 0; i < 100000; i++) {
+		stat = readl(pll->reg + PLL_16FFT_STAT);
+		if (stat & PLL_16FFT_STAT_LOCK)
+			return 0;
+	}
+
+	printf("%s: pll (%s) failed to lock\n", __func__,
+	       clk->dev->name);
+
+	return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u64 current_freq;
+	u64 parent_freq = clk_get_parent_rate(clk);
+	u32 pllm;
+	u32 plld;
+	u32 pllfm;
+	u32 ctrl;
+
+	/* Check if we are in bypass */
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+		return parent_freq;
+
+	pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+	pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+	plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+		PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+	current_freq = parent_freq * pllm / plld;
+
+	if (pllfm) {
+		u64 tmp;
+
+		tmp = parent_freq * pllfm;
+		do_div(tmp, plld);
+		tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		current_freq += tmp;
+	}
+
+	return current_freq;
+}
+
+static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u64 current_freq;
+	u64 parent_freq = clk_get_parent_rate(clk);
+	int ret;
+	u32 ctrl;
+	unsigned long pllm;
+	u32 pllfm = 0;
+	unsigned long plld;
+	u32 rem;
+	int shift;
+
+	debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate);
+
+	if (ti_pll_clk_get_rate(clk) == rate)
+		return rate;
+
+	if (rate != parent_freq)
+		/*
+		 * Attempt with higher max multiplier value first to give
+		 * some space for fractional divider to kick in.
+		 */
+		for (shift = 8; shift >= 0; shift -= 8) {
+			rational_best_approximation(rate, parent_freq,
+				((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
+				PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
+			if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
+				break;
+		}
+
+	/* Put PLL to bypass mode */
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	if (rate == parent_freq) {
+		debug("%s: put %s to bypass\n", __func__, clk->dev->name);
+		return rate;
+	}
+
+	debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
+	      __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
+
+	/* Check if we need fractional config */
+	if (plld > 1) {
+		pllfm = pllm % plld;
+		pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		rem = pllfm % plld;
+		pllfm /= plld;
+		if (rem)
+			pllfm++;
+		pllm /= plld;
+		plld = 1;
+	}
+
+	if (pllfm)
+		ctrl |= PLL_16FFT_CTRL_DSM_EN;
+	else
+		ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+
+	writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
+	writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+	writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
+
+	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+	ctrl |= PLL_16FFT_CTRL_PLL_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	ret = ti_pll_wait_for_lock(clk);
+	if (ret)
+		return ret;
+
+	debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
+	      __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
+
+	current_freq = parent_freq * pllm / plld;
+
+	if (pllfm) {
+		u64 tmp;
+
+		tmp = parent_freq * pllfm;
+		do_div(tmp, plld);
+		tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		current_freq += tmp;
+	}
+
+	return current_freq;
+}
+
+static int ti_pll_clk_enable(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 ctrl;
+
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+	ctrl |= PLL_16FFT_CTRL_PLL_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	return ti_pll_wait_for_lock(clk);
+}
+
+static int ti_pll_clk_disable(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 ctrl;
+
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	return 0;
+}
+
+static const struct clk_ops ti_pll_clk_ops = {
+	.get_rate = ti_pll_clk_get_rate,
+	.set_rate = ti_pll_clk_set_rate,
+	.enable = ti_pll_clk_enable,
+	.disable = ti_pll_clk_disable,
+};
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+				void __iomem *reg)
+{
+	struct ti_pll_clk *pll;
+	int ret;
+	int i;
+	u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->reg = reg;
+
+	ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
+	if (ret) {
+		printf("%s: failed to register: %d\n", __func__, ret);
+		kfree(pll);
+		return ERR_PTR(ret);
+	}
+
+	/* Unlock the PLL registers */
+	writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
+	writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
+
+	/* Enable all HSDIV outputs */
+	cfg = readl(pll->reg + PLL_16FFT_CFG);
+	for (i = 0; i < 16; i++) {
+		hsdiv_presence_bit = BIT(16 + i);
+		hsdiv_ctrl_offs = 0x80 + (i * 4);
+		/* Enable HSDIV output if present */
+		if ((hsdiv_presence_bit & cfg) != 0UL) {
+			ctrl = readl(pll->reg + hsdiv_ctrl_offs);
+			ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
+			writel(ctrl, pll->reg + hsdiv_ctrl_offs);
+		}
+	}
+
+	return &pll->clk;
+}
+
+U_BOOT_DRIVER(ti_pll_clk) = {
+	.name = "ti-pll-clk",
+	.id = UCLASS_CLK,
+	.ops = &ti_pll_clk_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <soc.h>
+#include <clk-uclass.h>
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ	800000000
+#define PLL_MAX_FREQ	3200000000UL
+#define PLL_MAX_DIV	127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+	u16 dev_id;
+	u32 clk_id;
+	struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+	struct clk_map *map;
+	int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+			u32 dev_id, u32 clk_id)
+{
+	struct clk_map *map;
+
+	debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+	      clk, data, dev_id, clk_id);
+	if (!clk)
+		return;
+
+	map = data->map + data->size++;
+
+	map->dev_id = dev_id;
+	map->clk_id = clk_id;
+	map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+	{
+		.family = "J721E",
+		.data = &j721e_clk_platdata,
+	},
+	{
+		.family = "J7200",
+		.data = &j7200_clk_platdata,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+	struct ti_clk_data *data = dev_get_priv(dev);
+	struct clk *clk;
+	const char *name;
+	const struct clk_data *ti_clk_data;
+	int i, j;
+	const struct soc_attr *soc_match_data;
+	const struct ti_k3_clk_platdata *pdata;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+	if (!soc_match_data)
+		return -ENODEV;
+
+	pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+	data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+			    GFP_KERNEL);
+	data->size = 0;
+
+	for (i = 0; i < pdata->clk_list_cnt; i++) {
+		ti_clk_data = &pdata->clk_list[i];
+
+		switch (ti_clk_data->type) {
+		case CLK_TYPE_FIXED_RATE:
+			name = ti_clk_data->clk.fixed_rate.name;
+			clk = clk_register_fixed_rate(NULL,
+						      name,
+						      ti_clk_data->clk.fixed_rate.rate);
+			break;
+		case CLK_TYPE_DIV:
+			name = ti_clk_data->clk.div.name;
+			clk = clk_register_divider(NULL, name,
+						   ti_clk_data->clk.div.parent,
+						   ti_clk_data->clk.div.flags,
+						   map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE),
+						   ti_clk_data->clk.div.shift,
+						   ti_clk_data->clk.div.width,
+						   0);
+			break;
+		case CLK_TYPE_MUX:
+			name = ti_clk_data->clk.mux.name;
+			clk = clk_register_mux(NULL, name,
+					       ti_clk_data->clk.mux.parents,
+					       ti_clk_data->clk.mux.num_parents,
+					       ti_clk_data->clk.mux.flags,
+					       map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE),
+					       ti_clk_data->clk.mux.shift,
+					       ti_clk_data->clk.mux.width,
+					       0);
+			break;
+		case CLK_TYPE_PLL:
+			name = ti_clk_data->clk.pll.name;
+			clk = clk_register_ti_pll(name,
+						  ti_clk_data->clk.pll.parent,
+						  map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE));
+
+			if (!osc_freq)
+				osc_freq = clk_get_rate(clk_get_parent(clk));
+			break;
+		default:
+			name = NULL;
+			clk = NULL;
+			printf("WARNING: %s has encountered unknown clk type %d\n",
+			       __func__, ti_clk_data->type);
+		}
+
+		if (clk && ti_clk_data->default_freq)
+			clk_set_rate(clk, ti_clk_data->default_freq);
+
+		if (clk && name) {
+			for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) {
+				if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) {
+					clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id,
+						    pdata->soc_dev_clk_data[j].clk_id);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map)
+{
+	if (map->dev_id == dev_id && map->clk_id == clk_id)
+		return 0;
+	if (map->dev_id > dev_id ||
+	    (map->dev_id == dev_id && map->clk_id > clk_id))
+		return -1;
+	return 1;
+}
+
+static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num)
+{
+	int result;
+	int idx;
+
+	for (idx = 0; idx < num; idx++) {
+		result = _clk_cmp(dev_id, clk_id, &map[idx]);
+
+		if (result == 0)
+			return idx;
+	}
+
+	return -ENOENT;
+}
+
+static int ti_clk_of_xlate(struct clk *clk,
+			   struct ofnode_phandle_args *args)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	int idx;
+
+	debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk,
+	      args->args_count, args->args[0], args->args[1]);
+
+	if (args->args_count != 2) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (!data->size)
+		return -EPROBE_DEFER;
+
+	idx = bsearch(args->args[0], args->args[1], data->map, data->size);
+	if (idx < 0)
+		return idx;
+
+	clk->id = idx;
+
+	return 0;
+}
+
+static ulong ti_clk_get_rate(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_get_rate(clkp);
+}
+
+static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+	int div = 1;
+	ulong child_rate;
+	const struct clk_ops *ops;
+	ulong new_rate, rem;
+	ulong diff, new_diff;
+
+	/*
+	 * We must propagate rate change to parent if current clock type
+	 * does not allow setting it.
+	 */
+	while (clkp) {
+		ops = clkp->dev->driver->ops;
+		if (ops->set_rate)
+			break;
+
+		/*
+		 * Store child rate so we can calculate the clock rate
+		 * that must be passed to parent
+		 */
+		child_rate = clk_get_rate(clkp);
+		clkp = clk_get_parent(clkp);
+		if (clkp) {
+			debug("%s: propagating rate change to parent %s, rate=%u.\n",
+			      __func__, clkp->dev->name, (u32)rate / div);
+			div *= clk_get_rate(clkp) / child_rate;
+		}
+	}
+
+	if (!clkp)
+		return -ENOSYS;
+
+	child_rate = clk_get_rate(clkp);
+
+	new_rate = clk_set_rate(clkp, rate / div);
+
+	diff = abs(new_rate - rate / div);
+
+	debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__,
+	      clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff);
+
+	/*
+	 * If the new rate differs by 50% of the target,
+	 * modify parent. This handles typical cases where we have a hsdiv
+	 * following directly a PLL
+	 */
+
+	if (diff > rate / div / 2) {
+		ulong pll_tgt;
+		int pll_div = 0;
+
+		clk = clkp;
+
+		debug("%s: propagating rate change to parent, rate=%u.\n",
+		      __func__, (u32)rate / div);
+
+		clkp = clk_get_parent(clkp);
+
+		if (rate > osc_freq) {
+			if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) {
+				pll_tgt = rate;
+				pll_div = 1;
+			} else {
+				for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) {
+					pll_tgt = rate / div * pll_div;
+					if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ)
+						break;
+				}
+			}
+		} else {
+			pll_tgt = osc_freq;
+			pll_div = rate / div / osc_freq;
+		}
+
+		debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__,
+		      (u32)pll_tgt, (u32)rate, pll_div);
+
+		clk_set_rate(clkp, pll_tgt);
+
+		return clk_set_rate(clk, rate / div) * div;
+	}
+
+	/*
+	 * If the new rate differs by at least 5% of the target,
+	 * we must check for rounding error in a divider, so try
+	 * set rate with rate + (parent_freq % rate).
+	 */
+
+	if (diff > rate / div / 20) {
+		u64 parent_freq = clk_get_parent_rate(clkp);
+
+		rem = parent_freq % rate;
+		new_rate = clk_set_rate(clkp, (rate / div) + rem);
+		new_diff = abs(new_rate - rate / div);
+
+		if (new_diff > diff) {
+			new_rate = clk_set_rate(clkp, rate / div);
+		} else {
+			debug("%s: Using better rate %lu that gives diff %lu\n",
+			      __func__, new_rate, new_diff);
+		}
+	}
+
+	return new_rate;
+}
+
+static int ti_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+	struct clk *parentp = data->map[parent->id].clk;
+
+	return clk_set_parent(clkp, parentp);
+}
+
+static int ti_clk_enable(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_enable(clkp);
+}
+
+static int ti_clk_disable(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_disable(clkp);
+}
+
+static const struct udevice_id ti_clk_of_match[] = {
+	{ .compatible = "ti,k2g-sci-clk" },
+	{ /* sentinel */ },
+};
+
+static const struct clk_ops ti_clk_ops = {
+	.of_xlate = ti_clk_of_xlate,
+	.set_rate = ti_clk_set_rate,
+	.get_rate = ti_clk_get_rate,
+	.enable = ti_clk_enable,
+	.disable = ti_clk_disable,
+	.set_parent = ti_clk_set_parent,
+};
+
+U_BOOT_DRIVER(ti_clk) = {
+	.name = "ti-clk",
+	.id = UCLASS_CLK,
+	.of_match = ti_clk_of_match,
+	.probe = ti_clk_probe,
+	.priv_auto = sizeof(struct ti_clk_data),
+	.ops = &ti_clk_ops,
+};
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate)
 #endif

 	ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
-	if (ret)
+	if (ret) {
 		dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+		return ret;
+	}

-	return ret;
+	return rate;
 }

 static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
--- a/drivers/dma/ti/k3-udma-u-boot.c
+++ b/drivers/dma/ti/k3-udma-u-boot.c
@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT	(16)
+
+/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */
+#define UDMA_RFLOW_SRCTAG_NONE		0
+#define UDMA_RFLOW_SRCTAG_CFG_TAG	1
+#define UDMA_RFLOW_SRCTAG_FLOW_ID	2
+#define UDMA_RFLOW_SRCTAG_SRC_TAG	4
+
+#define UDMA_RFLOW_DSTTAG_NONE		0
+#define UDMA_RFLOW_DSTTAG_CFG_TAG	1
+#define UDMA_RFLOW_DSTTAG_FLOW_ID	2
+#define UDMA_RFLOW_DSTTAG_DST_TAG_LO	4
+#define UDMA_RFLOW_DSTTAG_DST_TAG_HI	5
+
+#define UDMA_RFLOW_RFC_DEFAULT	\
+	((UDMA_RFLOW_SRCTAG_NONE <<  UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \
+	 (UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \
+	 (UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT) | \
+	 (UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT))
+
+#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT	(16)
+
+/* TCHAN */
+static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg)
+{
+	if (!tchan)
+		return 0;
+	return udma_read(tchan->reg_chan, reg);
+}
+
+static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val)
+{
+	if (!tchan)
+		return;
+	udma_write(tchan->reg_chan, reg, val);
+}
+
+static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg,
+					  u32 mask, u32 val)
+{
+	if (!tchan)
+		return;
+	udma_update_bits(tchan->reg_chan, reg, mask, val);
+}
+
+/* RCHAN */
+static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg)
+{
+	if (!rchan)
+		return 0;
+	return udma_read(rchan->reg_chan, reg);
+}
+
+static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val)
+{
+	if (!rchan)
+		return;
+	udma_write(rchan->reg_chan, reg, val);
+}
+
+static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg,
+					  u32 mask, u32 val)
+{
+	if (!rchan)
+		return;
+	udma_update_bits(rchan->reg_chan, reg, mask, val);
+}
+
+/* RFLOW */
+static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg)
+{
+	if (!rflow)
+		return 0;
+	return udma_read(rflow->reg_rflow, reg);
+}
+
+static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val)
+{
+	if (!rflow)
+		return;
+	udma_write(rflow->reg_rflow, reg, val);
+}
+
+static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg,
+					  u32 mask, u32 val)
+{
+	if (!rflow)
+		return;
+	udma_update_bits(rflow->reg_rflow, reg, mask, val);
+}
+
+static void udma_alloc_tchan_raw(struct udma_chan *uc)
+{
+	u32 mode, fetch_size;
+
+	if (uc->config.pkt_mode)
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+	else
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+	udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+			       UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+	if (uc->config.dir == DMA_MEM_TO_MEM)
+		fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+	else
+		fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+						   uc->config.psd_size, 0) >> 2;
+
+	udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+			       UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+	udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG,
+			 k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring));
+}
+
+static void udma_alloc_rchan_raw(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+	int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring);
+	int rx_ring = k3_nav_ringacc_get_ring_id(uc->rflow->r_ring);
+	int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
+	u32 rx_einfo_present = 0, rx_psinfo_present = 0;
+	u32 mode, fetch_size, rxcq_num;
+
+	if (uc->config.pkt_mode)
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+	else
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+	udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG,
+			       UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+	if (uc->config.dir == DMA_MEM_TO_MEM) {
+		fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+		rxcq_num = tc_ring;
+	} else {
+		fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+						   uc->config.psd_size, 0) >> 2;
+		rxcq_num = rx_ring;
+	}
+
+	udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG,
+			       UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+	udma_rchan_write(uc->rchan, UDMA_RCHAN_RCQ_REG, rxcq_num);
+
+	if (uc->config.dir == DMA_MEM_TO_MEM)
+		return;
+
+	if (ud->match_data->type == DMA_TYPE_UDMA &&
+	    uc->rflow->id != uc->rchan->id &&
+	    uc->config.dir != DMA_MEM_TO_MEM)
+		udma_rchan_write(uc->rchan, UDMA_RCHAN_RFLOW_RNG_REG, uc->rflow->id |
+				 1 << UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT);
+
+	if (uc->config.needs_epib)
+		rx_einfo_present = UDMA_RFLOW_RFA_EINFO;
+
+	if (uc->config.psd_size)
+		rx_psinfo_present = UDMA_RFLOW_RFA_PSINFO;
+
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(A),
+			 rx_einfo_present | rx_psinfo_present | rxcq_num);
+
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(C), UDMA_RFLOW_RFC_DEFAULT);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(D),
+			 fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(E),
+			 fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(G), fd_ring);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(H),
+			 fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+}
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@ -48,6 +48,9 @@ enum udma_mmr {
 	MMR_BCHANRT,
 	MMR_RCHANRT,
 	MMR_TCHANRT,
+	MMR_RCHAN,
+	MMR_TCHAN,
+	MMR_RFLOW,
 	MMR_LAST,
 };

@ -56,9 +59,13 @@ static const char * const mmr_names[] = {
 	[MMR_BCHANRT] = "bchanrt",
 	[MMR_RCHANRT] = "rchanrt",
 	[MMR_TCHANRT] = "tchanrt",
+	[MMR_RCHAN] = "rchan",
+	[MMR_TCHAN] = "tchan",
+	[MMR_RFLOW] = "rflow",
 };

 struct udma_tchan {
+	void __iomem *reg_chan;
 	void __iomem *reg_rt;

 	int id;
@ -71,12 +78,14 @@ struct udma_tchan {
 #define udma_bchan udma_tchan

 struct udma_rflow {
+	void __iomem *reg_rflow;
 	int id;
 	struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
 	struct k3_nav_ring *r_ring; /* Receive ring */
 };

 struct udma_rchan {
+	void __iomem *reg_chan;
 	void __iomem *reg_rt;

 	int id;
@ -335,6 +344,8 @@ static inline char *udma_get_dir_text(enum dma_direction dir)
 	return "invalid";
 }

+#include "k3-udma-u-boot.c"
+
 static void udma_reset_uchan(struct udma_chan *uc)
 {
 	memset(&uc->config, 0, sizeof(uc->config));
@ -1014,10 +1025,20 @@ static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
 	req.txcq_qnum = tc_ring;

 	ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
-	if (ret)
+	if (ret) {
 		dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
+		return ret;
+	}

-	return ret;
+	/*
+	 * Above TI SCI call handles firewall configuration, cfg
+	 * register configuration still has to be done locally in
+	 * absence of RM services.
+	 */
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		udma_alloc_tchan_raw(uc);
+
+	return 0;
 }

 static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
@ -1114,11 +1135,21 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)

 	ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
 						     &flow_req);
-	if (ret)
+	if (ret) {
 		dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
 			uc->rchan->id, uc->rflow->id, ret);
+		return ret;
+	}

-	return ret;
+	/*
+	 * Above TI SCI call handles firewall configuration, cfg
+	 * register configuration still has to be done locally in
+	 * absence of RM services.
+	 */
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		udma_alloc_rchan_raw(uc);
+
+	return 0;
 }

 static int udma_alloc_chan_resources(struct udma_chan *uc)
@ -1751,6 +1782,7 @@ static int udma_probe(struct udevice *dev)
 		struct udma_tchan *tchan = &ud->tchans[i];

 		tchan->id = i;
+		tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
 		tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
 	}

@ -1758,6 +1790,7 @@ static int udma_probe(struct udevice *dev)
 		struct udma_rchan *rchan = &ud->rchans[i];

 		rchan->id = i;
+		rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
 		rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
 	}

@ -1765,6 +1798,7 @@ static int udma_probe(struct udevice *dev)
 		struct udma_rflow *rflow = &ud->rflows[i];

 		rflow->id = i;
+		rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
 	}

 	for (i = 0; i < ud->ch_count; i++) {
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@ -23,6 +23,7 @@
 #include <linux/soc/ti/ti_sci_protocol.h>

 #include "ti_sci.h"
+#include "ti_sci_static_data.h"

 /* List of all TI SCI devices active in system */
 static LIST_HEAD(ti_sci_list);
@ -1668,6 +1669,34 @@ fail:
 	return ret;
 }

+static int __maybe_unused
+ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle,
+				     u32 dev_id, u8 subtype,
+				     u16 *range_start, u16 *range_num)
+{
+	struct ti_sci_resource_static_data *data;
+	int i = 0;
+
+	while (1) {
+		data = &rm_static_data[i];
+
+		if (!data->dev_id)
+			return -EINVAL;
+
+		if (data->dev_id != dev_id || data->subtype != subtype) {
+			i++;
+			continue;
+		}
+
+		*range_start = data->range_start;
+		*range_num = data->range_num;
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 /**
 * ti_sci_cmd_get_resource_range - Get a range of resources assigned to host
 *				   that is same as ti sci interface host.
@ -3016,6 +3045,58 @@ static int ti_sci_probe(struct udevice *dev)
 	return ret;
 }

+/**
+ * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI
+ * @dev:	corresponding system controller interface device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static __maybe_unused int ti_sci_dm_probe(struct udevice *dev)
+{
+	struct ti_sci_rm_core_ops *rm_core_ops;
+	struct ti_sci_rm_udmap_ops *udmap_ops;
+	struct ti_sci_rm_ringacc_ops *rops;
+	struct ti_sci_rm_psil_ops *psilops;
+	struct ti_sci_ops *ops;
+	struct ti_sci_info *info;
+	int ret;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	info = dev_get_priv(dev);
+	info->desc = (void *)dev_get_driver_data(dev);
+
+	ret = ti_sci_of_to_info(dev, info);
+	if (ret) {
+		dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret);
+		return ret;
+	}
+
+	info->dev = dev;
+	info->seq = 0xA;
+
+	list_add_tail(&info->list, &ti_sci_list);
+
+	ops = &info->handle.ops;
+
+	rm_core_ops = &ops->rm_core_ops;
+	rm_core_ops->get_range = ti_sci_cmd_get_resource_range_static;
+
+	rops = &ops->rm_ring_ops;
+	rops->config = ti_sci_cmd_ring_config;
+
+	psilops = &ops->rm_psil_ops;
+	psilops->pair = ti_sci_cmd_rm_psil_pair;
+	psilops->unpair = ti_sci_cmd_rm_psil_unpair;
+
+	udmap_ops = &ops->rm_udmap_ops;
+	udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;
+	udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;
+	udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;
+
+	return ret;
+}
+
 /*
 * ti_sci_get_free_resource() - Get a free resource from TISCI resource.
 * @res:	Pointer to the TISCI resource
@ -3153,6 +3234,14 @@ static const struct ti_sci_desc ti_sci_pmmc_am654_desc = {
 	.max_msg_size = 60,
 };

+/* Description for J721e DM to DMSC communication */
+static const struct ti_sci_desc ti_sci_dm_j721e_desc = {
+	.default_host_id = 3,
+	.max_rx_timeout_ms = 10000,
+	.max_msgs = 20,
+	.max_msg_size = 60,
+};
+
 static const struct udevice_id ti_sci_ids[] = {
 	{
 		.compatible = "ti,k2g-sci",
@ -3165,6 +3254,14 @@ static const struct udevice_id ti_sci_ids[] = {
 	{ /* Sentinel */ },
 };

+static __maybe_unused const struct udevice_id ti_sci_dm_ids[] = {
+	{
+		.compatible = "ti,j721e-dm-sci",
+		.data = (ulong)&ti_sci_dm_j721e_desc
+	},
+	{ /* Sentinel */ },
+};
+
 U_BOOT_DRIVER(ti_sci) = {
 	.name = "ti_sci",
 	.id = UCLASS_FIRMWARE,
@ -3172,3 +3269,13 @@ U_BOOT_DRIVER(ti_sci) = {
 	.probe = ti_sci_probe,
 	.priv_auto	= sizeof(struct ti_sci_info),
 };
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+U_BOOT_DRIVER(ti_sci_dm) = {
+	.name = "ti_sci_dm",
+	.id = UCLASS_FIRMWARE,
+	.of_match = ti_sci_dm_ids,
+	.probe = ti_sci_dm_probe,
+	.priv_auto = sizeof(struct ti_sci_info),
+};
+#endif
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C)  2021 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ */
+
+#ifndef __TI_SCI_STATIC_DATA_H
+#define __TI_SCI_STATIC_DATA_H
+
+struct ti_sci_resource_static_data {
+	u32 dev_id;
+	u16 range_start;
+	u16 range_num;
+	u8 subtype;
+};
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+
+#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	/* Free rings */
+	{
+		.dev_id = 235,
+		.subtype = 1,
+		.range_start = 124,
+		.range_num = 32,
+	},
+	/* TX channels */
+	{
+		.dev_id = 236,
+		.subtype = 13,
+		.range_start = 6,
+		.range_num = 2,
+	},
+	/* RX channels */
+	{
+		.dev_id = 236,
+		.subtype = 10,
+		.range_start = 6,
+		.range_num = 2,
+	},
+	/* RX Free flows */
+	{
+		.dev_id = 236,
+		.subtype = 0,
+		.range_start = 60,
+		.range_num = 8,
+	},
+	{ },
+};
+#endif /* CONFIG_TARGET_J721E_R5_EVM */
+
+#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	/* Free rings */
+	{
+		.dev_id = 235,
+		.subtype = 1,
+		.range_start = 144,
+		.range_num = 32,
+	},
+	/* TX channels */
+	{
+		.dev_id = 236,
+		.subtype = 13,
+		.range_start = 7,
+		.range_num = 2,
+	},
+	/* RX channels */
+	{
+		.dev_id = 236,
+		.subtype = 10,
+		.range_start = 7,
+		.range_num = 2,
+	},
+	/* RX Free flows */
+	{
+		.dev_id = 236,
+		.subtype = 0,
+		.range_start = 60,
+		.range_num = 8,
+	},
+	{ },
+};
+#endif /* CONFIG_TARGET_J7200_R5_EVM */
+
+#else
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	{ },
+};
+#endif /* CONFIG_K3_DM_FW */
+#endif /* __TI_SCI_STATIC_DATA_H */
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@ -409,7 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev)
 	return 0;
 }

-static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 };
+static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 };

 static const struct k3_sec_proxy_desc am654_desc = {
 	.thread_count = 90,
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
 	help
 	  Generic power domain implementation for TI devices implementing the
 	  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+	bool "Enable the TI K3 Power domain driver"
+	depends on POWER_DOMAIN && ARCH_K3
+	help
+	  Generic power domain implementation for TI K3 devices.
+
 endmenu
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <power-domain-uclass.h>
+#include <soc.h>
+#include <k3-dev.h>
+#include <linux/iopoll.h>
+
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_PDSTAT		0x200
+#define PSC_PDCTL		0x300
+#define PSC_MDSTAT		0x800
+#define PSC_MDCTL		0xa00
+
+#define PDCTL_STATE_MASK		0x1
+#define PDCTL_STATE_OFF			0x0
+#define PDCTL_STATE_ON			0x1
+
+#define MDSTAT_STATE_MASK		0x3f
+#define MDSTAT_BUSY_MASK		0x30
+#define MDSTAT_STATE_SWRSTDISABLE	0x0
+#define MDSTAT_STATE_ENABLE		0x3
+
+#define LPSC_TIMEOUT		1000
+#define PD_TIMEOUT		1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+	u32 val;
+
+	val = readl(psc->base + reg);
+	debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+	return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+	debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+	writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+	return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+	psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+	return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+	psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+	{
+		.family = "J721E",
+		.data = &j721e_pd_platdata,
+	},
+	{
+		.family = "J7200",
+		.data = &j7200_pd_platdata,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+	struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+	const struct soc_attr *soc_match_data;
+	const struct ti_k3_pd_platdata *pdata;
+
+	printf("%s(dev=%p)\n", __func__, dev);
+
+	if (!data)
+		return -ENOMEM;
+
+	soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+	if (!soc_match_data)
+		return -ENODEV;
+
+	pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+	data->psc = pdata->psc;
+	data->pd = pdata->pd;
+	data->lpsc = pdata->lpsc;
+	data->devs = pdata->devs;
+	data->num_psc = pdata->num_psc;
+	data->num_pd = pdata->num_pd;
+	data->num_lpsc = pdata->num_lpsc;
+	data->num_devs = pdata->num_devs;
+
+	return 0;
+}
+
+static int ti_pd_wait(struct ti_pd *pd)
+{
+	u32 ptstat;
+	int ret;
+
+	ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
+				 !(ptstat & BIT(pd->id)), PD_TIMEOUT);
+
+	if (ret)
+		printf("%s: psc%d, pd%d failed to transition.\n", __func__,
+		       pd->psc->id, pd->id);
+
+	return ret;
+}
+
+static void ti_pd_transition(struct ti_pd *pd)
+{
+	psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+}
+
+u8 ti_pd_state(struct ti_pd *pd)
+{
+	return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK;
+}
+
+static int ti_pd_get(struct ti_pd *pd)
+{
+	u32 pdctl;
+	int ret;
+
+	pd->usecount++;
+
+	if (pd->usecount > 1)
+		return 0;
+
+	if (pd->depend) {
+		ret = ti_pd_get(pd->depend);
+		if (ret)
+			return ret;
+		ti_pd_transition(pd->depend);
+		ret = ti_pd_wait(pd->depend);
+		if (ret)
+			return ret;
+	}
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+
+	if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON)
+		return 0;
+
+	debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+	pdctl &= ~PDCTL_STATE_MASK;
+	pdctl |= PDCTL_STATE_ON;
+
+	pd_write(pdctl, pd, PSC_PDCTL);
+
+	return 0;
+}
+
+static int ti_pd_put(struct ti_pd *pd)
+{
+	u32 pdctl;
+	int ret;
+
+	pd->usecount--;
+
+	if (pd->usecount > 0)
+		return 0;
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+	if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF)
+		return 0;
+
+	pdctl &= ~PDCTL_STATE_MASK;
+	pdctl |= PDCTL_STATE_OFF;
+
+	debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+	pd_write(pdctl, pd, PSC_PDCTL);
+
+	if (pd->depend) {
+		ti_pd_transition(pd);
+		ret = ti_pd_wait(pd);
+		if (ret)
+			return ret;
+
+		ret = ti_pd_put(pd->depend);
+		if (ret)
+			return ret;
+		ti_pd_transition(pd->depend);
+		ret = ti_pd_wait(pd->depend);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ti_lpsc_wait(struct ti_lpsc *lpsc)
+{
+	u32 mdstat;
+	int ret;
+
+	ret = readl_poll_timeout(lpsc->psc->base + PSC_MDSTAT + lpsc->id * 4,
+				 mdstat,
+				 !(mdstat & MDSTAT_BUSY_MASK), LPSC_TIMEOUT);
+
+	if (ret)
+		printf("%s: module %d failed to transition.\n", __func__,
+		       lpsc->id);
+
+	return ret;
+}
+
+u8 lpsc_get_state(struct ti_lpsc *lpsc)
+{
+	return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK;
+}
+
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
+{
+	struct ti_pd *psc_pd;
+	int ret;
+	u32 mdctl;
+
+	psc_pd = lpsc->pd;
+
+	if (state == MDSTAT_STATE_ENABLE) {
+		lpsc->usecount++;
+		if (lpsc->usecount > 1)
+			return 0;
+	} else {
+		lpsc->usecount--;
+		if (lpsc->usecount >= 1)
+			return 0;
+	}
+
+	debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__,
+	      lpsc->psc->id, lpsc->id, state);
+
+	if (lpsc->depend)
+		ti_lpsc_transition(lpsc->depend, state);
+
+	mdctl = lpsc_read(lpsc, PSC_MDCTL);
+	if ((mdctl & MDSTAT_STATE_MASK) == state)
+		return 0;
+
+	if (state == MDSTAT_STATE_ENABLE)
+		ti_pd_get(psc_pd);
+	else
+		ti_pd_put(psc_pd);
+
+	mdctl &= ~MDSTAT_STATE_MASK;
+	mdctl |= state;
+
+	lpsc_write(mdctl, lpsc, PSC_MDCTL);
+
+	ti_pd_transition(psc_pd);
+	ret = ti_pd_wait(psc_pd);
+	if (ret)
+		return ret;
+
+	return ti_lpsc_wait(lpsc);
+}
+
+static int ti_power_domain_transition(struct power_domain *pd, u8 state)
+{
+	struct ti_lpsc *lpsc = pd->priv;
+
+	return ti_lpsc_transition(lpsc, state);
+}
+
+static int ti_power_domain_on(struct power_domain *pd)
+{
+	debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+	return ti_power_domain_transition(pd, MDSTAT_STATE_ENABLE);
+}
+
+static int ti_power_domain_off(struct power_domain *pd)
+{
+	debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+	return ti_power_domain_transition(pd, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct ti_lpsc *lpsc_lookup(struct ti_k3_pd_platdata *data, int id)
+{
+	int idx;
+
+	for (idx = 0; idx < data->num_devs; idx++)
+		if (data->devs[idx].id == id)
+			return data->devs[idx].lpsc;
+
+	return NULL;
+}
+
+static int ti_power_domain_of_xlate(struct power_domain *pd,
+				    struct ofnode_phandle_args *args)
+{
+	struct ti_k3_pd_platdata *data = dev_get_priv(pd->dev);
+	struct ti_lpsc *lpsc;
+
+	debug("%s(power_domain=%p, id=%d)\n", __func__, pd, args->args[0]);
+
+	if (args->args_count < 1) {
+		printf("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	lpsc = lpsc_lookup(data, args->args[0]);
+	if (!lpsc) {
+		printf("%s: invalid dev-id: %d\n", __func__, args->args[0]);
+		return -ENOENT;
+	}
+
+	pd->id = lpsc->id;
+	pd->priv = lpsc;
+
+	return 0;
+}
+
+static int ti_power_domain_request(struct power_domain *pd)
+{
+	return 0;
+}
+
+static int ti_power_domain_free(struct power_domain *pd)
+{
+	return 0;
+}
+
+static const struct udevice_id ti_power_domain_of_match[] = {
+	{ .compatible = "ti,sci-pm-domain" },
+	{ /* sentinel */ }
+};
+
+static struct power_domain_ops ti_power_domain_ops = {
+	.on = ti_power_domain_on,
+	.off = ti_power_domain_off,
+	.of_xlate = ti_power_domain_of_xlate,
+	.request = ti_power_domain_request,
+	.rfree = ti_power_domain_free,
+};
+
+U_BOOT_DRIVER(ti_pm_domains) = {
+	.name = "ti-pm-domains",
+	.id = UCLASS_POWER_DOMAIN,
+	.of_match = ti_power_domain_of_match,
+	.probe = ti_power_domain_probe,
+	.priv_auto = sizeof(struct ti_k3_pd_platdata),
+	.ops = &ti_power_domain_ops,
+};
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@ -804,20 +804,28 @@ static int k3_r5f_probe(struct udevice *dev)
 		return ret;
 	}

-	ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
-					       &r_state, &core->in_use);
-	if (ret)
-		return ret;
+	/*
+	 * The PM functionality is not supported by the firmware during
+	 * SPL execution with the separated DM firmware image. The following
+	 * piece of code is not compiled in that case.
+	 */
+	if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+		ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci,
+						       core->tsp.dev_id,
+						       &r_state, &core->in_use);
+		if (ret)
+			return ret;

-	if (core->in_use) {
-		dev_info(dev, "Core %d is already in use. No rproc commands work\n",
-			 core->tsp.proc_id);
-		return 0;
+		if (core->in_use) {
+			dev_info(dev, "Core %d is already in use. No rproc commands work\n",
+				 core->tsp.proc_id);
+			return 0;
+		}
+
+		/* Make sure Local reset is asserted. Redundant? */
+		reset_assert(&core->reset);
 	}

-	/* Make sure Local reset is asserted. Redundant? */
-	reset_assert(&core->reset);
-
 	ret = k3_r5f_rproc_configure(core);
 	if (ret) {
 		dev_err(dev, "rproc configure failed %d\n", ret);
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@ -188,4 +188,11 @@ config RTC_ABX80X
 	  families of ultra-low-power  battery- and capacitor-backed real-time
 	  clock chips.

+config RTC_DAVINCI
+	bool "Enable TI OMAP RTC driver"
+	depends on ARCH_DAVINCI || ARCH_OMAP2PLUS
+	help
+	  Say "yes" here to support the on chip real time clock
+	  present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx.
+
 endmenu
--- a/drivers/rtc/davinci.c
+++ b/drivers/rtc/davinci.c
@ -2,81 +2,443 @@
 /*
 * (C) Copyright 2011 DENX Software Engineering GmbH
 * Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
 */
 #include <common.h>
 #include <command.h>
+#include <dm.h>
+#include <clk.h>
 #include <log.h>
 #include <rtc.h>
 #include <asm/io.h>
-#include <asm/davinci_rtc.h>
+#include <dm/device_compat.h>
 #include <linux/delay.h>

-int rtc_get(struct rtc_time *tmp)
-{
-	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
-	unsigned long sec, min, hour, mday, wday, mon_cent, year;
-	unsigned long status;
+/* RTC registers */
+#define OMAP_RTC_SECONDS_REG		0x00
+#define OMAP_RTC_MINUTES_REG		0x04
+#define OMAP_RTC_HOURS_REG		0x08
+#define OMAP_RTC_DAYS_REG		0x0C
+#define OMAP_RTC_MONTHS_REG		0x10
+#define OMAP_RTC_YEARS_REG		0x14
+#define OMAP_RTC_WEEKS_REG		0x18

-	status = readl(&rtc->status);
-	if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) {
+#define OMAP_RTC_CTRL_REG		0x40
+#define OMAP_RTC_STATUS_REG		0x44
+#define OMAP_RTC_INTERRUPTS_REG		0x48
+
+#define OMAP_RTC_OSC_REG		0x54
+
+#define OMAP_RTC_SCRATCH0_REG		0x60
+#define OMAP_RTC_SCRATCH1_REG		0x64
+#define OMAP_RTC_SCRATCH2_REG		0x68
+
+#define OMAP_RTC_KICK0_REG		0x6c
+#define OMAP_RTC_KICK1_REG		0x70
+
+#define OMAP_RTC_PMIC_REG		0x98
+
+/* OMAP_RTC_CTRL_REG bit fields: */
+#define OMAP_RTC_CTRL_SPLIT		BIT(7)
+#define OMAP_RTC_CTRL_DISABLE		BIT(6)
+#define OMAP_RTC_CTRL_SET_32_COUNTER	BIT(5)
+#define OMAP_RTC_CTRL_TEST		BIT(4)
+#define OMAP_RTC_CTRL_MODE_12_24	BIT(3)
+#define OMAP_RTC_CTRL_AUTO_COMP		BIT(2)
+#define OMAP_RTC_CTRL_ROUND_30S		BIT(1)
+#define OMAP_RTC_CTRL_STOP		BIT(0)
+
+/* OMAP_RTC_STATUS_REG bit fields */
+#define OMAP_RTC_STATUS_POWER_UP	BIT(7)
+#define OMAP_RTC_STATUS_ALARM2		BIT(7)
+#define OMAP_RTC_STATUS_ALARM		BIT(6)
+#define OMAP_RTC_STATUS_1D_EVENT	BIT(5)
+#define OMAP_RTC_STATUS_1H_EVENT	BIT(4)
+#define OMAP_RTC_STATUS_1M_EVENT	BIT(3)
+#define OMAP_RTC_STATUS_1S_EVENT	BIT(2)
+#define OMAP_RTC_STATUS_RUN		BIT(1)
+#define OMAP_RTC_STATUS_BUSY		BIT(0)
+
+/* OMAP_RTC_OSC_REG bit fields */
+#define OMAP_RTC_OSC_32KCLK_EN		BIT(6)
+#define OMAP_RTC_OSC_SEL_32KCLK_SRC	BIT(3)
+#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE	BIT(4)
+
+/* OMAP_RTC_KICKER values */
+#define	OMAP_RTC_KICK0_VALUE		0x83e70b13
+#define	OMAP_RTC_KICK1_VALUE		0x95a4f1e0
+
+struct omap_rtc_device_type {
+	bool has_32kclk_en;
+	bool has_irqwakeen;
+	bool has_pmic_mode;
+	bool has_power_up_reset;
+};
+
+struct omap_rtc_priv {
+	fdt_addr_t base;
+	u8 max_reg;
+	struct udevice *dev;
+	struct clk clk;
+	bool has_ext_clk;
+	const struct omap_rtc_device_type *type;
+};
+
+static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg)
+{
+	return readb(priv->base + reg);
+}
+
+static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg)
+{
+	return readl(priv->base + reg);
+}
+
+static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg,
+				   u8 val)
+{
+	writeb(val, priv->base + reg);
+}
+
+static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg,
+				   u32 val)
+{
+	writel(val, priv->base + reg);
+}
+
+static inline void omap_rtc_unlock(struct omap_rtc_priv *priv)
+{
+	omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE);
+	omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE);
+}
+
+static inline void omap_rtc_lock(struct omap_rtc_priv *priv)
+{
+	omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0);
+	omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0);
+}
+
+static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv)
+{
+	int count;
+	u8 status;
+
+	status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+	if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) {
 		printf("RTC doesn't run\n");
 		return -1;
 	}
-	if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY)
-		udelay(20);

-	sec	= readl(&rtc->second);
-	min	= readl(&rtc->minutes);
-	hour	= readl(&rtc->hours);
-	mday	= readl(&rtc->day);
-	wday	= readl(&rtc->dotw);
-	mon_cent = readl(&rtc->month);
-	year	= readl(&rtc->year);
+	/* BUSY may stay active for 1/32768 second (~30 usec) */
+	for (count = 0; count < 50; count++) {
+		if (!(status & OMAP_RTC_STATUS_BUSY))
+			break;

-	debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
+		udelay(1);
+		status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+	}
+
+	/* now we have ~15 usec to read/write various registers */
+	return 0;
+}
+
+static int omap_rtc_reset(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+
+	/* run RTC counter */
+	omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01);
+	return 0;
+}
+
+static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = omap_rtc_wait_not_busy(priv);
+	if (ret)
+		return ret;
+
+	omap_rtc_unlock(priv);
+	omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100));
+	omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon));
+	omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday));
+	omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday));
+	omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour));
+	omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min));
+	omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec));
+	omap_rtc_lock(priv);
+
+	dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
+		tm->tm_min, tm->tm_sec);
+
+	return 0;
+}
+
+static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	unsigned long sec, min, hour, mday, wday, mon_cent, year;
+	int ret;
+
+	ret = omap_rtc_wait_not_busy(priv);
+	if (ret)
+		return ret;
+
+	sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG);
+	min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG);
+	hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG);
+	mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG);
+	wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG);
+	mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG);
+	year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG);
+
+	dev_dbg(dev,
+		"Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
 		"hr: %02lx min: %02lx sec: %02lx\n",
 		year, mon_cent, mday, wday,
 		hour, min, sec);

-	tmp->tm_sec  = bcd2bin(sec  & 0x7F);
-	tmp->tm_min  = bcd2bin(min  & 0x7F);
-	tmp->tm_hour = bcd2bin(hour & 0x3F);
-	tmp->tm_mday = bcd2bin(mday & 0x3F);
-	tmp->tm_mon  = bcd2bin(mon_cent & 0x1F);
-	tmp->tm_year = bcd2bin(year) + 2000;
-	tmp->tm_wday = bcd2bin(wday & 0x07);
-	tmp->tm_yday = 0;
-	tmp->tm_isdst = 0;
+	tm->tm_sec  = bcd2bin(sec  & 0x7F);
+	tm->tm_min  = bcd2bin(min  & 0x7F);
+	tm->tm_hour = bcd2bin(hour & 0x3F);
+	tm->tm_mday = bcd2bin(mday & 0x3F);
+	tm->tm_mon  = bcd2bin(mon_cent & 0x1F);
+	tm->tm_year = bcd2bin(year) + 2000;
+	tm->tm_wday = bcd2bin(wday & 0x07);
+	tm->tm_yday = 0;
+	tm->tm_isdst = 0;

-	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+	dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
+		tm->tm_min, tm->tm_sec);

 	return 0;
 }

-int rtc_set(struct rtc_time *tmp)
+static int omap_rtc_scratch_read(struct udevice *dev, uint offset,
+				 u8 *buffer, uint len)
 {
-	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	u32 *val = (u32 *)buffer;
+	unsigned int reg;
+	int i;

-	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-	writel(bin2bcd(tmp->tm_year % 100), &rtc->year);
-	writel(bin2bcd(tmp->tm_mon), &rtc->month);
+	if (len & 3)
+		return -EFAULT;
+
+	for (i = 0; i < len / 4; i++) {
+		reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
+		if (reg >= OMAP_RTC_KICK0_REG)
+			return -EFAULT;
+
+		val[i] = omap_rtc_readl(priv, reg);
+	}

-	writel(bin2bcd(tmp->tm_wday), &rtc->dotw);
-	writel(bin2bcd(tmp->tm_mday), &rtc->day);
-	writel(bin2bcd(tmp->tm_hour), &rtc->hours);
-	writel(bin2bcd(tmp->tm_min), &rtc->minutes);
-	writel(bin2bcd(tmp->tm_sec), &rtc->second);
 	return 0;
 }

-void rtc_reset(void)
+static int omap_rtc_scratch_write(struct udevice *dev, uint offset,
+				  const u8 *buffer, uint len)
 {
-	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	u32 *val = (u32 *)buffer;
+	unsigned int reg;
+	int i;

-	/* run RTC counter */
-	writel(0x01, &rtc->ctrl);
+	if (len & 3)
+		return -EFAULT;
+
+	omap_rtc_unlock(priv);
+	for (i = 0; i < len / 4; i++) {
+		reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
+		if (reg >= OMAP_RTC_KICK0_REG)
+			return -EFAULT;
+
+		omap_rtc_writel(priv, reg, val[i]);
+	}
+	omap_rtc_lock(priv);
+
+	return 0;
 }
+
+static int omap_rtc_remove(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	u8 reg;
+
+	if (priv->clk.dev)
+		clk_disable(&priv->clk);
+
+	omap_rtc_unlock(priv);
+
+	/* leave rtc running, but disable irqs */
+	omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0);
+
+	if (priv->has_ext_clk) {
+		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+		reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
+		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
+	}
+
+	omap_rtc_lock(priv);
+	return 0;
+}
+
+static int omap_rtc_probe(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	struct rtc_time tm;
+	u8 reg, mask, new_ctrl;
+
+	priv->dev = dev;
+	priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev);
+	priv->max_reg = OMAP_RTC_PMIC_REG;
+
+	if (!clk_get_by_name(dev, "ext-clk", &priv->clk))
+		priv->has_ext_clk = true;
+	else
+		clk_get_by_name(dev, "int-clk", &priv->clk);
+
+	if (priv->clk.dev)
+		clk_enable(&priv->clk);
+	else
+		dev_warn(dev, "missing clock\n");
+
+	omap_rtc_unlock(priv);
+
+	/*
+	 * disable interrupts
+	 *
+	 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
+	 */
+	omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0);
+
+	if (priv->type->has_32kclk_en) {
+		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG,
+				reg | OMAP_RTC_OSC_32KCLK_EN);
+	}
+
+	/* clear old status */
+	reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+
+	mask = OMAP_RTC_STATUS_ALARM;
+
+	if (priv->type->has_pmic_mode)
+		mask |= OMAP_RTC_STATUS_ALARM2;
+
+	if (priv->type->has_power_up_reset) {
+		mask |= OMAP_RTC_STATUS_POWER_UP;
+		if (reg & OMAP_RTC_STATUS_POWER_UP)
+			dev_info(dev, "RTC power up reset detected\n");
+	}
+
+	if (reg & mask)
+		omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask);
+
+	/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
+	reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG);
+	if (reg & OMAP_RTC_CTRL_STOP)
+		dev_info(dev, "already running\n");
+
+	/* force to 24 hour mode */
+	new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
+	new_ctrl |= OMAP_RTC_CTRL_STOP;
+
+	/*
+	 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
+	 *
+	 *  - Device wake-up capability setting should come through chip
+	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
+	 *    flag in the platform device if the board is wired right for
+	 *    being woken up by RTC alarm. For OMAP-L138, this capability
+	 *    is built into the SoC by the "Deep Sleep" capability.
+	 *
+	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
+	 *    rather than nPWRON_RESET, should forcibly enable split
+	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
+	 *    is write-only, and always reads as zero...)
+	 */
+
+	if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
+		dev_info(dev, "split power mode\n");
+
+	if (reg != new_ctrl)
+		omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl);
+
+	/*
+	 * If we have the external clock then switch to it so we can keep
+	 * ticking across suspend.
+	 */
+	if (priv->has_ext_clk) {
+		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+		reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
+		reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
+		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
+	}
+
+	omap_rtc_lock(priv);
+
+	if (omap_rtc_get(dev, &tm)) {
+		dev_err(dev, "failed to get datetime\n");
+	} else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 &&
+		   tm.tm_wday == 0) {
+		tm.tm_wday = 6;
+		omap_rtc_set(dev, &tm);
+	}
+
+	return 0;
+}
+
+static int omap_rtc_of_to_plat(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "invalid address\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "base=%pa\n", &priv->base);
+	return 0;
+}
+
+static const struct rtc_ops omap_rtc_ops = {
+	.get = omap_rtc_get,
+	.set = omap_rtc_set,
+	.reset = omap_rtc_reset,
+	.read = omap_rtc_scratch_read,
+	.write = omap_rtc_scratch_write,
+};
+
+static const struct omap_rtc_device_type omap_rtc_am3352_type = {
+	.has_32kclk_en	= true,
+	.has_irqwakeen	= true,
+	.has_pmic_mode	= true,
+};
+
+static const struct omap_rtc_device_type omap_rtc_da830_type = {
+	.has_32kclk_en	= false,
+	.has_irqwakeen	= false,
+	.has_pmic_mode	= false,
+};
+
+static const struct udevice_id omap_rtc_ids[] = {
+	{.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type},
+	{.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type }
+};
+
+U_BOOT_DRIVER(omap_rtc) = {
+	.name = "omap_rtc",
+	.id = UCLASS_RTC,
+	.of_match = omap_rtc_ids,
+	.ops = &omap_rtc_ops,
+	.of_to_plat = omap_rtc_of_to_plat,
+	.probe = omap_rtc_probe,
+	.remove = omap_rtc_remove,
+	.priv_auto = sizeof(struct omap_rtc_priv),
+};
--- a/drivers/soc/ti/k3-navss-ringacc-u-boot.c
+++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator
+ * Manager (RA) subsystem driver
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+struct k3_nav_ring_cfg_regs {
+	u32	resv_64[16];
+	u32	ba_lo;		/* Ring Base Address Lo Register */
+	u32	ba_hi;		/* Ring Base Address Hi Register */
+	u32	size;		/* Ring Size Register */
+	u32	event;		/* Ring Event Register */
+	u32	orderid;	/* Ring OrderID Register */
+};
+
+#define KNAV_RINGACC_CFG_REGS_STEP	0x100
+
+#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK	GENMASK(15, 0)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK		GENMASK(31, 30)
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT		(30)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK		GENMASK(26, 24)
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT		(24)
+
+static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
+{
+	writel(0, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode)
+{
+	u32 val;
+
+	val = readl(&ring->cfg->size);
+	val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
+	val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
+	writel(val, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring)
+{
+	writel(0, &ring->cfg->ba_hi);
+	writel(0, &ring->cfg->ba_lo);
+	writel(0, &ring->cfg->size);
+}
+
+static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring)
+{
+	u32 val;
+
+	writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
+	writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
+
+	val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT |
+	      ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT |
+	      ring->size;
+	writel(val, &ring->cfg->size);
+}
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@ -124,6 +124,7 @@ struct k3_nav_ring_state {
 /**
 * struct k3_nav_ring - RA Ring descriptor
 *
+ * @cfg - Ring configuration registers
 * @rt - Ring control/status registers
 * @fifos - Ring queues registers
 * @ring_mem_dma - Ring buffer dma address
@ -138,6 +139,7 @@ struct k3_nav_ring_state {
 * @use_count - Use count for shared rings
 */
 struct k3_nav_ring {
+	struct k3_nav_ring_cfg_regs __iomem *cfg;
 	struct k3_nav_ring_rt_regs __iomem *rt;
 	struct k3_nav_ring_fifo_regs __iomem *fifos;
 	dma_addr_t	ring_mem_dma;
@ -195,6 +197,8 @@ struct k3_nav_ringacc {
 	bool dual_ring;
 };

+#include "k3-navss-ringacc-u-boot.c"
+
 static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
 {
 	return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
@ -330,6 +334,9 @@ static void k3_ringacc_ring_reset_sci(struct k3_nav_ring *ring)
 	struct k3_nav_ringacc *ringacc = ring->parent;
 	int ret;

+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		return k3_ringacc_ring_reset_raw(ring);
+
 	ret = ringacc->tisci_ring_ops->config(
 			ringacc->tisci,
 			TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
@ -362,6 +369,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_nav_ring *ring,
 	struct k3_nav_ringacc *ringacc = ring->parent;
 	int ret;

+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		return k3_ringacc_ring_reconfig_qmode_raw(ring, mode);
+
 	ret = ringacc->tisci_ring_ops->config(
 			ringacc->tisci,
 			TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
@ -442,6 +452,9 @@ static void k3_ringacc_ring_free_sci(struct k3_nav_ring *ring)
 	struct k3_nav_ringacc *ringacc = ring->parent;
 	int ret;

+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		return k3_ringacc_ring_free_raw(ring);
+
 	ret = ringacc->tisci_ring_ops->config(
 			ringacc->tisci,
 			TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
@ -531,11 +544,21 @@ static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring)
 			ring->mode,
 			ring->elm_size,
 			0);
-	if (ret)
+	if (ret) {
 		dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
 			ret, ring_idx);
+		return ret;
+	}

-	return ret;
+	/*
+	 * Above TI SCI call handles firewall configuration, cfg
+	 * register configuration still has to be done locally in
+	 * absence of RM services.
+	 */
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		k3_nav_ringacc_ring_cfg_raw(ring);
+
+	return 0;
 }

 static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg)
@ -951,13 +974,18 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)

 static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc)
 {
-	void __iomem *base_rt;
+	void __iomem *base_cfg, *base_rt;
 	int ret, i;

 	ret = k3_nav_ringacc_probe_dt(ringacc);
 	if (ret)
 		return ret;

+	base_cfg = dev_remap_addr_name(dev, "cfg");
+	pr_debug("cfg %p\n", base_cfg);
+	if (!base_cfg)
+		return -EINVAL;
+
 	base_rt = (uint32_t *)devfdt_get_addr_name(dev, "rt");
 	pr_debug("rt %p\n", base_rt);
 	if (IS_ERR(base_rt))
@ -975,6 +1003,8 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
 		return -ENOMEM;

 	for (i = 0; i < ringacc->num_rings; i++) {
+		ringacc->rings[i].cfg = base_cfg +
+					KNAV_RINGACC_CFG_REGS_STEP * i;
 		ringacc->rings[i].rt = base_rt +
 				       KNAV_RINGACC_RT_REGS_STEP * i;
 		ringacc->rings[i].parent = ringacc;
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@ -12,6 +12,8 @@
 #include <linux/sizes.h>
 #include <config_distro_bootcmd.h>
 #include <environment/ti/mmc.h>
+#include <asm/arch/am64_hardware.h>
+#include <environment/ti/k3_dfu.h>

 /* DDR Configuration */
 #define CONFIG_SYS_SDRAM_BASE1		0x880000000
@ -43,7 +45,7 @@
 * location filled in by the boot ROM that we want to read out without any
 * interference from the C context.
 */
-#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+#define CONFIG_SPL_BSS_START_ADDR	(TI_SRAM_SCRATCH_BOARD_EEPROM_START -\
 					 CONFIG_SPL_BSS_MAX_SIZE)
 /* Set the stack right below the SPL BSS section */
 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_BSS_START_ADDR
@ -94,16 +96,25 @@
 		"${bootdir}/${name_fit}\0"				\
 	"partitions=" PARTS_DEFAULT

+#define EXTRA_ENV_DFUARGS \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_OSPI
+
 /* Incorporate settings into the U-Boot environment */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	DEFAULT_LINUX_BOOT_ENV						\
 	DEFAULT_MMC_TI_ARGS						\
 	EXTRA_ENV_AM642_BOARD_SETTINGS					\
-	EXTRA_ENV_AM642_BOARD_SETTINGS_MMC
+	EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
+	EXTRA_ENV_DFUARGS

 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>

+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+
 /* MMC ENV related defines */
 #ifdef CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@ -85,9 +85,6 @@

 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

-/* Watchdog support */
-#define CONFIG_HW_WATCHDOG
-
 /*
 * Framebuffer
 */
--- a/include/image.h
+++ b/include/image.h
@ -1581,11 +1581,14 @@ int board_fit_config_name_match(const char *name);
 * into the FIT creation (i.e. the binary blobs would have been pre-processed
 * before being added to the FIT image).
 *
+ * @fit: pointer to fit image
+ * @node: offset of image node
 * @image: pointer to the image start pointer
 * @size: pointer to the image size
 * @return no return value (failure should be handled internally)
 */
-void board_fit_image_post_process(void **p_image, size_t *p_size);
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size);

 #define FDT_ERROR	((ulong)(-1))

--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com
+ *      Tero Kristo <t-kristo@ti.com>
+ */
+
+#ifndef __K3_CLK_H__
+#define __K3_CLK_H__
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/types.h>
+#include <stdint.h>
+
+struct dev_clk {
+	int dev_id;
+	int clk_id;
+	const char *clk_name;
+};
+
+#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id,		\
+					.clk_id = _clk_id, .clk_name = _clk_name, }
+
+#define CLK_TYPE_MUX		0x01
+#define CLK_TYPE_DIV		0x02
+#define CLK_TYPE_PLL		0x03
+#define CLK_TYPE_HFOSC		0x04
+#define CLK_TYPE_POSTDIV	0x05
+#define CLK_TYPE_MUX_PLLCTRL	0x06
+#define CLK_TYPE_FIXED_RATE	0x07
+
+struct pll_data {
+	u32 reg;
+	const char *name;
+	const char *parent;
+	u32 flags;
+};
+
+struct mux_data {
+	u32 reg;
+	const char *name;
+	const char * const *parents;
+	int num_parents;
+	u32 flags;
+	int shift;
+	int width;
+};
+
+struct div_data {
+	u32 reg;
+	const char *name;
+	const char *parent;
+	u32 flags;
+	int shift;
+	int width;
+};
+
+struct hfosc_data {
+	const char *name;
+	u32 flags;
+};
+
+struct fixed_rate_data {
+	const char *name;
+	u64 rate;
+	u32 flags;
+};
+
+struct postdiv_data {
+	const char *name;
+	const char *parent;
+	int width;
+	u32 flags;
+};
+
+struct mux_pllctrl_data {
+	u32 reg;
+	const char *name;
+	const char * const *parents;
+	int num_parents;
+	u32 flags;
+};
+
+struct clk_data {
+	int type;
+	u32 default_freq;
+	union {
+		struct pll_data pll;
+		struct mux_data mux;
+		struct div_data div;
+		struct hfosc_data hfosc;
+		struct postdiv_data postdiv;
+		struct mux_pllctrl_data mux_pllctrl;
+		struct fixed_rate_data fixed_rate;
+	} clk;
+};
+
+#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \
+	{								\
+		.type = CLK_TYPE_MUX,					\
+		.clk.mux = { .name = _name, .parents = _parents,	\
+		.reg = _reg,						\
+		.num_parents = _num_parents, .shift = _shift,		\
+		.width = _width, .flags = _flags }			\
+	}
+
+#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags)	\
+	{							\
+		.type = CLK_TYPE_DIV,				\
+		.clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \
+	}
+
+#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \
+	{							\
+		.type = CLK_TYPE_DIV,				\
+		.default_freq = _freq,				\
+		.clk.div = {					\
+			.name = _name, .parent = _parent,	\
+			.reg = _reg, .shift = _shift,		\
+			.width = _width, .flags = _flags }	\
+	}
+
+#define CLK_PLL(_name, _parent, _reg,  _flags)	\
+	{					\
+		.type = CLK_TYPE_PLL,		\
+		.clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
+	}
+
+#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq)	\
+	{							\
+		.type = CLK_TYPE_PLL,				\
+		.default_freq = _freq,				\
+		.clk.pll = { .name = _name, .parent = _parent,	\
+				.reg = _reg, .flags = _flags }	\
+	}
+
+#define CLK_HFOSC(_name, _flags)		\
+	{					\
+		.type = CLK_TYPE_HFOSC,		\
+		.clk.hfosc = { .name = _name, .flags = _flags } \
+	}
+
+#define CLK_FIXED_RATE(_name, _rate, _flags)		\
+	{						\
+		.type = CLK_TYPE_FIXED_RATE,		\
+		.clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \
+	}
+
+#define CLK_POSTDIV(_name, _parent, _width, _flags)	\
+	{						\
+		.type = CLK_TYPE_POSTDIV,		\
+		.clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
+	}
+
+#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags)	\
+	{								\
+		.type = CLK_TYPE_MUX,					\
+		.clk.mux_pllctrl = { .name = _name, .parents = _parents,\
+		.num_parents = _num_parents, .flags = _flags }		\
+	}
+
+struct ti_k3_clk_platdata {
+	const struct clk_data *clk_list;
+	int clk_list_cnt;
+	const struct dev_clk *soc_dev_clk_data;
+	int soc_dev_clk_data_cnt;
+};
+
+extern const struct ti_k3_clk_platdata j721e_clk_platdata;
+extern const struct ti_k3_clk_platdata j7200_clk_platdata;
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+				void __iomem *reg);
+
+#endif /* __K3_CLK_H__ */
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments K3 Device Platform Data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __K3_DEV_H__
+#define __K3_DEV_H__
+
+#include <asm/io.h>
+#include <linux/types.h>
+#include <stdint.h>
+
+#define LPSC_MODULE_EXISTS      BIT(0)
+#define LPSC_NO_CLOCK_GATING    BIT(1)
+#define LPSC_DEPENDS            BIT(2)
+#define LPSC_HAS_RESET_ISO      BIT(3)
+#define LPSC_HAS_LOCAL_RESET    BIT(4)
+#define LPSC_NO_MODULE_RESET    BIT(5)
+
+#define PSC_PD_EXISTS           BIT(0)
+#define PSC_PD_ALWAYSON         BIT(1)
+#define PSC_PD_DEPENDS          BIT(2)
+
+#define MDSTAT_STATE_MASK		0x3f
+#define MDSTAT_BUSY_MASK		0x30
+#define MDSTAT_STATE_SWRSTDISABLE	0x0
+#define MDSTAT_STATE_ENABLE		0x3
+
+struct ti_psc {
+	int id;
+	void __iomem *base;
+};
+
+struct ti_pd;
+
+struct ti_pd {
+	int id;
+	int usecount;
+	struct ti_psc *psc;
+	struct ti_pd *depend;
+};
+
+struct ti_lpsc;
+
+struct ti_lpsc {
+	int id;
+	int usecount;
+	struct ti_psc *psc;
+	struct ti_pd *pd;
+	struct ti_lpsc *depend;
+};
+
+struct ti_dev {
+	struct ti_lpsc *lpsc;
+	int id;
+};
+
+/**
+ * struct ti_k3_pd_platdata - pm domain controller information structure
+ */
+struct ti_k3_pd_platdata {
+	struct ti_psc *psc;
+	struct ti_pd *pd;
+	struct ti_lpsc *lpsc;
+	struct ti_dev *devs;
+	int num_psc;
+	int num_pd;
+	int num_lpsc;
+	int num_devs;
+};
+
+#define PSC(_id, _base) { .id = _id, .base = (void *)_base, }
+#define PSC_PD(_id, _psc, _depend) { .id = _id, .psc = _psc, .depend = _depend }
+#define PSC_LPSC(_id, _psc, _pd, _depend) { .id = _id, .psc = _psc, .pd = _pd, .depend = _depend }
+#define PSC_DEV(_id, _lpsc) { .id = _id, .lpsc = _lpsc }
+
+extern const struct ti_k3_pd_platdata j721e_pd_platdata;
+extern const struct ti_k3_pd_platdata j7200_pd_platdata;
+
+u8 ti_pd_state(struct ti_pd *pd);
+u8 lpsc_get_state(struct ti_lpsc *lpsc);
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state);
+
+#endif
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags);

+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+				    ulong rate);
+
 const char *clk_hw_get_name(const struct clk *hw);
 ulong clk_generic_get_rate(struct clk *clk);

--- a/include/linux/rational.h
+++ b/include/linux/rational.h
@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com>
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+	unsigned long given_numerator, unsigned long given_denominator,
+	unsigned long max_numerator, unsigned long max_denominator,
+	unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
--- a/lib/Kconfig
+++ b/lib/Kconfig
@ -674,6 +674,13 @@ config GENERATE_SMBIOS_TABLE
 	  See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
 	  the devicetree.

+config LIB_RATIONAL
+	bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+	bool "enable continued fraction calculation routines for SPL"
+	depends on SPL
+
 endmenu

 config ASN1_COMPILER
--- a/lib/Makefile
+++ b/lib/Makefile
@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/
 obj-$(CONFIG_$(SPL_)LZMA) += lzma/
 obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o

+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
 obj-$(CONFIG_LIBAVB) += libavb/

 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
--- a/lib/rational.c
+++ b/lib/rational.c
@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com>
+ * Copyright (C) 2019 Trent Piepho <tpiepho@gmail.com>
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include <linux/rational.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 10000,
+ *		(1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+	unsigned long given_numerator, unsigned long given_denominator,
+	unsigned long max_numerator, unsigned long max_denominator,
+	unsigned long *best_numerator, unsigned long *best_denominator)
+{
+	/* n/d is the starting rational, which is continually
+	 * decreased each iteration using the Euclidean algorithm.
+	 *
+	 * dp is the value of d from the prior iteration.
+	 *
+	 * n2/d2, n1/d1, and n0/d0 are our successively more accurate
+	 * approximations of the rational.  They are, respectively,
+	 * the current, previous, and two prior iterations of it.
+	 *
+	 * a is current term of the continued fraction.
+	 */
+	unsigned long n, d, n0, d0, n1, d1, n2, d2;
+	n = given_numerator;
+	d = given_denominator;
+	n0 = d1 = 0;
+	n1 = d0 = 1;
+
+	for (;;) {
+		unsigned long dp, a;
+
+		if (d == 0)
+			break;
+		/* Find next term in continued fraction, 'a', via
+		 * Euclidean algorithm.
+		 */
+		dp = d;
+		a = n / d;
+		d = n % d;
+		n = dp;
+
+		/* Calculate the current rational approximation (aka
+		 * convergent), n2/d2, using the term just found and
+		 * the two prior approximations.
+		 */
+		n2 = n0 + a * n1;
+		d2 = d0 + a * d1;
+
+		/* If the current convergent exceeds the maxes, then
+		 * return either the previous convergent or the
+		 * largest semi-convergent, the final term of which is
+		 * found below as 't'.
+		 */
+		if ((n2 > max_numerator) || (d2 > max_denominator)) {
+			unsigned long t = min((max_numerator - n0) / n1,
+					      (max_denominator - d0) / d1);
+
+			/* This tests if the semi-convergent is closer
+			 * than the previous convergent.
+			 */
+			if (2u * t > a || (2u * t == a && d0 * dp > d1 * d)) {
+				n1 = n0 + t * n1;
+				d1 = d0 + t * d1;
+			}
+			break;
+		}
+		n0 = n1;
+		n1 = n2;
+		d0 = d1;
+		d1 = d2;
+	}
+	*best_numerator = n1;
+	*best_denominator = d1;
+}
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@ -5,7 +5,7 @@
 # ATF, OPTEE, SPL and multiple device trees (given on the command line).
 # Inspired from board/sunxi/mksunxi_fit_atf.sh
 #
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+# usage: $0 <atf_load_addr> <dt_name> [<dt_name> [<dt_name] ...]

 [ -z "$ATF" ] && ATF="bl31.bin"

@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then
 	TEE=/dev/null
 fi

+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+	echo "WARNING DM file $DM NOT found, resulting might be non-functional" >&2
+	DM=/dev/null
+fi
+
 if [ ! -z "$IS_HS" ]; then
 	HS_APPEND=_HS
 fi
@ -40,8 +47,8 @@ cat << __HEADER_EOF
 			arch = "arm64";
 			compression = "none";
 			os = "arm-trusted-firmware";
-			load = <0x70000000>;
-			entry = <0x70000000>;
+			load = <$1>;
+			entry = <$1>;
 		};
 		tee {
 			description = "OPTEE";
@ -53,6 +60,16 @@ cat << __HEADER_EOF
 			load = <0x9e800000>;
 			entry = <0x9e800000>;
 		};
+		dm {
+			description = "DM binary";
+			data = /incbin/("$DM");
+			type = "firmware";
+			arch = "arm32";
+			compression = "none";
+			os = "DM";
+			load = <0xa0000000>;
+			entry = <0xa0000000>;
+		};
 		spl {
 			description = "SPL (64-bit)";
 			data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@ -65,6 +82,9 @@ cat << __HEADER_EOF
 		};
 __HEADER_EOF

+# shift through ATF load address in the command line arguments
+shift
+
 for dtname in $*
 do
 	cat << __FDT_IMAGE_EOF
@ -91,7 +111,7 @@ do
 		$(basename $dtname) {
 			description = "$(basename $dtname .dtb)";
 			firmware = "atf";
-			loadables = "tee", "spl";
+			loadables = "tee", "dm", "spl";
 			fdt = "$(basename $dtname)";
 		};
 __CONF_SECTION_EOF