Commit graph

1955 commits

Author SHA1 Message Date
Tom Rini
6115f1c4fe Convert CONFIG_NAND_OMAP_ECCSCHEME to Kconfig
The values of CONFIG_NAND_OMAP_ECCSCHEME map to the enum in
include/linux/mtd/omap_gpmc.h for valid ECC schemes.  Make which one we
will use be a choice statement, enumerating the ones which we have
implemented.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:24 -04:00
Tom Rini
53f06134ed Convert CONFIG_NAND_FSL_ELBC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_FSL_ELBC
   CONFIG_NAND_FSL_IFC

Note that a number of PowerPC platforms had previously enabled
CONFIG_NAND_FSL_ELBC without CONFIG_MTD_RAW_NAND, and now they no longer
enable the option, reducing the size of a few functions.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:24 -04:00
Tom Rini
b2e25afabd Convert CONFIG_SYS_NAND_MAX_CHIPS to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_MAX_CHIPS

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:24 -04:00
Tom Rini
1cefed1e39 nand.h: Cleanup linux/mtd/rawnand.h usage
We only include <linux/mtd/rawnand.h> in <nand.h> for the forward
declaration of struct nand_chip, so do that directly.  Then, include
<linux/mtd/rawnand.h> where required directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
c0ad62c5f7 Convert CONFIG_SYS_NAND_ONFI_DETECTION to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_ONFI_DETECTION

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
4884d829d7 Convert CONFIG_SYS_NAND_5_ADDR_CYCLE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_5_ADDR_CYCLE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
9d9f59dd0a Convert CONFIG_SYS_NAND_BAD_BLOCK_POS to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_BAD_BLOCK_POS

In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS
as those are the only valid values.  Use LARGE as the default as no
in-tree boards use SMALL, but it is possible.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
606c377849 nand_spl_simple: Drop CONFIG_SYS_NAND_4_ADDR_CYCLE support
This code is unused, drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
8db73ec106 Convert CONFIG_SYS_NAND_PAGE_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_PAGE_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
a0de075392 Convert CONFIG_SPL_NAND_LOAD et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_NAND_LOAD
   CONFIG_SYS_NAND_BLOCK_SIZE
   CONFIG_SYS_NAND_PAGE_SIZE
   CONFIG_SYS_NAND_OOBSIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
ccdc7cfbdc Convert CONFIG_NAND_LPC32XX_MLC to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_LPC32XX_MLC

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:15:14 -04:00
Tom Rini
8ba59608dc arm: Remove zmx25 board and ARCH_MX25
This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last ARCH_MX25 platform, remove those
references as well.

Cc: Matthias Weisser <weisserm@arcor.de>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01 21:08:18 -04:00
Tom Rini
14b38cb0c2 arm: Remove flea3 board
This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last mx35 platform, remove that support as
well.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2021-10-01 12:08:19 -04:00
Tom Rini
8bef036836 Xilinx changes for v2022.01-rc1
zynq:
 - Enable capsule update for qspi and mmc
 - Update zed DT qspi compatible string
 
 zynqmp:
 - Add missing modeboot for EMMC
 - Add missing nand DT properties
 - List all eeproms for SC on vck190
 - Add vck190 SC psu_init
 
 clk:
 - Handle only GATE type clock for Versal
 
 watchdog:
 - Update versal driver to handle system reset
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Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.01-rc1

zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string

zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init

clk:
- Handle only GATE type clock for Versal

watchdog:
- Update versal driver to handle system reset
2021-09-30 11:29:41 -04:00
Wolfgang Denk
0cf207ec01 WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 09:08:16 -04:00
Wolfgang Denk
0a50b3c97b WS cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-30 08:08:56 -04:00
Wolfgang Denk
c72231d272 WS cleanup: remove excessive empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Tom Rini
ba17871884 Merge branch '2021-09-25-TI-platform-updates' into next
- Start moving some TI board docs to rST
- Assorted TI-specific Kconfig migrations and namespace cleanups.  This
  also allows for some code cleanups.
2021-09-28 19:18:56 -04:00
Patrice Chotard
b8919eaa68 mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interface
nand_dt_init() is still using fdtdec_xx() interface.
If OF_LIVE flag is enabled, dt property can't be get anymore.
Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue.

For doing this, node parameter type must be ofnode.

First idea was to convert "node" parameter to ofnode type inside
nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode()
is not bijective, in case OF_LIVE flag is enabled, it performs an assert().

So, this leads to update nand_chip struct flash_node field from int to
ofnode and to update all nand_dt_init() callers.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28 12:03:21 -04:00
Marek Vasut
b81ce79df0 mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0
Before e2e95e5e25 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus mode 0. Now the mode is always updated,
which causes breakage. It seems most SF which are used as boot media
operate in bus mode 0, so switch that as the default.

This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx
ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble
with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked
as those might need mode 3.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Cc: Andreas Biessmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
2021-09-28 12:03:21 -04:00
Patrick Delaunay
a4f2d83414 mtd: spi: nor: force mtd name to "nor%d"
Force the mtd name of spi-nor to "nor" + the driver sequence number:
"nor0", "nor1"... beginning after the existing nor devices.

This patch is coherent with existing "nand" and "spi-nand"
mtd device names.

When CFI MTD NOR device are supported, the spi-nor index is chosen after
the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS.

When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config
is replaced by to cfi_flash_num_flash_banks in the include file
mtd/cfi_flash.h.

This generic name "nor%d" can be use to identify the mtd spi-nor device
without knowing the real device name or the DT path of the device,
used with API get_mtd_device_nm() and is used in mtdparts command.

This patch also avoids issue when the same NOR device is present 2 times,
for example on STM32MP15F-EV1:

STM32MP> mtd list
SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \
total 64 MiB

List of MTD devices:
* nand0
  - type: NAND flash
  - block size: 0x40000 bytes
  - min I/O: 0x1000 bytes
  - OOB size: 224 bytes
  - OOB available: 118 bytes
  - ECC strength: 8 bits
  - ECC step size: 512 bytes
  - bitflip threshold: 6 bits
  - 0x000000000000-0x000040000000 : "nand0"
* mx66l51235l
  - device: mx66l51235l@0
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@0
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"
* mx66l51235l
  - device: mx66l51235l@1
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@1
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"

The same mtd name "mx66l51235l" identify the 2 instances
mx66l51235l@0 and mx66l51235l@1.

This patch fixes a ST32CubeProgrammer / stm32prog command issue
with nor0 target on STM32MP157C-EV1 board introduced by
commit b7f060565e ("mtd: spi-nor: allow registering multiple MTDs when
DM is enabled").

Fixes: b7f060565e ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
[trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-28 12:03:20 -04:00
Patrice Chotard
a70c3f9fb8 mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interface
nand_dt_init() is still using fdtdec_xx() interface.
If OF_LIVE flag is enabled, dt property can't be get anymore.
Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue.

For doing this, node parameter type must be ofnode.

First idea was to convert "node" parameter to ofnode type inside
nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode()
is not bijective, in case OF_LIVE flag is enabled, it performs an assert().

So, this leads to update nand_chip struct flash_node field from int to
ofnode and to update all nand_dt_init() callers.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28 06:34:45 +02:00
Tom Rini
c8c934b910 ti: keystone: Clean up or migrate some NAND related options.
The COFNIG_KEYSTONE_RBL_NAND option is always enabled for the driver on
keystone platforms, but not older davinci platforms.  Use def_bool for
the symbol. For CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE, it's only used within
the driver and derived from another symbol, so remove CONFIG from the
name.  Finally, CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE is a bit more fixed.
For now, use the value directly.  Long term, as part of DM'ifying NAND,
this should come from the device tree.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27 21:38:34 -04:00
Tom Rini
e908d20fcb Prepare v2021.10-rc5
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Merge tag 'v2021.10-rc5' into next

Prepare v2021.10-rc5
2021-09-27 09:45:36 -04:00
Patrick Delaunay
b071431d52 mtd: remove SPEAr flash driver st_smi
Remove the driver st_smic.c used in SPEAr products and the associated
config CONFIG_ST_SMI; this driver is no more used in U-Boot after the
commit 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr
support").

Fixes: 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-24 12:09:47 -04:00
Michal Simek
b4c2c151b1 Kconfig: Remove all default n/no options
default n/no doesn't need to be specified. It is default option anyway.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:47:49 -04:00
Tom Rini
4d540a3a81 nand: vf610_nfc: Do not abuse CONFIG namespace
This driver uses the CONFIG namespace to set the chips internal CONFIG
namespace related bits.  However, CONFIG is reserved for the top-level
Kconfig based configuration system.  Use CFG as the namespace here
instead to avoid pollution.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-08-30 14:10:08 -04:00
Tom Rini
0704305528 Merge tag 'u-boot-rockchip-20210812' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Rockchip SFC driver support;
- DTS sync from kernel;
- emmc hs400 support for rk3399;
- Fix for spinore bootdevice and MMC boot order;
2021-08-12 09:33:39 -04:00
Chris Morgan
674a948309 mtd: spi-nor-ids: Add XTX XT25F128B
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12 09:34:11 +08:00
Bin Meng
8fff9e335d mtd: kconfig: Fix CFI_FLASH dependency
The DM version CFI flash driver is in driver/mtd/cfi_flash.c, which
only gets built when FLASH_CFI_DRIVER is on. If CFI_FLASH is on but
FLASH_CFI_DRIVER is not, nothing is enabled at all.

Fix this dependency by selecting FLASH_CFI_DRIVER when CFI_FLASH is
enabled.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11 10:36:10 +02:00
Bin Meng
d008190920 mtd: spi-nor: Mask out fast read if not requested in DT
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property
to indicate that "fast read" opcode can be used to read data from the
chip instead of the usual "read" opcode.

If this property is not present in DT, mask out fast read in
spi_nor_init_params(). This change mirrors the same logic in
spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in
the Linux kernel v5.14-rc3.

[1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-03 11:56:25 +05:30
Bin Meng
87e7219f9c mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's
hwcaps, and only looks to the controller on what can be supported.

The flash's hwcaps needs to be AND'ed before checking.

Fixes: 71025f013c ("mtd: spi-nor-core: Rework hwcaps selection")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-03 11:53:16 +05:30
Reto Schneider
9102cce7f4 mtd: spi-nor-ids: Add support for XMC XM25QH64C
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA
smart gateway.

Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-03 11:46:13 +05:30
Frieder Schrempf
2a79775069 mtd: spi-nor-ids: Add support for Macronix MX25V8035F and MX25R1635F
The MX25V8035F is a 8Mb SPI NOR flash and the MX25R1635F is very
similar, but has twice the size (16Mb) and supports a wider supply
voltage range.

They were tested on the Kontron Electronics i.MX6UL and i.MX8MM SoMs.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-10 15:59:20 +02:00
Tom Rini
570c3dcfc1 arm: Remove spear600 boards and the rest of SPEAr support
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Patrick Delaunay
b953ec2bca dm: define LOG_CATEGORY for all uclass
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Takahiro Kuwano
5b8ec59e2a mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t
Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
1c3dd193b5 mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t
The nor->ready() and spansion_sr_ready() introduced earlier in this
series are used for multi-die package parts.

The nor->quad_enable() sets the volatile QE bit on each die.

The nor->erase() is hooked if the device is not configured to uniform
sectors, assuming it has 32 x 4KB sectors overlaid on bottom address.
Other configurations, top and split, are not supported at this point.
Will submit additional patches to support it as needed.

The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
72151ad10f mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.

Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).

This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode for Cypress chips.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
d2d79895da mtd: spi-nor-core: Read status by Read Any Register
The spansion_sr_ready() reads status register 1 by Read Any Register
commnad. This function is called from Flash specific hook with die address
and dummy cycles to support multi-die package parts from Spansion/Cypress.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
24b1e2c690 mtd: spi-nor-core: Add the ->ready() hook
For dual/quad die package devices from Spansion/Cypress, the device's
status needs to be checked by reading status registers in all dies, by
using Read Any Register command. To support this, a Flash specific hook
that can overwrite the legacy status check is needed.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
a4aa9b7522 mtd: spi-nor-core: Add support for volatile QE bit
Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in CFR1
volatile.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
2d20f34485 mtd: spi-nor-core: Add support for Read/Write Any Register
Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.

The Read Any Register instruction (65h) is followed by register address
and dummy cycles, then the selected register byte is returned.

The Write Any Register instruction (71h) is followed by register address
and register byte to write.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Takahiro Kuwano
c95a914aed mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.

https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)

The full version can be found in the following links (registration
required).
https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522
https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503

S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable
sector architecture. By default, the 512Mb and 1Gb, single-die package
parts are configured to non-uniform that 4KB sectors overlaid on bottom
address. To support this, an erase hook makes overlaid sectors appear as
uniform sectors. The 2Gb, dual-die package parts are configured to uniform
by default.

Tested on Xilinx Zynq-7000 FPGA board.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 19:16:54 +05:30
Pratyush Yadav
f6adec1af4 mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.

Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 12:06:57 +05:30
Pratyush Yadav
ea9a22f7e7 mtd: spi-nor-core: Add support for Cypress Semper flash
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.

The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.

The SFDP programming on some older versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 12:06:43 +05:30
Takahiro Kuwano
ee52b0b764 mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.

The spansion_erase_non_uniform()  erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and remaining normal sectors, by
selecting correct erase command and size based on the address to erase
and size of overlaid portion in parameters. Since different Spansion
flashes can use different opcode for erasing the 4K sectors, the opcode
must be passed in as a parameter based on the flash being used.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
[p.yadav@ti.com: Refactor the function to be compatible with nor->erase,
make 4K opcode customizable, call spi_nor_setup_op() before executing
the op.]
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 12:06:07 +05:30
Pratyush Yadav
aba0bcd7bd mtd: spi-nor-core: allow truncated erases
On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then
256 KiB sectors till the end.

Let the flash-specific erase functions erase less than the requested
length in case of the 4 or 128 KiB sectors and report the number of
bytes erased back to the calling function.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 12:05:38 +05:30
Pratyush Yadav
0be8ab1f16 mtd: spi-nor-core: Perform a Soft Reset on boot
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is

difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.

Further, even if you detect the mode of the flash via SFDP, you still
have the problem of actually reading the ID. The Read ID command is not
standardized across flash vendors. Flashes can have different dummy
cycles needed for reading the ID. Some flashes even expect a 4-byte
dummy address with the Read ID command. All this information cannot be
obtained from the SFDP table.

So, perform a Software Reset sequence before reading the ID and
initializing the flash. A Soft Reset will bring back the flash in its
default protocol mode assuming no non-volatile configuration was set.
This will let us detect the flash even if ROM hands it to us in Octal
DTR mode.

To accommodate cases where there is more than one flash on a board, and
only one of them needs a soft reset, failure to reset is not made fatal,
and we still try to read ID if possible.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 12:05:17 +05:30