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Convert CONFIG_SYS_NAND_MAX_CHIPS to Kconfig
This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_CHIPS Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
1cefed1e39
commit
b2e25afabd
10 changed files with 8 additions and 20 deletions
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@ -111,6 +111,14 @@ config HBMC_AM654
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source "drivers/mtd/nand/Kconfig"
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config SYS_NAND_MAX_CHIPS
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int "NAND max chips"
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depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
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SPL_OMAP3_ID_NAND
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default 1
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help
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The maximum number of NAND chips per device to be supported.
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source "drivers/mtd/spi/Kconfig"
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source "drivers/mtd/ubi/Kconfig"
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@ -423,13 +423,6 @@ config SYS_NAND_BUSWIDTH_16BIT
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not available while configuring controller. So a static CONFIG_NAND_xx
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is needed to know the device's bus-width in advance.
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config SYS_NAND_MAX_CHIPS
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int "NAND max chips"
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default 1
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depends on NAND_ARASAN
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help
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The maximum number of NAND chips per device to be supported.
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if SPL
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config SYS_NAND_5_ADDR_CYCLE
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@ -95,7 +95,6 @@
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/* NAND configuration part */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0x0C000000
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#endif /* __CONFIG_H */
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@ -142,7 +142,6 @@
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/* NAND */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* APBH DMA is required for NAND support */
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#endif
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@ -51,8 +51,6 @@
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#undef CONFIG_SYS_MAX_NAND_DEVICE
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#define CONFIG_SYS_MAX_NAND_DEVICE 3
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#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
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@ -129,7 +129,6 @@
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*/
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#define CONFIG_SYS_NAND_BASE 0xE1000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_NAND_FSL_ELBC
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#define NAND_CACHE_PAGES 64
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@ -33,7 +33,6 @@
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/* When runtime detection fails this is the default */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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/*
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* Ethernet Driver configuration
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@ -78,7 +78,6 @@
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/* nand driver parameters */
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#ifdef CONFIG_TARGET_PRESIDIO_ASIC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#endif
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@ -94,7 +94,6 @@
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
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#define DFU_ALT_INFO_MMC \
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@ -15,11 +15,6 @@
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#ifndef __LINUX_MTD_BBM_H
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#define __LINUX_MTD_BBM_H
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/* The maximum number of NAND chips in an array */
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#ifndef CONFIG_SYS_NAND_MAX_CHIPS
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#endif
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/**
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* struct nand_bbt_descr - bad block table descriptor
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* @options: options for this descriptor
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