Commit graph

1665 commits

Author SHA1 Message Date
Yangbo Lu
8ef0d5c438 armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Shaohui Xie
e82973414d armv8/ls1043a: Add Fman support
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Gong Qianyu
3ad4472923 armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
f3a8e2b7d4 armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
9f3183d2d6 armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Shaohui Xie
8225b2fd87 net: Move some header files to include/
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Mingkai Hu
435acd83b2 armv7/ls1021a: move ns_access to common file
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:58 -07:00
Aneesh Bansal
7bcb0eb285 Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:57 -07:00
Alison Wang
947cee1127 arm: ls1021a: Add QSPI or IFC support in SD boot
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.

This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 09:09:57 -07:00
Anthony Felice
4b8cdd484c vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-16 07:21:09 -04:00
Anthony Felice
42e550d44b vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-16 09:33:26 +02:00
Albert ARIBAUD \\(3ADEV\\)
3f353ceccb vf610: refactor DDRMC code
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-10-02 10:42:31 +02:00
Peng Fan
60dba18801 imx: mx7dsabresd: drop code for CONFIG_CMD_BMODE
We use outer pmic reset and drop internal reset signal, bmode will
not work as expected, so drop boot mode code for 7dsabresd board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Adrian Alonso <aalonso@freescale.com>
2015-09-24 11:32:18 +02:00
Peng Fan
0b530b140a imx: boards: Add maintainers info
Add MAINTAINERS info for mx6slevk_spl, mx6ul_9x9_evk and mx6qpsabreauto.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-24 11:28:59 +02:00
Peng Fan
8e4ba5e0ff imx: mx7dsabresd: drop SYS_SOC from board Kconfig
We have defined this kconfig entry in arch/arm/cpu/armv7/mx7/Kconfig,
no need to redefine it in board Kconfig.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-20 09:57:00 +02:00
Fabio Estevam
07af555513 mx6ul_14x14_evk: Remove get_board_rev()
get_board_rev() is not actually providing the board revision.

It just returns the CPU revision instead.

As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:48:00 +02:00
Fabio Estevam
d547e7ab16 mx6ul_14x14_evk: Staticize when possible
Make the internal symbols static when possible.

This prevents sparse build warnings.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
e9c8f0982d mx6ul_14x14_evk: Remove dead code
iox74lv_set() is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
e0ece17304 mx7dsabresd: Remove get_board_rev()
get_board_rev() is not actually providing the board revision.

It just returns the CPU revision instead.

As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
0df2f01d42 mx7dsabresd: Include USB header
Include <usb/ehci-fsl.h> in order to fix the following sparse warning:

board/freescale/mx7dsabresd/mx7dsabresd.c:538:5: warning: symbol 'board_ehci_hcd_init' was not declared. Should it be static?

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
b7d4db2f96 mx7dsabreasd: Remove dead code
iox74lv_set() is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
72e49e0364 mx7dsabresd: Staticize when possible
Make the internal symbols static when possible.

This prevents sparse build warnings.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Peng Fan
4fae48e8a9 imx: mx7dsabresd set wdog SRS bit
We use trigger pmic reset to reset the board, so set bit SRS to
disable internal WDOG_RESET_B_DEB to make reset stable.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:40:19 +02:00
Fabio Estevam
d6be30fe95 mx6ul_14x14_evk: Add a README file
Add a README file to help users getting started with the board.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-13 10:54:37 +02:00
Peng Fan
f20562e4c4 mx6: remove SYS_SOC from board Kconfig
Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: "Eric Bénard" <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-09-13 10:37:29 +02:00
Peng Fan
d9cbb264e8 imx: mx6ul: support mx6ul 9x9 evk board
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
   supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.

This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
   CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
   part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
   so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
   mx6ul_14x14_evk. And we have no way to dymaically checking this chip
   is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
   POWER related configurations also effect for mx6ul_14x14_evk. But
   power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
   do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
   configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
   according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry

Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C:   ready
DRAM:  256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   FEC1
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-13 10:32:44 +02:00
Adrian Alonso
1a8150d4b1 imx: mx7dsabresd: Add support for MX7D SABRESD board
* Add i.MX7D SABRESD target board support with enabled modules:
  UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.

  Build target: mx7dsabresd_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:54 +02:00
Tom Rini
9809ccdd4c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-09-02 11:30:46 -04:00
Tom Rini
0ffadab1b9 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-09-02 10:39:28 -04:00
Peng Fan
e7d3b21bb7 imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.

Boot Log:

U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)

CPU:   Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
f2ff834365 imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.

Initialize ddr_type for different boards which enable SPL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
0d4cdb5609 imx: mx6ul_14x14_evk add ENET support
Add enet support for mx6ul_14x14_evk board:
1. add pinmux settings
2. implement board_eth_init
3. implement board_phy_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:11 +02:00
Peng Fan
6d97dc10a8 imx: clock support enet2 anatop clock support
To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:29:14 +02:00
Zhuoyu Zhang
03c22449c5 arm/ls102xa:add hwconfig setting to support disable unused devices
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.

For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:49:20 -05:00
York Sun
ec93af0dec armv8/ls2085a_emu: Drop DDR3 emulation target
The emulator with DDR3 model was used during model bringup. DDR4
controllers are used with ls2085a. Drop the DDR4 target defconfig
and enable DDR4 in ls2085a_emu_defconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01 21:39:21 -05:00
Claudiu Manoil
ebe4c1e646 ls102xa: etsec: Use proper settings for BE BDs
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:39:03 -05:00
Prabhakar Kushwaha
cf7ee6c4e3 armv8: ls2085qds: Add support of X-QSGMII-16PORT riser card
The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
interfaces implemented in PCIe form factor board.
It supports followings
 - Card can operate with up to 4 QSGMII lane simultaneously
 - Card can operate with up to 8 SGMII lane simultaneously

Add support of X-QSGMII-16PORT riser card.
This patch also take care of back-ward compatiblity with old SGMII rise cards
used on LS2085QDS Platform.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:38:46 -05:00
Priyanka Jain
7fb79e6552 armv8/ls2085aqds: enable 32KHz rtc output
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:37:42 -05:00
Shengzhou Liu
47deb4b4a9 powerpc/t1023rdb: change default core frequency to 1200MHz
Per new requirement, change default core frequency
from previous 1400MHz to 1200MHz to save power.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 20:58:58 -05:00
York Sun
293194c8be powerpc/defconfig: Rename defconfig file for T1040QDS/T1024QDS DDR4 targets
Previously the DDR4 targets were named with _D4. Rename them with
_DDR4 for easy identification.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01 20:42:54 -05:00
Peng Fan
125914d4be fsl: common: pfuze: no use original pfuze code if DM_PMIC
If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-12 11:05:11 +02:00
Alison Wang
8f0c7cbb0d armv7/ls1021a: allow OCRAM access permission as R/W in SPL
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:37 -07:00
chenhui zhao
933db81c04 armv7/ls1021atwr: program the regulator for deep sleep
Program the external regulator to switch off voltage in deep sleep.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tang Yuantian
99e1bd4241 armv7/ls1021atwr: added deep sleep support in uboot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tom Rini
7a1af7a79b Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-08-02 07:40:37 -04:00
Peng Fan
f0ff57b0b2 imx: mx6ul_14x14_evk add basic board support
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
   supports sd for usdhc2, but can do hardware rework to make usdhc2 support
   emmc.

Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device
 Reset cause: POR
 Board: MX6UL 14x14 EVK
 I2C:   ready
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0, FSL_SDHC: 1
 *** Warning - bad CRC, using default environment

 In:    serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
361b715bbf imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)

CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-02 10:47:52 +02:00
Peng Fan
e6fc8995d6 imx: mx6sabresd/sabreauto runtime setting fdt_file
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.

Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:47:05 +02:00
Priyanka Jain
f2af1c37a0 powerpc/T104xRDB: Remove vbank check redundant code
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:56:11 -07:00
Shengzhou Liu
e04dd12bf1 powerpc/t1023rdb: eMMC boot without external SD card
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:19 -07:00
Shengzhou Liu
ff7ea2d18b powerpc/t1023rdb: add support for T1023RDB RevC
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
73cc2f50eb powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
467a40dfe3 powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Priyanka Jain
fa9ccff835 powerpc/t104x, t102x: Update CPC debug register value in PBI commands
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
Shaohui Xie
f57709ab18 powerpc/t4rdb: fix cpld reset altbank
cpld reset altbank should always reset to bank4 no matter what
current bank is.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
Ying Zhang
01a6113d2a powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.

In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
gaurav rana
e622d9ed3b powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms
defconfig files are added and SFP version for these platforms
is updated.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:14 -07:00
Priyanka Jain
4b6067ae9d powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
    T1040D4RDB is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory
    - Support of 0x66 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 1 SGMII on DTSEC3
    - Support of QE-TDM

    Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
    SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
    - Support of DDR4 memory
    - Support for 0x86 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
    - Support of DIU

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:40:57 -07:00
Fabio Estevam
42acd1874f mx6sxsabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.

Fix the variable type.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-26 12:12:04 +02:00
Fabio Estevam
e4b984d75e mx6sabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.

Fix the variable type.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-26 12:12:04 +02:00
Haikun.Wang@freescale.com
5989df7e2c armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Haikun Wang
e71a980a4d armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Alison Wang
88c857df8c arm/ls102xa: Add little-endian mode support for audio IPs
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Prabhakar Kushwaha
9527931507 board/ls2085rdb: Export functions for standalone AQ FW load apps
Export functions required by Aquntia PHY firmware load application.
functions are memset, strcpy, mdelay, mdio_get_current_dev,
phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Prabhakar Kushwaha
5c05508971 armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr
The agreed split of the top of memory is 256M for debug server and 256M
 for MC. This patch implements the split.

 In addition, the MC mem must be 512MB aligned, so the amount of memory
 to hide must be 512MB to achieve that alignment.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:36 -07:00
Bhupesh Sharma
a2dc818f21 armv8/ls2085a: Expose all DDR region(s) to Linux
This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).

This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
York Sun
fc7b3855e1 armv8/ls2085ardb: Fix SPD address error on early boards
Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20 11:44:35 -07:00
Prabhakar Kushwaha
ff1b8e3f55 armv8/ls2085a: Avoid hard-coding for board name print
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.

Instead of hard-coding, board name should change as per selected
personality.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
Prabhakar Kushwaha
27df54b163 armv8/ls2085RDB: Update board version print logic
As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.

So update board version print logic to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Jaiprakash Singh
b8baf460ee board/fsl/common: Fix eeprom system version endianness
SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.

So use cpu-specific APIs to read SYSTEM version.

Signed-off-by: Jaiprakash Singh <b44839 at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Prabhakar Kushwaha
d7b76e89ed armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI
FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.

Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Prabhakar Kushwaha
94540c5604 armv8/ls2085aqds: Add support of SerDes protocol 0x49
SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.

Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Yangbo Lu
5a4d744c90 armv8/ls2085ardb: add hwconfig setting for eSDHC
Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Prabhakar Kushwaha
3484d95307 armv8/ls2085ardb: Add eth & phy firmware loading support
Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Tom Rini
9bea236b34 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-05-26 10:38:01 -04:00
York Sun
a88cc3bd90 arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
2015-05-20 10:34:09 -07:00
Peng Fan
3fd10f3e25 pmic: pfuze100 fix typo
Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-05-19 15:13:38 +02:00
Jan Kiszka
104d6fb6cd ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:13 -07:00
Shaohui Xie
38289c6945 powerpc/t4240qds: Update RCW, defconfig and maintainer
1. board/freescale/t4qds/t4_rcw.cfg
1.8GHz support is requested as default frequency, so update the rcw.

2. remove un-used configs
configs/T4160QDS_SPIFLASH_defconfig
configs/T4240QDS_SPIFLASH_defconfig
SPI boot is not available on T4QDS, so the configs should be removed.

3. board/freescale/t4qds/MAINTAINERS
Updated MAINTAINERS accordingly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revise subject]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:26:01 -07:00
Shengzhou Liu
c0379b19e2 t2080rdb/rcw: update ddr frequency from 1600MT/s to 1867MT/s
T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s.
So update RCW to support new DDR frequency 1867MT/s by default.
Reserve the old 1600MT/s in comment for users in needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:53 -07:00
Yangbo Lu
5a8dbdc6b4 mmc: fsl_esdhc: Add adapter card type identification support
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
[York Sun: resolve conflicts in README.fsl-esdhc]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:19 -07:00
Shengzhou Liu
fd3a78a538 board/t2080rdb: reset cs4315 phy
CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:12 -07:00
Tang Yuantian
1a56fcea9f fsl/deepsleep: avoid the DDR restore from being optimized out
Function dp_ddr_restore is to restore the first 128-byte space
of DDR. However those codes may be optimized out by compiler
since the destination address is at 0x0. In order to avoid
compiler optimization, we restore the space from high address,
which is not at 0x0, to low address.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:06 -07:00
Shengzhou Liu
ea753267d5 board/t102x: use fdt_setprop_string instead of fdt_setprop
Use fdt_setprop_string instead of fdt_setprop to fix string length.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:50 -07:00
Shengzhou Liu
e8a7f1c32b powerpc/t1023rdb: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.

T1023RDB board Overview
-----------------------
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - one 1G RGMII port on-board(RTL8211F PHY)
  - one 1G SGMII port on-board(RTL8211F PHY)
  - one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR:  128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging

As well updated T1024RDB to add T1023RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix defconfig files]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:31 -07:00
Chunhe Lan
373762c34c powerpc/t4rdb: Add SD boot support for T4240RDB board
This patch adds SD boot support for T4240RDB board. SPL
framework is used. PBL initializes the internal RAM and
copies SPL to it. Then SPL initializes DDR using SPD and
copies u-boot from SD card to DDR, finally SPL transfers
control to u-boot.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: Fix T4240RDB_SDCARD_defcofig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:04 -07:00
York Sun
7fc63cca61 mpc85xx/T4240EMU: Remove T4240EMU board
T4240 SoC has been available for a long time. Emulator support
is no longer needed.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-05-04 09:23:46 -07:00
Tom Rini
e536ab8849 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-04-28 12:15:13 -04:00
Tom Rini
3f6dcdb9cd Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-04-24 13:43:24 -04:00
Scott Wood
32eda7cc94 armv8/ls2085ardb: Enable NAND SPL support
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:51 -07:00
Scott Wood
548cf52fd5 freescale/qixis: Add support for booting from NAND
Use "qixis_reset nand" to reset the board to boot from NAND.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:51 -07:00
Scott Wood
b2d5ac5985 armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Jaiprakash Singh
39b0bbbb23 driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.

FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Prabhakar Kushwaha
e60476a01e board/ls2085qds: Add support ethernet
Add support of ethernet:
 - eth.c: mapping lane to slot for (0x2A, 0x07)
 - ls2085a.c: To enable/disable dpmac and get link type

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Stefan Agner
8b4f9afac0 ARM: vf610: Enable external 32KHz oscillator
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2015-04-23 14:56:08 -04:00
Sanchayan Maity
c7ea243cc0 ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2015-04-23 14:56:08 -04:00
angelo@sysam.it
5296cb1d99 m68k: add architecture-specific u-boot.lds
Add architecture-specific u-boot.lds and remove all board-specific
u-boot.lds.

All the .text customization that was board-specific have been
moved inside the related include/configs, inside a
LDS_BOARD_TEXT define.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2015-04-23 14:56:07 -04:00
York Sun
e2b65ea975 armv8/ls2085ardb: Add support of LS2085ARDB platform
The LS2085ARDB is a evaluation platform that supports LS2085A
family SoCs. This patch add sbasic support for the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-04-23 08:55:58 -07:00
York Sun
7288c2c2b0 armv8/ls2085aqds: Add support of LS2085AQDS platform
The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2015-04-23 08:55:58 -07:00
Scott Wood
b991b981e0 fsl-lsch3: Introduce place for common early SoC init
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:56 -07:00