Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.
Also add debug messages for workarounds and debug registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:
setenv bootmaster PCIE1
saveenv
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:
setenv bootmaster SRIO1
saveenv
The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the "bootmaster" variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to "bootmaster"
based on the using SRIO port.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.
Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:
fsl_cpu_a011:disable
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for. The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Subject slightly changed.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and
TQM860LDB0A3-T50.202 (MPC860T at 50MHz).
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
work with drivers shared with other architecture. However, it is
compiled only if USB is set, but it is required for other drivers
(FSL_ESDHC), too.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Andy Fleming <afleming@gmail.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Marek Vasut <marex@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Added MPC83xx version.
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
powerpc/mpc85xx: Workaround for erratum CPU_A011
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
powerpc/P4080: Check SVR for CPU22 workaround
lib/powerpc: addrmap_phys_to_virt() should return a pointer
powerpc/85xx: clean up P1022DS board configuration header file
powerpc/85xx: fdt_set_phy_handle() should return an error code
powerpc/85xx: minor clean-ups to the P2020DS board header file
powerpc/p1010rdb: add readme document for p1010rdb
powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
powerpc/mpc85xx:Add debugger support for e500v2 SoC
powerpc/85xx:Fix NAND code base to support debugger
powerpc/85xx:Make debug exception vector accessible
powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
powerpc/p1010rdb: update mux config of p1010rdb board
powerpc/mpc85xx:Add BSC9131 RDB Support
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
powerpc/85xx: Add USB device-tree fixup for various platforms
Signed-off-by: Wolfgang Denk <wd@denx.de>
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun <yorksun@freescale.com>
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun <yorksun@freescale.com>
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.
Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.
As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.
2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register
Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
The misspelling of "semiconductor" causes some internal copyright analysis
tools to complain.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:
$ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
Configuring for MPC8572DS board...
make: *** [u-boot] Error 1
powerpc-linux-gnu-size: './u-boot': No such file
e1000.c: In function ‘e1000_initialize’:
e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
tsec.c: In function ‘tsec_initialize’:
tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1
--------------------- SUMMARY ----------------------------
Boards compiled: 1
Boards with errors: 1 ( MPC8572DS )
----------------------------------------------------------
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Fix this:
ether_scc.c: In function 'mpc82xx_scc_enet_initialize':
ether_scc.c:377:14: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:453:15: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:390:15: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
fec.c: In function 'mpc8220_fec_recv':
fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
fec.c: In function 'mpc8220_fec_initialize':
fec.c:839:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Commit db288a9 "net: Remove volatile from net API" caused a number of
build warnings:
fec.c: In function 'fec_initialize':
fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default]
fec.c: In function 'fec_recv':
fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default]
/home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
scc.c: In function 'scc_initialize':
scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default]
Fix these.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
GOT is now handled the way the main u-boot.lds does it. Without this,
the boot hangs when built with newer GCC (since 4.6). Older toolchains
hid the issue by converting -fpic to -fPIC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.
Signed-off-by: Timur Tabi <timur@freescale.com>
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's NOR flash by SRIO
interface, so it can not modify the ENV parameters stored in
master's NOR flash using "saveenv" or other commands.
Master needs to:
1. Put the slave's ENV into it's own memory space.
2. Set an inbound SRIO window covered slave's ENV stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode and ENV from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.
Master needs to:
1. Put the slave's ucode image into it's own memory space.
2. Set an inbound SRIO window covered slave's ucode stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Currently "u-boot", the elf file generated via u-boot-nand.lds does not
contain required debug information i.e. .debug_{line, info, abbrev, aranges,
ranges} into their respective _global_ sections.
The original ld script line arch/powerpc/cpu/mpc85xx/start.o
KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
not process start.o again for bootpg.
So Fix u-boot-nand.lds to generate these debug information.
Signed-off-by: Anmol Paralkar <b07584@freescale.com>
Signed-off-by: John Russo <John.Russo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
NAND SPL code never compile the vector table.
So no need to setup interrupt vector table for NAND SPL.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.
As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00 hard-coded values.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
For e500 and e500v2 architecturees processor IVPR address should be alinged on
64K boundary.
in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
not point to an exception handler.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func. This also fixes the build errors:
ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Some code cleanup done for USB device-tree fixup:
- handling error value returned from fdt_fixup_usb_mode_phy_type()
- using ARRAY_SIZE macro
- using snprintf instead of sprintf
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
It can be handy to have these in the output when trying to
debug odd behaviour.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the current u-boot code, the value of these fields are the reserved
value (0b100), through the signal integrity measurement on freescale's
board with these reserved setting, the signal eye is out of the recommended
spec for non-transition amplitude at 500mV nominal.
According to the errata for MPC8379E, we should make a change to the
recommended setting from essentially nothing at this time to 0b001 for SATA.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Fix:
cpu.c: In function 'checkcpu':
cpu.c:51:7: warning: variable 'ver' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
interactive.c: In function 'fsl_ddr_interactive':
interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR. If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.
Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong. This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman. Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both. A given SOC will only have
a QE or an Fman, so this is safe.
Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND. There's no way to know by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default. So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum A-003474: Internal DDR calibration circuit is not supported
Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.
Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
CCSRBAR + DDR OFFSET + 0xf54
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Make the fixup matchable with dts and kernel. Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency". We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.
We now keep the old interfaces to make previous kernel work. They should
be removed in the future.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum A-003999: Running Floating Point instructions requires special
initialization.
Impact:
Floating point arithmetic operations may result in an incorrect value.
Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Configuring for sbc8349 board...
spd_sdram.c: In function 'spd_sdram':
spd_sdram.c:152:41: warning: variable 'trfc_high' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Fix:
iop480_uart.c: In function 'serial_init':
iop480_uart.c:137:16: warning: variable 'val' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
40x_spd_sdram.c: In function 'spd_sdram':
40x_spd_sdram.c:137:6: warning: variable 'sdram0_b3cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:136:6: warning: variable 'sdram0_b2cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:129:6: warning: variable 'sdram0_ecccfg' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
44x_spd_ddr2.c: In function 'initdram':
44x_spd_ddr2.c:450:17: warning: variable 'dimm_spd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'program_copt1':
44x_spd_ddr2.c:1003:16: warning: variable 'ddrtype' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'DQS_calibration_process':
44x_spd_ddr2.c:2498:7: warning: variable 'window_found' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2497:16: warning: variable 'end_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2496:16: warning: variable 'end_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2495:16: warning: variable 'begin_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2494:16: warning: variable 'begin_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2493:7: warning: variable 'min_end' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
44x_spd_ddr.c: In function 'program_cfg0':
44x_spd_ddr.c:384:16: warning: variable 'dimm_64bit' set but not used [-Wunused-but-set-variable]
44x_spd_ddr.c:383:16: warning: variable 'dimm_32bit' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
cmd_ecctest.c: In function 'inject_ecc_error':
cmd_ecctest.c:116:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]
cmd_ecctest.c: In function 'rewrite_ecc_parity':
cmd_ecctest.c:154:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
4xx_ibm_ddr2_autocalib.c: In function 'get_membase':
4xx_ibm_ddr2_autocalib.c:157:8: warning: variable 'bxcf' set but not used [-Wunused-but-set-variable]
4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB':
4xx_ibm_ddr2_autocalib.c:722:8: warning: variable 'rffd' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
4xx_pcie.c: In function 'pcie_read_config':
4xx_pcie.c:230:6: warning: variable 'address' set but not used [-Wunused-but-set-variable]
4xx_pcie.c: In function 'pcie_write_config':
4xx_pcie.c:290:6: warning: variable 'address' set but not used [-Wunused-but-set-variable]
4xx_pcie.c: In function 'ppc4xx_setup_pcie_rootpoint':
4xx_pcie.c:1066:17: warning: variable 'rmbase' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:756:8: warning: variable 'tdINFO' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:81:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
pci.c: In function 'pci_init_board':
pci.c:55:26: warning: variable 'pci_conf' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 'master' of git://git.denx.de/u-boot-video:
api: export LCD device to external apps
font: split font data from video_font.h
tools: logo: split bmp arrays from bmp_logo.h
lcd: add clear and draw bitmap declaration
VIDEO: mx3fb: GCC4.6 fix build warnings
Powerpc/DIU: Fixed the 800x600 and 1024x768 resolution bug
While video_font.h is useful even without referencing the font data, it
is not possible to be included multiple times because it defines font
data array right in the header.
This patch splits the font data array into video_font_data.h and so now
video_font.h can be included multiple times. This at least solves the
code duplication in board/mcc200/lcd.c.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Remove symbolic link generated by compiling. Fix makefile for out-of-tree
compiling error.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Fix:
ctrl_regs.c: In function 'set_ddr_sdram_cfg_2':
ctrl_regs.c:641:15: warning: variable 'rcw_en' set but not used [-Wunused-but-set-variable]
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:951:31: warning: array subscript is above array bounds [-Warray-bounds]
ctrl_regs.c:752:34: warning: array subscript is above array bounds [-Warray-bounds]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
fsl_corenet_serdes.c: In function 'fsl_serdes_init':
fsl_corenet_serdes.c:511:8: warning: variable 'buf' set but not used [-Wunused-but-set-variable]
fsl_corenet_serdes.c:498:18: warning: variable 'lane_prtcl' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
options.c: In function 'populate_memctl_options':
options.c:486:28: warning: variable 'pdodt' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
fsl_lbc.c: In function 'upmconfig':
fsl_lbc.c:110:9: warning: variable 'mdr' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
tlb.c: In function 'disable_tlb':
tlb.c:175:34: warning: variable '_mas7' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
cpu_init.c: In function 'cpu_init_r':
cpu_init.c:320:7: warning: variable 'l2srbar' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Wrong pointer was being used to copy code into L2SRAM.
Also removed the unreferenced variable l2srbar.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
A few of the config registers changed definition between MMU v1.0 and
MMUv2.0. The new e6500 core from Freescale implements v2.0 of the
architecture.
Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix USB device-fixup warning "node not found". This was occuring
because of static nature of start_offset variable
Static start_offset was storing offset of last node modified, and
was becoming issue if node fixup is carried multiple times,
resulting in "node not found" warning
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On some Freescale systems (e.g. those booted from the on-chip ROM), the
TLB that covers the boot page can also cover CCSR, which breaks the CCSR
relocation code. To fix this, we resize the boot page TLB so that it only
covers the 4KB boot page.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Verify that CCSR is actually located where it is supposed to be before
we relocate it. This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.
Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
spi.c: In function 'spi_init_r':
spi.c:279:22: warning: variable 'cp' set but not used
[-Wunused-but-set-variable]
spi.c: In function 'spi_xfer':
spi.c:361:22: warning: variable 'cp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:109:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
This also fixes some GCC 4.6 build warnings like:
i2c.c: In function 'i2c_init':
i2c.c:221:26: warning: variable 'txbd' set but not used
[-Wunused-but-set-variable]
i2c.c:221:19: warning: variable 'rxbd' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Make (mostly) checkpatch clean (don't convert to use I/O accessors
yet, so there will be "Use of volatile is usually wrong" warnings
left. Also accept some other harmless checkpatch warnings.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Fix:
fec.c: In function 'mpc8220_fec_recv':
fec.c:733:8: warning: variable 'frame' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
speed.c: In function 'get_clocks':
speed.c:113:30: warning: variable 'cpmdf' set but not used
[-Wunused-but-set-variable]
speed.c:113:23: warning: variable 'busdf' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
spi.c: In function 'spi_init_f':
spi.c:144:21: warning: variable 'iop' set but not used
[-Wunused-but-set-variable]
spi.c:142:22: warning: variable 'cpi' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
This also fixes some GCC 4.6 build warnings like:
warning: variable 'txbd' set but not used [-Wunused-but-set-variable]
warning: variable 'rxbd' set but not used [-Wunused-but-set-variable]
Signed-off-by: WOlfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Make (mostly) checkpatch-clean
We don't acctually change the code (like convert to use I/O
accessors), so there will be some remaining "Use of volatile"
warnings from checkpatch.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Fix:
cpu.c: In function 'check_CPU':
cpu.c:188:8: warning: variable 'mid' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
fec.c: In function 'fec_pin_init':
fec.c:381:18: warning: variable 'fecp' set but not used
[-Wunused-but-set-variable]
fec.c: In function 'fec8xx_miiphy_write':
fec.c:1013:8: warning: variable 'rdreg' set but not used
[-Wunused-but-set-variable]
Note: The code was slightly rearranged, but no functional changes
attempted, i. e. no conversion to use I/O accessors.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:751:8: warning: variable 'tdINFO' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:104:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
U-Boot Makefiles contain a number of tests for compiler features etc.
which so far are executed again and again. On some architectures
(especially ARM) this results in a large number of calls to gcc.
This patch makes sure to run such tests only once, thus largely
reducing the number of "execve" system calls.
Example: number of "execve" system calls for building the "P2020DS"
(Power Architecture) and "qong" (ARM) boards, measured as:
-> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board>
-> grep execve /tmp/foo | wc -l
Before: After: Reduction:
==================================
P2020DS 20555 15205 -26%
qong 31692 14490 -54%
As a result, built times are significantly reduced, typically by
30...50%.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Albert Aribaud <albert.aribaud@free.fr>
cc: Graeme Russ <graeme.russ@gmail.com>
cc: Mike Frysinger <vapier@gentoo.org>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
Tested-by: Sanjeev Premi <premi@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Fix:
4xx_pci.c: In function 'pci_init_board':
4xx_pci.c:855:6: warning: variable 'busno' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Fix:
4xx_uart.c: In function 'get_serial_clock':
4xx_uart.c:204:6: warning: variable 'tmp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
interrupts.c: In function 'interrupt_init_cpu':
interrupts.c:62: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
interrupts.c:69: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:72: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:75: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:79: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:83: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
ddr1_dimm_params.c: In function 'compute_ranksize':
ddr1_dimm_params.c:44: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'
ddr2_dimm_params.c: In function 'compute_ranksize':
ddr2_dimm_params.c:43: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'
ddr3_dimm_params.c: In function 'compute_ranksize':
ddr3_dimm_params.c:74: warning: format '%16lx' expects type 'long unsigned int',
but argument 2 has type 'long long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
4xx_pcie.c: In function 'pcie_read_config':
4xx_pcie.c:268: warning: format '%08x' expects type 'unsigned int', but argument
3 has type 'volatile unsigned char *'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB':
4xx_ibm_ddr2_autocalib.c:910: warning: format '%08X' expects type 'unsigned
int', but argument 2 has type 'ulong'
4xx_ibm_ddr2_autocalib.c:911: warning: format '%08X' expects type 'unsigned
int', but argument 2 has type 'ulong'
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
4xx_ibm_ddr2_autocalib.c:1217: warning: format '%08x' expects type 'unsigned
int', but argument 2 has type 'ulong'
4xx_ibm_ddr2_autocalib.c:1230: warning: format '%08x' expects type 'unsigned
int', but argument 2 has type 'ulong'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
44x_spd_ddr.c: In function 'program_tr0':
44x_spd_ddr.c:823: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'long unsigned int'
44x_spd_ddr.c: In function 'program_tr1':
44x_spd_ddr.c:1054: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'long unsigned int'
44x_spd_ddr.c: In function 'program_bxcr':
44x_spd_ddr.c:1127: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 3 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 4 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 5 has
type 'long unsigned int'
44x_spd_ddr.c:1242: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
denali_spd_ddr2.c: In function 'get_spd_info':
denali_spd_ddr2.c:363: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'check_frequency':
denali_spd_ddr2.c:390: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'get_dimm_size':
denali_spd_ddr2.c:473: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:474: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:475: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:476: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_03':
denali_spd_ddr2.c:571: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:604: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:604: warning: format '%d' expects type 'int', but argument 3
has type 'long unsigned int'
denali_spd_ddr2.c:643: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:644: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:645: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:646: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:676: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_04':
denali_spd_ddr2.c:731: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:733: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:735: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_05':
denali_spd_ddr2.c:772: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:774: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_06':
denali_spd_ddr2.c:831: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:833: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_11':
denali_spd_ddr2.c:860: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_26':
denali_spd_ddr2.c:931: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:933: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_27':
denali_spd_ddr2.c:944: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_43':
denali_spd_ddr2.c:978: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_44':
denali_spd_ddr2.c:1006: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
denali_data_eye.c: In function
'denali_core_search_data_eye':denali_spd_ddr2.c:646: warning: format '%d'
expects type 'int', but argument 2 has type 'long unsigned int'
denali_data_eye.c:320: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_data_eye.c:330: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_spd_ddr2.c:676: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_data_eye.c:340: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_data_eye.c:350: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_data_eye.c:360: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
serial.c: In function 'serial_setbrg_dev':
serial.c:143: warning: format '%d' expects type 'int', but argument 4 has type
'long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For P3060 and P4080, USB pins are multiplexed with other functions.
Update the device tree status for USB ports based on setting of
RCW[EC1] & RCW[EC2] which describe if pins are muxed to usb.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch is intended to initialize RMan LIODN related registers on
P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to
qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Update device tree handling for SRIO controller to support updated
fsl,srio device tree binding.
We handle disabling of individual ports, the whole controller, RMU, and
RMAN. Additionally, we setup the SRIO related LIODNs in the device
tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Properly set the LIODN values associated with SRIO controller. On
P4080/P3060 we have an LIODN per port and one for the RMU. On
P2041/P3041/P5020 we have 2 LIODNs per port.
Update the tables for all of these devices to properly handle both
styles.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 'master' of git://git.denx.de/u-boot-fdt:
powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
fdt: update fdt_alloc_phandle to use fdt_get_phandle
fdt: check for fdt errors in fdt_create_phandle
fdt: Add a do_fixup_by_path_string() function
Function fdt_create_phandle() conveniently creates new phandle properties
using both "linux,phandle" and "phandle", so it should be used by all code
that wants to create a phandle.
The Fman firmware code, which embeds an Fman firmware into the device tree,
was creating the phandle properties manually. Instead, change it to use
fdt_create_phandle().
Signed-off-by: Timur Tabi <timur@freescale.com>
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P3041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P5020 has 10 qman portals, we need to configure all of them:
* As there are only 2 physical cores sdest can only be 0 or 1
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We really shouldn't be overwriting bat registers with translation enabled,
especially when we're executing code using one of them for translating
the current instruction stream. Instead, disable address translation
while doing the final BAT setup.
In order to do this, setup_bats has to move back to asm code, because we
require translation to be enabled to have a stack for C code. The yucky
thing about that is that the assembler doesn't like ULL so we have to
switch to using HIGH/LOW pairs for physical addresses that are > 32 bits
in length.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is long over due. All but two net drivers have been converted, but
those have now been dropped.
The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined. So here we scrub the
core code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p3060: Add SoC related support for P3060 platform
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
powerpc/85xx: Refactor some defines out of corenet_ds.h
fm-eth: Add ability for board code to disable a port
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
powerpc/mpc85xxcds: Fix PCI speed
powerpc/mpc8548cds: Fix booting message
powerpc/p4080: Add support for secure boot flow
powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
powerpc/p2041rdb: remove watch dog related codes
powerpc/p2041rdb: updated description of cpld command
powerpc/p2041rdb: add more ddr frequencies support
powerpc/p2041rdb: set sysclk according to status of physical switch SW1
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
powerpc/mpc8xxx: Add DDR2 to unified DDR driver
powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
powerpc/85xx: Enable CMD_REGINFO on corenet boards
powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
powerpc/85xx: Fix USB protocol definitions for P1020RDB
powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
powerpc/mpc8xxx: Move DDR RCW overriding to common code
powerpc/mpc8xxx: Extend CWL table
powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
powerpc/85xx: Cleanup extern in corenet_ds board code
powerpc/p2041rdb: Add ethernet support on P2041RDB board
powerpc/85xx: Add networking support to P1023RDS
powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
powerpc/85xx: Add FMan ethernet support to P4080DS
powerpc/85xx: Add support for FMan ethernet in Independent mode
powerpc/mpc8548cds: Cleanup mpc8548cds.c
powerpc/mp: add support for discontiguous cores
powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
fdt: Add new fdt_create_phandle helper
fdt: Rename fdt_create_phandle to fdt_set_phandle
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
nand: Freescale Integrated Flash Controller NAND support
powerpc/85xx: Add basic support for P1010RDB
powerpc/85xx: Add support for new P102x/P2020 RDB style boards
powerpc/85xx: relocate CCSR before creating the initial RAM area
powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
Add P3060 SoC specific information:cores setup, LIODN setup, etc
The P3060 SoC combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ). This just handles RAID Engine in non-DPAA mode.
Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document.
Any local bus transaction may fail during LBIU resynchronization
process when the clock divider [CLKDIV] is changing. Ensure there
is no transaction on the local bus for at least 100 microseconds
after changing clock divider LCRR[CLKDIV].
Refer to the erratum LBIU3 of mpc8548.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some
early version silicons. The default settings of the DDR IO receiver
biasing may not work at cold temperature. When a failure occurs,
a DDR input latches an incorrect value. The workaround will set the
receiver to an acceptable bias point.
Signed-off-by: Gong Chen
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
(Please note that ISBC expects all these addresses, images to be
validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
at 0xcffffffc.
Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
(The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
created by PBL/configuration word within 0 - 3.5G memory range. The
u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
PBL/configuration word after switch to AS = 1
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The EST SBC8260 is over 10 years old, and the SBC8240 older than
that. With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com
There are some locations in the code which anticipate printf() being called
before the console is ready by squelching printf() on gd->have_console.
Move this squelching into printf(), vprintf(), puts() and putc(). Also
make tstc() and getc() return 0 if console is not yet initialised
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Unified DDR driver is maintained for better performance, robustness and bug
fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of
overall improvement. It requires changes for board files to customize
platform-dependent parameters.
To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx
in the header file. No more boards will be accepted without such definition.
Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1
and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR2 has different ODT table and values. Adding table according to Samsung
application note.
Fix additive latency calculation to avoid interger underflow.
Also converted typedef dynamic_odt_t to struct dynamic_odt.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The two slots on the same controller have different addresses.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Extend CAS write Latency (CWL) table to comply with DDR3 spec
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8536 seems to use only 3 bits for the major revision field in the
SVR rather than the 4 bits used by all other processors. The most
significant bit is used as a mfg code on MPC8536.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration
architecture) is the ethernet contoller block. Normally it is utilized
via Queue Manager (Qman) and Buffer Manager (Bman). However for boot
usage the FMan supports a mode similar to QE or CPM ethernet collers
called Independent mode.
Additionally the FMan block supports multiple 1g and 10g interfaces as a
single entity in the system rather than each controller being managed
uniquely. This means we have to initialize all of Fman regardless of
the number of interfaces we utilize.
Different SoCs support different combinations of the number of FMan as
well as the number of 1g & 10g interfaces support per Fman.
We add support for the following SoCs:
* P1023 - 1 Fman, 2x1g
* P4080 - 2 Fman, each Fman has 4x1g and 1x10g
* P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Dai Haruki <dai.haruki@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The old fdt_create_phandle didn't actually create a phandle it just
set one. We'll introduce a new helper that actually does creation.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Add ifdef protection around fman specific code related to device tree
clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.
Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.
Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.
Impact:
Boot from IFC may not be successful if IFC_CS3 is used.
Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size
Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data
Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.
Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add NAND support (including spl) on IFC, such as is found on the p1010.
Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should
work, as it does not use OOB for anything but ECC.
When hardware ECC is not enabled in CSOR, software ECC is now used.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) structure. This is
called the initial RAM area, or initram. The L1 cache is locked and the TLBs
point to a non-existent address (so that there's no chance it will overlap
main memory or any device). The L1 cache is also configured not to write
out to memory or the L2 cache, so everything stays in the L1 cache.
One of the things we might do while running out of initram is relocate CCSR.
On reset, CCSR is typically located at some high 32-bit address, like
0xfe000000, and this may not be the best place for CCSR. For example, on
36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit
memory space.
On some future Freescale SOCs, the L1 cache will be forced to write to the
backing store, so we can no longer have the TLBs point to non-existent address.
Instead, we will point the TLBs to an unused area in CCSR. In order for this
technique to work, CCSR needs to be relocated before the initram memory is
enabled.
Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs
we create now for relocating CCSR are deleted after the relocation is finished.
cpu_init_early_f() will still need to create a TLB for CCSR (at the new
location) for normal U-Boot purposes. This is done to keep the impact to
existing U-Boot code minimal and to better isolate the CCSR relocation code.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).
Signed-off-by: Stefan Roese <sr@denx.de>
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 files to UTF-8.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board.
This device only supports 800x600 resolution, so if that resolution is selected,
assume that this is the device. The device is attached to the LVDS port
on the P1022DS board.
The existing 800x600 entry (for the PDM360NG board) is actually 800x480,
so we fix that. To support two different 800x resolutions, the Y-resolution
is now passed to fsl_diu_init() and both values are used to pick the proper
fb_videomode structure.
The data for the 800x600 video mode is originally from Jiang Yutang.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
We used <usb.h> for USB_MAX_DEVICE. However this requires we actual
build in support for USB into u-boot (which should not be required for
device tree fixup).
At this time no FSL SoC that utilizies this code (83xx/85xx) has more
than 2 USB controllers. So we replace USB_MAX_DEVICE with a local
define FSL_MAX_NUM_USB_CTRLS.
If/when a device shows up with more than 2 controllers we can easily
bump this value or refactor into a proper define per SoC.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
out if it cannot find 'usb1', so drop the 'else' clause to make driver scan
all the 'usbx'.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Introduce ft_verify_fdt(), a function that is called after the device tree
has been fixed up, that displays warning messages if there is a mismatch
between the physical addresses of some devices that U-Boot has configured
with what the device tree says the addresses are.
This is a particular problem when booting a 36-bit device tree from a
32-bit U-Boot (or vice versa), because the physical address of CCSR is
wrong in the device tree. When the operating system boots, no messages are
displayed, so the user generally has no idea what's wrong.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Current code would print RAM size information like this:
DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Turn a number of printf()s into debug() to get rid of the redundant
"DDR: " string like this:
DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
At some point we broke the detection of e500v1 class cores. Fix that
and simply the code to just utilize PVR_VER() to have a single case
statement.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix up the device tree property associated with the Flexcan clock
frequency. This property is used to calculate the bit timing parameters
for Flexcan.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This provides a function that will override the weak function
flush_icache to let 85xx boards to flush the icache
cc: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However
for the P2040[e] devices that dont support XAUI we handle this at
runtime via SVR checks. If we are on a P2040[e] device the SERDES
functions will behave as follows:
is_serdes_prtcl_valid() will always report invalid if prtcl passed in is
XAUI_FM1.
serdes_get_prtcl() will report NONE if the prtcl in the table is set to
XAUI_FM1.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041 is the superset part that covers both P2040 & P2041. The only
difference between the two devices is that P2041 supports 10g/XAUI and
has an L2 cache.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.
Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch removes the architecture specific implementation of
version_string where possible. Some architectures use a special place
and therefore we provide U_BOOT_VERSION_STRING definition and a common
weak symbol version_string.
Signed-off-by: Andreas Biemann <andreas.devel@googlemail.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Peter Pan <pppeterpppan@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The multi serial support has a "ctlr" field which almost no one uses,
but everyone is forced to set to useless strings. So punt it.
Funny enough, the only code that actually reads this field (the mpc8xx
driver) has a typo where it meant to look for the SCC driver. Fix it
while converting the check to use the name field.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Heiko Schocher <hs@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Tom Rix <Tom.Rix@windriver.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
CC: Craig Nauman <cnauman@diagraph.com>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Prafulla Wadaskar <prafulla@marvell.com>
CC: Mahavir Jain <mjain@marvell.com>
Rather than sticking arch/board/driver specific logic in the common
serial code, push it all out to the respective drivers. The serial
drivers declare these funcs weak so that boards can still override
things with their own definition.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Heiko Schocher <hs@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Tom Rix <Tom.Rix@windriver.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
CC: Craig Nauman <cnauman@diagraph.com>
CC: Prafulla Wadaskar <prafulla@marvell.com>
CC: Mahavir Jain <mjain@marvell.com>
Tested-by: Minkyu Kang <mk7.kang@samsung.com>
This is useful when we just want to wipe out the TLBs. There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function. The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Fman device tree node binding allows for the entire Fman firmware binary
data to be embedded in the device tree. This eliminates the need to have
NOR flash mapped to Linux just so that the Fman driver can see the firmware.
The location of the Fman firmware is taken from the 'fman_ucode' environment
variable.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The ePAPR specification says that phandle properties should be called
"phandle", and not "linux,phandle". To facilitate the migration from
"linux,phandle" to "phandle", we update fdt_qportal() to use the new
function, fdt_create_phandle(). This function abstracts the creation of
phandle properties.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though
enabling a bank causes it to reset. Because the reset was required for
multiple errata, it was not properly enclosed in an #ifdef, and so was
not removed with all the other rev1 errata work-arounds.
Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if
bank 2 is enabled, but this was not being done for SERDES protocols 0xF
and 0x10. The bank reset also happened to enable bank 3 (apparently an
undocumented feature). Simply removing the reset breaks these two
protocols.
It turns out that every time we call enable_bank(), we do want at least
one lane of the bank enabled, either because the bank is supposed to be
enabled, or because we need the clock from that bank enabled.
For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we
call enable_bank(), because that array is used elsewhere to determine if
the bank is available.
Note that the side effect of these changes is that the work-arounds for
these two errata are now linked. Specifically, if SERDES-A001 is
enabled, then we need SERDES-8 enabled as well.
Because this was the only SERDES bank soft-reset, there is no need to
implement a work-around for erratum SERDES-A003.
Also fix an off-by-one error in a printf().
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Ed Swarthout <swarthou@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.
Signed-off-by: York Sun <yorksun@freescale.com>
Modify support for USB mode fixup:
- Add common support for USB mode and phy type
device tree fix-up for all USB controllers
mentioned in hwconfig string
- Fetch USB mode and phy type via hwconfig; if not
defined in hwconfig, then fetch them from env
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to determine the width.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add ifdef protection for qp_info and liodn associated with Q/BMan. Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.
Also add protection around setup_portals() call in corenet_ds board
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add ifdef protection in LBC code to handle the case in which
CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a
build.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On a 8308 based board it was found that the PEX_GLK_RATIO register
(programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This
was tracked to the fact that the pci express clock frequency was not being
assigned to the pciexp1_clk entry in the global data structure in file
arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in
'do_clocks' command.
Signed-off-by: Bill Cook <cook@isgchips.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
CPO value and driver strength settings are board specifc.
Also allow SPD data fetch from any accessible I2C EEPROM.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Running on mpc837x without CONFIG_FSL_ESDHC leads to
i2c1_clk not being set at all. It is bound to clock
of encryption module. fix this.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
