Commit graph

946 commits

Author SHA1 Message Date
Fabio Estevam
af7ec0b058 mx6q: Factor out common DDR3 init code
Factor out common DDR3 initialization code, allowing easier maintainance of such
scripts.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:08 -07:00
Albert ARIBAUD
1c27059a2f Merge remote-tracking branch 'u-boot/master' 2012-09-30 23:49:17 +02:00
Tom Rini
5675b50916 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2012-09-25 12:23:55 -07:00
Fabio Estevam
5436eaeab9 mx28evk: Remove fecmxc_mii_postcall()
fecmxc_mii_postcall() is specific to the KSZ9021 PHY on m28evk and
should not be used on mx28evk, which has LAN8270 instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-24 10:45:41 +02:00
Benoît Thébaudeau
362635bd50 mx51evk: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG
information.

If this data is not present, the kernel misconfigures the TZIC, which results in
the timer interrupt handler never being called, so the kernel deadlocks while
calibrating its delay.

Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-23 19:55:06 +02:00
Tom Rini
495dbd72dd Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-09-21 14:53:13 -07:00
Alison Wang
198cafbf2c ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
a4110eecf2 ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
c6d8863015 ColdFire: Clean up checkpatch warnings for MCF523x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
aa0d99fc28 ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
32dbaafa5a ColdFire: Clean up checkpatch warnings for MCF52x2
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Alison Wang
849fc42471 ColdFire: Clean up checkpatch warnings for MCF5227x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Ira W. Snyder
db1fc7d28e mpc8308rdb: add support for eSDHC MMC controller
Add support for the onboard eSDHC MMC controller. The hardware on the
MPC8308RDB has the following errata:

- ESDHC111: manual asynchronous CMD12 is broken
- DMA is broken (PIO works)

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>

[added include fsl_esdhc header to prevent implicit declarations of
fsl_esdhc_mmc_init() and fdt_fixup_esdhc()]

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-09-18 16:16:45 -05:00
Ira W. Snyder
ea1ea54e35 mpc8308rdb: add support for Spansion SPI flash on header J8
The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.

This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-09-18 16:16:44 -05:00
Fabio Estevam
1d9b033269 mx35pdk: README: Remove NAND references
Booting from NAND is currently not supported, so remove its references.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-17 13:17:17 +02:00
Stefano Babic
3292539e7d MX35: mx35pdk: add support for MMC
Add support for SD card and change the default
environment due to increased u-boot size.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-10 14:32:47 +02:00
Ashok Kumar Reddy
5d20881eec mx6qsabrelite:Use IMX_GPIO_NR Macro
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
2012-09-10 14:25:38 +02:00
Fabio Estevam
ddfcc810d3 mx28evk: Convert to mxs_adjust_memory_params()
Recent conversion from mx28_adjust_memory_params to mxs_adjust_memory_params
missed to update mx28evk, which caused the board not to boot.

Apply the conversion so that the board can boot again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-04 11:57:56 +02:00
Otavio Salvador
4f434e3d6d MX28: mx28evk: Align SSP clock speed
Align the SSP clock speed with oscilator to achieve higher transfer
stability.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-04 11:57:56 +02:00
Benoît Thébaudeau
16e43f354d fsl_esdhc: Remove cache snooping for i.MX
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so
disable it globally for this architecture. This avoids setting no_snoop for all
i.MX boards, and it prevents setting a reserved bit of a reserved register if
fsl_esdhc_mmc_init() is used on i.MX, like in
arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init().

Since no_snoop was only used on i.MX, get rid of it BTW.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
2012-09-01 14:58:30 +02:00
Ashok Kumar Reddy
925507088b mx5:Use IMX_GPIO_NR macro
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
2012-09-01 14:58:30 +02:00
Ashok Kumar Reddy
acbdea2ece mx6qarm2:Use IMX_GPIO_NR macro
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Otavio Salvador
72f8ebf17e mxs: Rename 'mx28_dram_init' to 'mxs_dram_init'
The DRAM initialization, after SPL has complete, is exactly the same
for all mxs SoCs so we should name it accordinly.

The following boards has been changed:

 * apx4devkit
 * m28evk
 * mx28evk
 * sc_sps_1

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
2012-09-01 14:58:28 +02:00
Fabio Estevam
5c8d14dfd9 mx53ard: Use IMX_GPIO_NR macro
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:28 +02:00
Fabio Estevam
5179a26848 mx51evk: Use IMX_GPIO_NR macro
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:28 +02:00
Fabio Estevam
3ef0a312c0 mx53loco: Use IMX_GPIO_NR macro
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:28 +02:00
Stefano Babic
5fecb36ca0 MX: Set a common gpio.h for all i.MX
Each i.MX has its own gpio.h, defining the same structure.
The internal GPIO controller has the same layout
(at least for the register used by u-boot) and can be shared.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Matt Sealey <matt@genesi-usa.com>
2012-09-01 14:58:27 +02:00
Troy Kisky
0aff384b14 mx53evk: add boot_mode support
This allows a watchdog reset to start the ROM's
usb/serial downloader, or boot from an sdcard.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-09-01 14:58:26 +02:00
Troy Kisky
bb05b40b06 mx6qsabrelite: add boot_mode support
This allows a watchdog reset to start the ROM's
usb downloader, or boot from an sdcard.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-09-01 14:58:26 +02:00
Troy Kisky
d1c679a46d iomux: move IOMUX_GPR13_xxx defines
Move mx6 specific defines to arch-mx6 directory.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
34a31bf52b mx35: Fix typo on EDIO
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Marek Vasut
7fb1ed0eab MX28: Move the u-boot.bd info CPUDIR/SOCDIR
This gets us rid of duplication of the same file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:18 +02:00
Fabio Estevam
1e080988d0 mx51evk: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:18 +02:00
Stefano Babic
3e0773708d MX5: mx53loco: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:18 +02:00
Otavio Salvador
1e0cf5c34b mxs: Reowork SPL to use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
9c471142bc mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Scott Wood
d69dba367a powerpc/mpc85xx/p1_p2_rdb: add all LAWs during SPL
LAW init is skipped in the SPL payload because it's assumed that the SPL
has taken care of it -- so make sure the SPL loads all the LAWs as is
done on other boards.

This bug was introduced by:

  commit 4589728e21
  Author: Kumar Gala <galak@kernel.crashing.org>
  Date:   Fri Nov 11 08:14:53 2011 -0600

    powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND

    Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing
    LAW entries not needed during SPL phase.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-08-23 12:49:48 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
Timur Tabi
61fc52b660 powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on.  This is pointless, so remove it.  Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:19 -05:00
Timur Tabi
45b092d301 powerpc/85xx: introduce function serdes_device_from_fm_port()
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Paul Gortmaker
a2af6a7a84 mpc85xx: use LCRR_DBYP define instead of raw constant
Using the raw value of 0x80000000 directly in the code can
lead to "count the zeros" bugs like that fixed in commit
718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC")

Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.

Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Matthew McClintock
c8f9802a72 p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)
There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.

Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bits

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Shaohui Xie
5d898a00f3 powerpc/CoreNet: add tool to support pbl image build.
Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Liu Gang
461632bd71 powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE interface, so it can not modify the ENV parameters stored
	  in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE interface by RCW.
	3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
	1. Updated the README.srio-boot-corenet to add descriptions about
	   boot from PCIE, and change the name to
	   README.srio-pcie-boot-corenet.
	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
	   from PCIE.
	3. Updated other macros and documents if needed to add information
	   about boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:15 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Hongtao Jia
308bc61db7 powerpc/sgmii: To support PHY link state auto detect in SGMII mode
PHYs on SGMII riser card are used in SGMII mode with different external
IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type
under ethernet node should be updated. Otherwise the PHY interrupt can not
be handled therefor PHY link state change can not be auto detected.

For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed
but it's still be kept to guarantee the sgmii mode could work with old
device tree.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:15 -05:00
Shaohui Xie
145dbc0250 powerpc/p2041: configure the CPLD lane_mux according to RCW
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.

Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.

Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:39 -05:00
Timur Tabi
7a946961c7 powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead.  Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:37 -05:00
Matthew McClintock
af2536088e powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.

Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.

Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:37 -05:00
Troy Kisky
9c06782863 mx6qsabrelite: add i2c multi-bus support
This includes bus recovery support.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31 08:01:09 +02:00
Troy Kisky
af2a35fb1f i.mx: iomux-v3.h: move to imx-common include directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:19 +02:00
Wolfgang Denk
b98b611502 Merge branch 'next' of git://git.denx.de/u-boot
* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-30 20:39:52 +02:00
Wolfgang Denk
702e6014f1 doc: cleanup - move board READMEs into respective board directories
Also drop a few files referring to no longer / not yet supported
boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-07-29 15:42:02 +02:00
Wolfgang Denk
00c60f9131 Minor Coding Style Cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-22 21:58:26 +02:00
Fabio Estevam
175a7d2778 mx28evk: Add I2C support
Add I2C support.

Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-11 10:54:53 +02:00
Troy Kisky
3174689be2 mx6qsabrelite: add i2c support
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11 10:54:52 +02:00
Wolfgang Denk
3fe63839f3 Minor Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-10 09:18:33 +02:00
Wolfgang Denk
50cd93b250 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-08 19:26:33 +02:00
Fabio Estevam
f69b0653ac mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
commit acc4959fc1 (Revert "i.MX28: Enable additional DRAM address bits")
broke mx28evk boot.

Fix it by properly adjusting the HW_DRAM_CTL29 register value.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:29 +02:00
Vikram Narayanan
b29da17494 mx6: Avoid writing to read-only bits in imximage.cfg
If in case this is valid according to the latest datasheet, ignore this patch.
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:27 +02:00
Fabio Estevam
001533eb0e mx6qsabrelite: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-07 14:07:27 +02:00
Fabio Estevam
ef0ed6a48d mx6qarm2: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-07 14:07:27 +02:00
Fabio Estevam
cf0a8ec227 mx51evk: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
d0004a687c mx53smd: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
5094fbf79b mx53ard: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
b4896cd618 mx53evk: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
2fb563f2f5 mx53loco: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:26 +02:00
Fabio Estevam
eae08eb2b5 mx53loco: Fix revision of Dialog boards
Original code was assuming that the fuse revision version for all mx53loco boards
based on Dialog PMIC was the same, which is not the case.

Force the revision of all Dialog-based boards to 0.

This fixes a kernel crash when PMIC is accessed in the 2.6.35 kernel
for Dialog rev E boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:25 +02:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Timur Tabi
1fc0d59486 powerpc/85xx: fdt_set_phy_handle() should return an error code
fdt_set_phy_handle() makes several FDT calls that could fail, so it should
not be hiding these errors.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-07-06 17:30:32 -05:00
Shengzhou Liu
d3de823e54 powerpc/p1010rdb: add readme document for p1010rdb
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2012-07-06 17:30:31 -05:00
Shengzhou Liu
487e8abbaa powerpc/p1010rdb: update mux config of p1010rdb board
On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2012-07-06 17:30:29 -05:00
Prabhakar Kushwaha
7530d341c7 powerpc/mpc85xx:Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
 is an integrated device that targets Femto base station market. It combines
 Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
 MAPLE-B2F baseband acceleration processing elements

  BSC9131RDB Overview
   -----------------
     -1Gbyte DDR3 (on board DDR)
     -128Mbyte 2K page size NAND Flash
     -256 Kbit M24256 I2C EEPROM
     -128 Mbit SPI Flash memory
     -USB-ULPI
     -eTSEC1: Connected to RGMII PHY
     -eTSEC2: Connected to RGMII PHY
     -DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.

This patch adds support for mainly Power side functionalities and peripherals

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:29 -05:00
ramneek mehresh
3d7506fa38 powerpc/85xx: Add USB device-tree fixup for various platforms
Add USB device-tree fixup for following platforms:
MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-07-06 17:03:25 -05:00
Fabio Estevam
f714b0a911 mx53loco: Add LCD support
Add support for CLAA07LC0ACW LCD that connects to the mx53loco board.

Configure the board to show the Linux logo on the LCD.

Also increase the size of CONFIG_SYS_MALLOC_LEN variable to take into account
the framebuffer usage.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-05-25 10:40:32 +02:00
Fabio Estevam
a1b0e190a3 mx5: Rename mx51_fb_init()
The ipuv3 driver is currently only used on mx51, but it can be extended to work
on mx53 and mx6 as well.

Rename mx51_fb_init(), so that it can be used by other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-05-25 10:39:23 +02:00
Fabio Estevam
f1adefd239 mx51evk: Add LCD support
Add support for CLAA07LC0ACW LCD that connects to the mx51evk board.

Configure the board to show the Linux logo on the LCD.

Also increase the size of CONFIG_SYS_MALLOC_LEN variable to take into account
the framebuffer usage.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-25 10:06:38 +02:00
Fabio Estevam
6ecaee8201 mx53loco: Remove unneeded gpio_set_value()
There is no need to set the VBUS power enable to 0 first and then to 1.

Set it to 1 in the gpio_direction_output() function.

While at it, use the standard naming convention for the GPIO comment.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:34 +02:00
Fabio Estevam
54cd1dee8f mx53loco: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.

The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.

Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
768a059710 mx53loco: Turn on VUSB regulator
On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator
so that the mx53 USBH1 PHY receives the 3.3V voltage.

Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the
commands:

usb start

usb info

,which correctly detected and printed the USB pen drive information.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
5b547f3c20 mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
ed5157e889 pmic: dialog: Avoid name conflicts
As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC,
we need to be able to build both drivers.

Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Eric Nelson
3996a96c5e i.MX6: mx6q_sabrelite: add SATA bindings
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: stefano Babic <sbabic@denx.de>
2012-05-15 08:31:33 +02:00
Lauri Hintsala
ecb7be2985 mx28evk: add NAND support
NAND support is not enabled by default because Eval Kit is not delivered
with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config.

Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-05-15 08:31:33 +02:00
Fabio Estevam
e7e337227b mx53loco: Add support for 1GHz operation for DA9053-based boards
There are two types of mx53loco boards: initial boards were built with a Dialog
DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC.

Add DA9053 PMIC support and adjust the required voltages and clocks for running
the CPU at 1GHz.

Tested on both versions of mx53loco boards.

In the case of a MC34708-based board the CPU operating voltage remains at 800MHz.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by : Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Fabio Estevam
1fc56f1cb0 mx53loco: Allow to print CPU information at a later stage
Print CPU information within board_late_init().

This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Eric Nelson
28fdbddc94 i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
Uses the 'magic_keys' idiom as described in doc/README.kbd:
	http://lists.denx.de/pipermail/u-boot/2012-April/122502.html

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Fabio Estevam
bdb9f7604d mx6qsabrelite: No need to set the direction for GPIO3_23 again
There is a 'gpio_direction_output(87, 0);' call previously, so the GPIO direction is
already established.

Use gpio_set_value() for changing the GPIO output then.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
2012-05-15 08:31:31 +02:00
Stefano Babic
f92e4e6c19 MX53: mx53loco: Add SATA support
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
2012-05-15 08:31:31 +02:00
Timur Tabi
5d065c3e10 powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time.  The board-specific code is
deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:34 -05:00
Liu Gang
3f1af81b80 powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
292dc6c501 powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
York Sun
1ba62f1017 powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Chunhe Lan
617e46e3c0 powerpc/p1023rds: Disable nor flash node and enable nand flash node
In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.

Default device tree nor and nand node should have the following structure:

	Example:

		nor_flash: nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x02000000>;
			bank-width = <2>;
			device-width = <1>;
			status = "okay";

			partition@0 {
				label = "ramdisk";
				reg = <0x00000000 0x01c00000>;
			};
		}

		nand_flash: nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1023-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x00040000>;
			status = "disabled";

			u-boot-nand@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				read-only;
			};
		}

When booting from nor flash, the status of nor node is enabled and the
status of nand node is disabled in the default dts file, so do not do
anything.

But, when booting from nand flash, need to do some operations:

	o Disable the NOR node by setting status = "disabled";
	o Enable the NAND node by setting status = "okay";

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Dirk Behme
03f3587822 i.MX6: arm2: Add AXI cache and Qos setting
Do the same AXI cache and Qos settings done already in the
SabreLite imximage.cfg for the ARM2 board, too.

It fixes a display flash issue caused by low priority of
the display IDMA channel.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-04-17 15:41:22 +02:00
Wolfgang Denk
f5cdc11775 Prepare v2012.04-rc2; minor Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-04-16 23:13:51 +02:00
Stefano Babic
2f002eceae MX35: mx35pdk: wrong board revision
The board revision is detected accessing to the pmic,
that is not available before relocation (I2C).
This generates the following error:

CPU:   Freescale i.MX35 rev 2.0 at 532 MHz.
Reset cause: WDOG
<reg num> = 7 is invalid. Should be less than 0
Board: MX35 PDK 1.0

The revision number is wrong, as a default value is printed
(tested on a mx35pdk Rev. 2.0).

Move the output in the board_late_init(), when
pmic can be accessed.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-04-16 14:53:59 +02:00
Stefano Babic
d0f5600f54 MX31: mx31pdk: drop enable_caches from board file
enable_caches() is implemented now in cpu.c for
ARM1136.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:59 +02:00
Troy Kisky
1482410531 MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:58 +02:00
Fabio Estevam
19db9be4aa mx53ard: Initialize return code with error
The variable "rc" is the return of board_eth_init() function. Initialize
it with an error code, so that this function can return an error when
CONFIG_SMC911X is not set.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-03-27 09:41:17 +02:00