Commit graph

84781 commits

Author SHA1 Message Date
Chris Morgan
02cbda2b72 dts: rockchip: px30: add gpio-ranges property to gpio nodes
Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".

Fixes: 537b1a2774 ("rockchip: add px30 devicetrees")

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
904b8700f8 gpio: gpio-rockchip: parse gpio-ranges for bank id
Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Manoj Sai
5aedc8bf0f rk3566: radxa-cm3: Enable USB2.0, USB3.0 support
=> usb start
starting USB...
Bus usb@fd000000: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd800000: USB EHCI 1.00
scanning bus usb@fd000000 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning bus usb@fd800000 for devices... 4 USB Device(s) found
       scanning usb for storage devices... 2 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Mass Storage (5 Gb/s, 224mA)
       SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5

  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 100mA)
    |   USB 2.0 Hub
    |
    +-3  Mass Storage (480 Mb/s, 500mA)
    |    JetFlash Mass Storage Device 19M7I4ZQFTSC08SU
    |
    +-4  Human Interface (12 Mb/s, 98mA)
         Logitech USB Receiver

Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Manoj Sai
2c99198574 rockchip: rk3568: Select DM_REGULATOR_FIXED
Select the DM_REGULATOR_FIXED on RK3568 platform.

Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
1977d746aa rockchip: rk3568: add rk3568 pinctrl driver
Add driver supporting pin multiplexing on rk3568 platform.

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
3abfd33e57 arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates
combphy1 is failing to probe due to unhandled assigned-clocks and
assigned-clocks-rates.

=> usb start
starting USB...
Bus usb@fd000000: Failed to get PHY1 for usb@fd000000
Port not available.
Bus usb@fd800000: USB EHCI 1.00

There is no real requirement for them in U-Boot to handle, hence
mark them as deleted-properties for the  probe to success

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
82220526ac drivers: phy: add naneng combphy for rk3568
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Manoj Sai
3da15f0b49 phy: rockchip-inno-usb2: Add USB2 PHY for rk3568
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.

However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.

This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.

Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Co-developed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
d538efb9ad phy: rockchip: inno-usb2: Add support #address_cells = 2
New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only
use 32 bit addresses.

Adjust the driver to check if the returned address is "0", and adjust
the index in that case.

Derived and adjusted the similar change from linux-next with below
 commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support
 #address_cells = 2")

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
3dd126155c board: rockchip: Add Radxa Compute Module 3 IO Board
Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
3356c67d1f arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO
Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.

Specification:
- 1x HDMI,
- 2x MIPI DSI
- 2x MIPI CSI2
- 1x eDP
- 1x PCIe card
- 2x SATA
- 2x USB 2.0 Host
- 1x USB 3.0
- 1x USB 2.0 OTG
- Phone jack
- microSD slot
- 40-pin GPIO expansion header
- 12V DC

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

linux-next commit for the same,

commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")

Add support for Radxa CM3 IO Board.

Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jagan Teki
63391b198a arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3
Radxa Compute Module 3(CM3) is one of the modules from a series
System On Module based on the Radxa ROCK 3 series and is compatible
with Raspberry Pi CM4 pinout and form factor.

Specification:
- Rockchip RK3566
- up to 8GB LPDDR4
- up to 128GB high performance eMMC
- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
  BT 5.0, BLE with onboard and external antenna.
- Gigabit Ethernet PHY

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.

linux-next commit for the same,

commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")

Add support for Radxa CM3.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28 18:07:26 +08:00
Jagan Teki
1bb92d7cb3 dt-bindings: rockchip: Sync rockchip, vop2.h from Linux
Sync rockchip,vop2.h from linux-next, and the last commit is

commit <604be85547ce> ("drm/rockchip: Add VOP2 driver")

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28 18:07:26 +08:00
Jagan Teki
5f5b1cf3ff rockchip: rk3568: Move DM_RESET in arch kconfig
Like other rockchip SoCs, DM_RESET is useful across rk3568
platform.

Select it from arch kconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jagan Teki
165bc9cccf board: edgeble: Fix neural-compute-module-2 board name
The board should be RV1126-NEU2 instead RV1126-ECM0.

Fix the wrong name.

Fixes: b8f1ca9540 ("board: rockchip: Add Edgeble Neu2 IO Board")
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Christopher Obbard
13d819c04a include: rk3328: Add default env for compressed kernel images
Add default memory addresses for kernel_comp_addr_r and kernel_comp_size
to enable booting from a compressed kernel image. This area is temporarily
used to decompress the kernel image on-the-fly.

Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Akash Gajjar
6cd6ed9da5 arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.

ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply

Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")

Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Akash Gajjar
b44c54f600 arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7

Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A

Refer Linux commit <22a442e6586c>
("arm64: dts: rockchip: add basic dts for the radxa rock3 model a")

Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
40389c2a46 binman: Mark mkimage entry missing when its subnodes is missing
Using the mkimage entry with the multiple-data-files prop and having a
missing external blob result in an unexpected ValueError exception using
the --allow-missing flag.

  ValueError: Filename 'missing.bin' not found in input path (...)

Fix this by using _pathname that is resolved by ObtainContents for blob
entries, ObtainContents also handles allow missing for external blobs.

Mark mkimage entry as missing and return without running mkimage when
missing entries is reported by CheckMissing.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
5fc5a840d4 rockchip: mkimage: Update init size limit for RK3568
The current init size limit of 76KiB is too big to fit in the 64KiB SRAM
on RK3568, sync init size limit from vendor u-boot to fix this.

Set init size limit to 60KiB (-16KiB) for RK3568.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
ed8d098300 rockchip: mkimage: Update init size limit for RK3328
Latest vendor TPL for RK3328 has grown past the current init size limit
of 28KiB, sync the init size limit from vendor u-boot to fix this.

Set init size limit to 30KiB (+2KiB) for RK3328.

This makes it possible to use latest vendor TPL on RK3328 without
getting a size limit error running the mkimage command.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
d1bdffa8a2 Revert "board: rockchip: Fix binman_init failure on EVB-RK3568"
An external TPL binary is now expected to be provided using ROCKCHIP_TPL
when building RK3568 targets.

This reverts commit 31500e7bcf.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
4773e9d5ed rockchip: Use an external TPL binary on RK3568
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
jumps to U-Boot SPL to continue the normal boot flow.

However, there is no support to initialize DRAM on RK35xx SoCs using
U-Boot TPL and instead an external TPL binary must be used to generate a
bootable u-boot-rockchip.bin image.

Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
bootable u-boot-rockchip.bin image for RK3568.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
05b978be5f binman: Add support for a rockchip-tpl entry
The rockchip-tpl entry can be used when an external TPL binary should be
used instead of the normal U-Boot TPL.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
f0498b2be2 rockchip: dts: rk3328: fix sdram params
The rk3328 sdram driver read sdram parameters from the devicetree into a
struct rk3328_sdram_params using dev_read_u32_array.

After commit 5ab30c3176 ("ram: rockchip: Update ddr pctl regs for px30")
changed the size of struct ddr_pctl_regs, a member of struct
rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328.

Add ten u32 to the sdram parameter array in devicetree to align with
this size change. This fixes DRAM initialization on RK3328.

Fixes: 5ab30c3176 ("ram: rockchip: Update ddr pctl regs for px30")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc
2023-02-28 18:07:26 +08:00
Jonas Karlman
2ec15cabe9 rockchip: sdram: add dram bank with usable memory beyond 4GB
Add a second dram bank of usable memory beyond the blob of space for
peripheral near 4GB. Any memory that exists beyond the 4GB mark is added
to the second bank.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
bde73b14f0 rockchip: sdram: add basic support for sdram reg info version 3
Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.

Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.

This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.

Details on the new format was deciphered from vendor u-boot commit [1].

[1] c69667e0e2

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Quentin Schulz
5bb4697ca3 rockchip: ringneck: fix SDRAM init fail
CONFIG_RAM_PX30_DDR4 got renamed to CONFIG_RAM_ROCKCHIP_DDR4 in commit
26f92be07e ("ram: rockchip: Add common ddr type configs"). Since both
patchsets were merged unbeknownst to the other, the conflict wasn't
detected while testing each patchset individually and could only be
observed after a merge to master branch.

Fixes: c925be73a0 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
John Keeping
ea0f766253 mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handling
The RK3288 TRM states that, for 8-bit DDR modes:

	The CLKDIV register should always be programmed with a value
	higher than zero (0); that is, a clock divider should always be
	used for 8-bit DDR mode.

In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.

Add the necessary code to double the clock frequency when 8-bit DDR is
selected.  The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-28 18:07:26 +08:00
Christian Kohlschütter
2492ba8a3b arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfo
Provide human-readable manufacturer and product names for the
FriendlyELEC NanoPi R4S.

Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default.

Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Tom Rini
e8c80ac0f7 Prepare v2023.04-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-27 17:18:36 -05:00
Tom Rini
2a433a5b53 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-27 09:11:57 -05:00
Tom Rini
0024e7f72b Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra 2023-02-23 17:40:18 -05:00
Tom Rini
0b58258a33 Merge branch '2023-02-23-assorted-fixes'
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally,
  relax one of the trace test time requirements (so CI doesn't fail due
  to test being slightly slow, but still correct), and correct env on
  MMC and checking for where GPT can be
2023-02-23 17:30:49 -05:00
Svyatoslav Ryhel
5a8fe1ee81 ARM: tegra20: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypt BCT.

Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Ramin Khonsari
327ff8e0a4 ARM: tegra30: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypted BCT.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
bab087802a ARM: tegra: crypto: extend crypto functional
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
8ed2bd1d1b ARM: tegra: expose crypto module for all Tegra SoCs
Move crypto module from T20 only into common Tegra dir.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
5668c75ce9 board: tegra30: switch to updated pre-dm i2c write
Configure PMIC voltages for early stages using updated
early i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
e7184debf4 board: tegra124: switch to updated pre-dm i2c write
Configure PMIC for early stages using updated i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
4213d52b33 ARM: tegra: create common pre-dm i2c write
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.

Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
1a7ce63c08 ARM: tegra: add late init support
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Maxim Schwalm
b1de4d7c6e ARM: tegra: provide default USB gadget setup
All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.

Inspired by commit e02687bda9 ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.

Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
09ca4d8028 spi: tegra20_slink: accept any word length
Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
23d24df34c ARM: tegra: Fix Tegra PWM parent clock
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
678157e212 ARM: tegra30: add PLLD to pll setup
On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
a81d792479 ARM: tegra: clock: add clock_decode_pair helper
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
65e02744ec ARM: tegra: clock: add clk_id_to_pll_id helper
This function allows to convert a device tree clock ID to PLL ID.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
2fafac30ef ARM: t20/t30: swap host1x and disp1 clock parents
According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
fca18a2643 tegra30: clock: add EXTPERIPH
This mappings were missing for some reason.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00