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ram: rockchip: Add common ddr type configs

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We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.

The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2022-12-14 23:20:48 +05:30 committed by Kever Yang
parent 78276c5313
commit 26f92be07e
15 changed files with 33 additions and 36 deletions
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2
board/engicam/px30_core/Kconfig
View file

@ -11,6 +11,6 @@ config SYS_CONFIG_NAME
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RAM_PX30_DDR4
select RAM_ROCKCHIP_DDR4
endif

2
configs/khadas-edge-captain-rk3399_defconfig
View file

@ -53,7 +53,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

2
configs/khadas-edge-rk3399_defconfig
View file

@ -52,7 +52,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

2
configs/khadas-edge-v-rk3399_defconfig
View file

@ -53,7 +53,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

2
configs/leez-rk3399_defconfig
View file

@ -48,7 +48,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

2
configs/nanopi-r4s-rk3399_defconfig
View file

@ -49,7 +49,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

2
configs/pinebook-pro-rk3399_defconfig
View file

@ -74,7 +74,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y

2
configs/roc-pc-mezzanine-rk3399_defconfig
View file

@ -69,7 +69,7 @@ CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2

2
configs/roc-pc-rk3399_defconfig
View file

@ -68,7 +68,7 @@ CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y

2
configs/rock-pi-4-rk3399_defconfig
View file

@ -64,7 +64,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2

2
configs/rock-pi-4c-rk3399_defconfig
View file

@ -64,7 +64,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2

2
configs/rockpro64-rk3399_defconfig
View file

@ -71,7 +71,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y

32
drivers/ram/rockchip/Kconfig
View file

@ -11,9 +11,10 @@ config ROCKCHIP_SDRAM_COMMON
help
This enable sdram common driver
if RAM_ROCKCHIP
config RAM_ROCKCHIP_DEBUG
bool "Rockchip ram drivers debugging"
depends on RAM_ROCKCHIP
default y
help
This enables debugging ram driver API's for the platforms
@ -22,31 +23,28 @@ config RAM_ROCKCHIP_DEBUG
This is an option for developers to understand the ram drivers
initialization, configurations and etc.
config RAM_PX30_DDR4
bool "DDR4 support for Rockchip PX30"
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
config RAM_ROCKCHIP_DDR4
bool "DDR4 support for Rockchip SoCs"
help
This enables DDR4 sdram support instead of the default DDR3 support
on Rockchip PC30 SoCs.
on Rockchip SoCs.
config RAM_PX30_LPDDR2
bool "LPDDR2 support for Rockchip PX30"
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
config RAM_ROCKCHIP_LPDDR2
bool "LPDDR2 support for Rockchip SoCs"
help
This enables LPDDR2 sdram support instead of the default DDR3 support
on Rockchip PC30 SoCs.
on Rockchip SoCs.
config RAM_PX30_LPDDR3
bool "LPDDR3 support for Rockchip PX30"
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
config RAM_ROCKCHIP_LPDDR3
bool "LPDDR3 support for Rockchip SoCs"
help
This enables LPDDR3 sdram support instead of the default DDR3 support
on Rockchip PC30 SoCs.
on Rockchip SoCs.
config RAM_RK3399_LPDDR4
bool "LPDDR4 support for Rockchip RK3399"
depends on RAM_ROCKCHIP && ROCKCHIP_RK3399
config RAM_ROCKCHIP_LPDDR4
bool "LPDDR4 support for Rockchip SoCs"
help
This enables LPDDR4 sdram code support for the platforms based
on Rockchip RK3399 SoC.
on Rockchip SoCs.
endif # RAM_ROCKCHIP

6
drivers/ram/rockchip/sdram_px30.c
View file

@ -125,11 +125,11 @@ u32 addrmap[][8] = {
struct dram_info dram_info;
struct px30_sdram_params sdram_configs[] = {
#if defined(CONFIG_RAM_PX30_DDR4)
#if defined(CONFIG_RAM_ROCKCHIP_DDR4)
#include "sdram-px30-ddr4-detect-333.inc"
#elif defined(CONFIG_RAM_PX30_LPDDR2)
#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR2)
#include "sdram-px30-lpddr2-detect-333.inc"
#elif defined(CONFIG_RAM_PX30_LPDDR3)
#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR3)
#include "sdram-px30-lpddr3-detect-333.inc"
#else
#include "sdram-px30-ddr3-detect-333.inc"

7
drivers/ram/rockchip/sdram_rk3399.c
View file

@ -1625,7 +1625,7 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
}
#if !defined(CONFIG_RAM_RK3399_LPDDR4)
#if !defined(CONFIG_RAM_ROCKCHIP_LPDDR4)
static int data_training_first(struct dram_info *dram, u32 channel, u8 rank,
struct rk3399_sdram_params *params)
{
@ -2558,8 +2558,7 @@ static int lpddr4_set_rate(struct dram_info *dram,
return 0;
}
#endif /* CONFIG_RAM_RK3399_LPDDR4 */
#endif /* CONFIG_RAM_ROCKCHIP_LPDDR4 */
/* CS0,n=1
* CS1,n=2
@ -3059,7 +3058,7 @@ static int conv_of_plat(struct udevice *dev)
#endif
static const struct sdram_rk3399_ops rk3399_ops = {
#if !defined(CONFIG_RAM_RK3399_LPDDR4)
#if !defined(CONFIG_RAM_ROCKCHIP_LPDDR4)
.data_training_first = data_training_first,
.set_rate_index = switch_to_phy_index1,
.modify_param = modify_param,